| Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1 | /* |
| 2 | * include/asm-sh/watchdog.h |
| 3 | * |
| 4 | * Copyright (C) 2002, 2003 Paul Mundt |
| 5 | * |
| 6 | * This program is free software; you can redistribute it and/or modify it |
| 7 | * under the terms of the GNU General Public License as published by the |
| 8 | * Free Software Foundation; either version 2 of the License, or (at your |
| 9 | * option) any later version. |
| 10 | */ |
| 11 | #ifndef __ASM_SH_WATCHDOG_H |
| 12 | #define __ASM_SH_WATCHDOG_H |
| 13 | #ifdef __KERNEL__ |
| 14 | |
| 15 | #include <linux/types.h> |
| 16 | #include <linux/config.h> |
| 17 | #include <asm/cpu/watchdog.h> |
| 18 | #include <asm/io.h> |
| 19 | |
| 20 | /* |
| 21 | * See asm/cpu-sh2/watchdog.h for explanation of this stupidity.. |
| 22 | */ |
| 23 | #ifndef WTCNT_R |
| 24 | # define WTCNT_R WTCNT |
| 25 | #endif |
| 26 | |
| 27 | #ifndef WTCSR_R |
| 28 | # define WTCSR_R WTCSR |
| 29 | #endif |
| 30 | |
| 31 | #define WTCNT_HIGH 0x5a |
| 32 | #define WTCSR_HIGH 0xa5 |
| 33 | |
| 34 | #define WTCSR_CKS2 0x04 |
| 35 | #define WTCSR_CKS1 0x02 |
| 36 | #define WTCSR_CKS0 0x01 |
| 37 | |
| 38 | /* |
| 39 | * CKS0-2 supports a number of clock division ratios. At the time the watchdog |
| 40 | * is enabled, it defaults to a 41 usec overflow period .. we overload this to |
| 41 | * something a little more reasonable, and really can't deal with anything |
| 42 | * lower than WTCSR_CKS_1024, else we drop back into the usec range. |
| 43 | * |
| 44 | * Clock Division Ratio Overflow Period |
| 45 | * -------------------------------------------- |
| 46 | * 1/32 (initial value) 41 usecs |
| 47 | * 1/64 82 usecs |
| 48 | * 1/128 164 usecs |
| 49 | * 1/256 328 usecs |
| 50 | * 1/512 656 usecs |
| 51 | * 1/1024 1.31 msecs |
| 52 | * 1/2048 2.62 msecs |
| 53 | * 1/4096 5.25 msecs |
| 54 | */ |
| 55 | #define WTCSR_CKS_32 0x00 |
| 56 | #define WTCSR_CKS_64 0x01 |
| 57 | #define WTCSR_CKS_128 0x02 |
| 58 | #define WTCSR_CKS_256 0x03 |
| 59 | #define WTCSR_CKS_512 0x04 |
| 60 | #define WTCSR_CKS_1024 0x05 |
| 61 | #define WTCSR_CKS_2048 0x06 |
| 62 | #define WTCSR_CKS_4096 0x07 |
| 63 | |
| 64 | /** |
| 65 | * sh_wdt_read_cnt - Read from Counter |
| 66 | * |
| 67 | * Reads back the WTCNT value. |
| 68 | */ |
| 69 | static inline __u8 sh_wdt_read_cnt(void) |
| 70 | { |
| 71 | return ctrl_inb(WTCNT_R); |
| 72 | } |
| 73 | |
| 74 | /** |
| 75 | * sh_wdt_write_cnt - Write to Counter |
| 76 | * |
| 77 | * @val: Value to write |
| 78 | * |
| 79 | * Writes the given value @val to the lower byte of the timer counter. |
| 80 | * The upper byte is set manually on each write. |
| 81 | */ |
| 82 | static inline void sh_wdt_write_cnt(__u8 val) |
| 83 | { |
| 84 | ctrl_outw((WTCNT_HIGH << 8) | (__u16)val, WTCNT); |
| 85 | } |
| 86 | |
| 87 | /** |
| 88 | * sh_wdt_read_csr - Read from Control/Status Register |
| 89 | * |
| 90 | * Reads back the WTCSR value. |
| 91 | */ |
| 92 | static inline __u8 sh_wdt_read_csr(void) |
| 93 | { |
| 94 | return ctrl_inb(WTCSR_R); |
| 95 | } |
| 96 | |
| 97 | /** |
| 98 | * sh_wdt_write_csr - Write to Control/Status Register |
| 99 | * |
| 100 | * @val: Value to write |
| 101 | * |
| 102 | * Writes the given value @val to the lower byte of the control/status |
| 103 | * register. The upper byte is set manually on each write. |
| 104 | */ |
| 105 | static inline void sh_wdt_write_csr(__u8 val) |
| 106 | { |
| 107 | ctrl_outw((WTCSR_HIGH << 8) | (__u16)val, WTCSR); |
| 108 | } |
| 109 | |
| 110 | #endif /* __KERNEL__ */ |
| 111 | #endif /* __ASM_SH_WATCHDOG_H */ |