blob: 02f015fc3ed299e7760b874de191f4fd9ea4ea16 [file] [log] [blame]
Steve Wisecfdda9d2010-04-21 15:30:06 -07001/*
2 * Copyright (c) 2009-2010 Chelsio, Inc. All rights reserved.
3 *
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
9 *
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
12 * conditions are met:
13 *
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
16 * disclaimer.
17 * - Redistributions in binary form must reproduce the above
18 * copyright notice, this list of conditions and the following
19 * disclaimer in the documentation and/or other materials
20 * provided with the distribution.
21 *
22 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
23 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
24 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
25 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
26 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
27 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
28 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
29 * SOFTWARE.
30 */
31#ifndef __IW_CXGB4_H__
32#define __IW_CXGB4_H__
33
34#include <linux/mutex.h>
35#include <linux/list.h>
36#include <linux/spinlock.h>
37#include <linux/idr.h>
Steve Wisec3373742011-05-20 16:25:05 +000038#include <linux/completion.h>
Steve Wisecfdda9d2010-04-21 15:30:06 -070039#include <linux/netdevice.h>
40#include <linux/sched.h>
41#include <linux/pci.h>
42#include <linux/dma-mapping.h>
43#include <linux/inet.h>
44#include <linux/wait.h>
45#include <linux/kref.h>
46#include <linux/timer.h>
47#include <linux/io.h>
48#include <linux/kfifo.h>
49
50#include <asm/byteorder.h>
51
52#include <net/net_namespace.h>
53
54#include <rdma/ib_verbs.h>
55#include <rdma/iw_cm.h>
56
57#include "cxgb4.h"
58#include "cxgb4_uld.h"
59#include "l2t.h"
60#include "user.h"
61
62#define DRV_NAME "iw_cxgb4"
63#define MOD DRV_NAME ":"
64
65extern int c4iw_debug;
66#define PDBG(fmt, args...) \
67do { \
68 if (c4iw_debug) \
69 printk(MOD fmt, ## args); \
70} while (0)
71
72#include "t4.h"
73
74#define PBL_OFF(rdev_p, a) ((a) - (rdev_p)->lldi.vr->pbl.start)
75#define RQT_OFF(rdev_p, a) ((a) - (rdev_p)->lldi.vr->rq.start)
76
77static inline void *cplhdr(struct sk_buff *skb)
78{
79 return skb->data;
80}
81
Steve Wisecfdda9d2010-04-21 15:30:06 -070082struct c4iw_resource {
83 struct kfifo tpt_fifo;
84 spinlock_t tpt_fifo_lock;
85 struct kfifo qid_fifo;
86 spinlock_t qid_fifo_lock;
87 struct kfifo pdid_fifo;
88 spinlock_t pdid_fifo_lock;
89};
90
91struct c4iw_qid_list {
92 struct list_head entry;
93 u32 qid;
94};
95
96struct c4iw_dev_ucontext {
97 struct list_head qpids;
98 struct list_head cqids;
99 struct mutex lock;
100};
101
102enum c4iw_rdev_flags {
103 T4_FATAL_ERROR = (1<<0),
104};
105
106struct c4iw_rdev {
107 struct c4iw_resource resource;
108 unsigned long qpshift;
109 u32 qpmask;
110 unsigned long cqshift;
111 u32 cqmask;
112 struct c4iw_dev_ucontext uctx;
113 struct gen_pool *pbl_pool;
114 struct gen_pool *rqt_pool;
Steve Wisec6d7b262010-09-13 11:23:57 -0500115 struct gen_pool *ocqp_pool;
Steve Wisecfdda9d2010-04-21 15:30:06 -0700116 u32 flags;
117 struct cxgb4_lld_info lldi;
Steve Wisec6d7b262010-09-13 11:23:57 -0500118 unsigned long oc_mw_pa;
119 void __iomem *oc_mw_kva;
Steve Wisecfdda9d2010-04-21 15:30:06 -0700120};
121
122static inline int c4iw_fatal_error(struct c4iw_rdev *rdev)
123{
124 return rdev->flags & T4_FATAL_ERROR;
125}
126
127static inline int c4iw_num_stags(struct c4iw_rdev *rdev)
128{
129 return min((int)T4_MAX_NUM_STAG, (int)(rdev->lldi.vr->stag.size >> 5));
130}
131
Steve Wiseaadc4df2010-09-10 11:15:25 -0500132#define C4IW_WR_TO (10*HZ)
133
134struct c4iw_wr_wait {
Steve Wisec3373742011-05-20 16:25:05 +0000135 struct completion completion;
Steve Wiseaadc4df2010-09-10 11:15:25 -0500136 int ret;
137};
138
139static inline void c4iw_init_wr_wait(struct c4iw_wr_wait *wr_waitp)
140{
141 wr_waitp->ret = 0;
Steve Wisec3373742011-05-20 16:25:05 +0000142 init_completion(&wr_waitp->completion);
Steve Wiseaadc4df2010-09-10 11:15:25 -0500143}
144
Steve Wised9594d92011-05-09 22:06:22 -0700145static inline void c4iw_wake_up(struct c4iw_wr_wait *wr_waitp, int ret)
146{
147 wr_waitp->ret = ret;
Steve Wisec3373742011-05-20 16:25:05 +0000148 complete(&wr_waitp->completion);
Steve Wised9594d92011-05-09 22:06:22 -0700149}
150
Steve Wiseaadc4df2010-09-10 11:15:25 -0500151static inline int c4iw_wait_for_reply(struct c4iw_rdev *rdev,
152 struct c4iw_wr_wait *wr_waitp,
153 u32 hwtid, u32 qpid,
154 const char *func)
155{
156 unsigned to = C4IW_WR_TO;
Steve Wised9594d92011-05-09 22:06:22 -0700157 int ret;
Steve Wiseaadc4df2010-09-10 11:15:25 -0500158
Steve Wised9594d92011-05-09 22:06:22 -0700159 do {
Steve Wisec3373742011-05-20 16:25:05 +0000160 ret = wait_for_completion_timeout(&wr_waitp->completion, to);
Steve Wised9594d92011-05-09 22:06:22 -0700161 if (!ret) {
Steve Wiseaadc4df2010-09-10 11:15:25 -0500162 printk(KERN_ERR MOD "%s - Device %s not responding - "
163 "tid %u qpid %u\n", func,
164 pci_name(rdev->lldi.pdev), hwtid, qpid);
Steve Wise2f25e9a2011-05-09 22:06:23 -0700165 if (c4iw_fatal_error(rdev)) {
166 wr_waitp->ret = -EIO;
167 break;
168 }
Steve Wiseaadc4df2010-09-10 11:15:25 -0500169 to = to << 2;
170 }
Steve Wised9594d92011-05-09 22:06:22 -0700171 } while (!ret);
Steve Wiseaadc4df2010-09-10 11:15:25 -0500172 if (wr_waitp->ret)
Steve Wise30c95c22011-05-09 22:06:22 -0700173 PDBG("%s: FW reply %d tid %u qpid %u\n",
174 pci_name(rdev->lldi.pdev), wr_waitp->ret, hwtid, qpid);
Steve Wiseaadc4df2010-09-10 11:15:25 -0500175 return wr_waitp->ret;
176}
177
Steve Wisecfdda9d2010-04-21 15:30:06 -0700178struct c4iw_dev {
179 struct ib_device ibdev;
180 struct c4iw_rdev rdev;
181 u32 device_cap_flags;
182 struct idr cqidr;
183 struct idr qpidr;
184 struct idr mmidr;
185 spinlock_t lock;
Steve Wisecfdda9d2010-04-21 15:30:06 -0700186 struct dentry *debugfs_root;
187};
188
189static inline struct c4iw_dev *to_c4iw_dev(struct ib_device *ibdev)
190{
191 return container_of(ibdev, struct c4iw_dev, ibdev);
192}
193
194static inline struct c4iw_dev *rdev_to_c4iw_dev(struct c4iw_rdev *rdev)
195{
196 return container_of(rdev, struct c4iw_dev, rdev);
197}
198
199static inline struct c4iw_cq *get_chp(struct c4iw_dev *rhp, u32 cqid)
200{
201 return idr_find(&rhp->cqidr, cqid);
202}
203
204static inline struct c4iw_qp *get_qhp(struct c4iw_dev *rhp, u32 qpid)
205{
206 return idr_find(&rhp->qpidr, qpid);
207}
208
209static inline struct c4iw_mr *get_mhp(struct c4iw_dev *rhp, u32 mmid)
210{
211 return idr_find(&rhp->mmidr, mmid);
212}
213
214static inline int insert_handle(struct c4iw_dev *rhp, struct idr *idr,
215 void *handle, u32 id)
216{
217 int ret;
218 int newid;
219
220 do {
221 if (!idr_pre_get(idr, GFP_KERNEL))
222 return -ENOMEM;
223 spin_lock_irq(&rhp->lock);
224 ret = idr_get_new_above(idr, handle, id, &newid);
225 BUG_ON(newid != id);
226 spin_unlock_irq(&rhp->lock);
227 } while (ret == -EAGAIN);
228
229 return ret;
230}
231
232static inline void remove_handle(struct c4iw_dev *rhp, struct idr *idr, u32 id)
233{
234 spin_lock_irq(&rhp->lock);
235 idr_remove(idr, id);
236 spin_unlock_irq(&rhp->lock);
237}
238
239struct c4iw_pd {
240 struct ib_pd ibpd;
241 u32 pdid;
242 struct c4iw_dev *rhp;
243};
244
245static inline struct c4iw_pd *to_c4iw_pd(struct ib_pd *ibpd)
246{
247 return container_of(ibpd, struct c4iw_pd, ibpd);
248}
249
250struct tpt_attributes {
251 u64 len;
252 u64 va_fbo;
253 enum fw_ri_mem_perms perms;
254 u32 stag;
255 u32 pdid;
256 u32 qpid;
257 u32 pbl_addr;
258 u32 pbl_size;
259 u32 state:1;
260 u32 type:2;
261 u32 rsvd:1;
262 u32 remote_invaliate_disable:1;
263 u32 zbva:1;
264 u32 mw_bind_enable:1;
265 u32 page_size:5;
266};
267
268struct c4iw_mr {
269 struct ib_mr ibmr;
270 struct ib_umem *umem;
271 struct c4iw_dev *rhp;
272 u64 kva;
273 struct tpt_attributes attr;
274};
275
276static inline struct c4iw_mr *to_c4iw_mr(struct ib_mr *ibmr)
277{
278 return container_of(ibmr, struct c4iw_mr, ibmr);
279}
280
281struct c4iw_mw {
282 struct ib_mw ibmw;
283 struct c4iw_dev *rhp;
284 u64 kva;
285 struct tpt_attributes attr;
286};
287
288static inline struct c4iw_mw *to_c4iw_mw(struct ib_mw *ibmw)
289{
290 return container_of(ibmw, struct c4iw_mw, ibmw);
291}
292
293struct c4iw_fr_page_list {
294 struct ib_fast_reg_page_list ibpl;
FUJITA Tomonorif38926a2010-06-03 05:37:50 +0000295 DEFINE_DMA_UNMAP_ADDR(mapping);
Steve Wisecfdda9d2010-04-21 15:30:06 -0700296 dma_addr_t dma_addr;
297 struct c4iw_dev *dev;
298 int size;
299};
300
301static inline struct c4iw_fr_page_list *to_c4iw_fr_page_list(
302 struct ib_fast_reg_page_list *ibpl)
303{
304 return container_of(ibpl, struct c4iw_fr_page_list, ibpl);
305}
306
307struct c4iw_cq {
308 struct ib_cq ibcq;
309 struct c4iw_dev *rhp;
310 struct t4_cq cq;
311 spinlock_t lock;
Kumar Sanghvi581bbe22011-10-24 21:20:21 +0530312 spinlock_t comp_handler_lock;
Steve Wisecfdda9d2010-04-21 15:30:06 -0700313 atomic_t refcnt;
314 wait_queue_head_t wait;
315};
316
317static inline struct c4iw_cq *to_c4iw_cq(struct ib_cq *ibcq)
318{
319 return container_of(ibcq, struct c4iw_cq, ibcq);
320}
321
322struct c4iw_mpa_attributes {
323 u8 initiator;
324 u8 recv_marker_enabled;
325 u8 xmit_marker_enabled;
326 u8 crc_enabled;
327 u8 version;
328 u8 p2p_type;
329};
330
331struct c4iw_qp_attributes {
332 u32 scq;
333 u32 rcq;
334 u32 sq_num_entries;
335 u32 rq_num_entries;
336 u32 sq_max_sges;
337 u32 sq_max_sges_rdma_write;
338 u32 rq_max_sges;
339 u32 state;
340 u8 enable_rdma_read;
341 u8 enable_rdma_write;
342 u8 enable_bind;
343 u8 enable_mmid0_fastreg;
344 u32 max_ord;
345 u32 max_ird;
346 u32 pd;
347 u32 next_state;
348 char terminate_buffer[52];
349 u32 terminate_msg_len;
350 u8 is_terminate_local;
351 struct c4iw_mpa_attributes mpa_attr;
352 struct c4iw_ep *llp_stream_handle;
353};
354
355struct c4iw_qp {
356 struct ib_qp ibqp;
357 struct c4iw_dev *rhp;
358 struct c4iw_ep *ep;
359 struct c4iw_qp_attributes attr;
360 struct t4_wq wq;
361 spinlock_t lock;
Steve Wise2f5b48c2010-09-10 11:15:36 -0500362 struct mutex mutex;
Steve Wisecfdda9d2010-04-21 15:30:06 -0700363 atomic_t refcnt;
364 wait_queue_head_t wait;
365 struct timer_list timer;
366};
367
368static inline struct c4iw_qp *to_c4iw_qp(struct ib_qp *ibqp)
369{
370 return container_of(ibqp, struct c4iw_qp, ibqp);
371}
372
373struct c4iw_ucontext {
374 struct ib_ucontext ibucontext;
375 struct c4iw_dev_ucontext uctx;
376 u32 key;
377 spinlock_t mmap_lock;
378 struct list_head mmaps;
379};
380
381static inline struct c4iw_ucontext *to_c4iw_ucontext(struct ib_ucontext *c)
382{
383 return container_of(c, struct c4iw_ucontext, ibucontext);
384}
385
386struct c4iw_mm_entry {
387 struct list_head entry;
388 u64 addr;
389 u32 key;
390 unsigned len;
391};
392
393static inline struct c4iw_mm_entry *remove_mmap(struct c4iw_ucontext *ucontext,
394 u32 key, unsigned len)
395{
396 struct list_head *pos, *nxt;
397 struct c4iw_mm_entry *mm;
398
399 spin_lock(&ucontext->mmap_lock);
400 list_for_each_safe(pos, nxt, &ucontext->mmaps) {
401
402 mm = list_entry(pos, struct c4iw_mm_entry, entry);
403 if (mm->key == key && mm->len == len) {
404 list_del_init(&mm->entry);
405 spin_unlock(&ucontext->mmap_lock);
406 PDBG("%s key 0x%x addr 0x%llx len %d\n", __func__,
407 key, (unsigned long long) mm->addr, mm->len);
408 return mm;
409 }
410 }
411 spin_unlock(&ucontext->mmap_lock);
412 return NULL;
413}
414
415static inline void insert_mmap(struct c4iw_ucontext *ucontext,
416 struct c4iw_mm_entry *mm)
417{
418 spin_lock(&ucontext->mmap_lock);
419 PDBG("%s key 0x%x addr 0x%llx len %d\n", __func__,
420 mm->key, (unsigned long long) mm->addr, mm->len);
421 list_add_tail(&mm->entry, &ucontext->mmaps);
422 spin_unlock(&ucontext->mmap_lock);
423}
424
425enum c4iw_qp_attr_mask {
426 C4IW_QP_ATTR_NEXT_STATE = 1 << 0,
427 C4IW_QP_ATTR_ENABLE_RDMA_READ = 1 << 7,
428 C4IW_QP_ATTR_ENABLE_RDMA_WRITE = 1 << 8,
429 C4IW_QP_ATTR_ENABLE_RDMA_BIND = 1 << 9,
430 C4IW_QP_ATTR_MAX_ORD = 1 << 11,
431 C4IW_QP_ATTR_MAX_IRD = 1 << 12,
432 C4IW_QP_ATTR_LLP_STREAM_HANDLE = 1 << 22,
433 C4IW_QP_ATTR_STREAM_MSG_BUFFER = 1 << 23,
434 C4IW_QP_ATTR_MPA_ATTR = 1 << 24,
435 C4IW_QP_ATTR_QP_CONTEXT_ACTIVATE = 1 << 25,
436 C4IW_QP_ATTR_VALID_MODIFY = (C4IW_QP_ATTR_ENABLE_RDMA_READ |
437 C4IW_QP_ATTR_ENABLE_RDMA_WRITE |
438 C4IW_QP_ATTR_MAX_ORD |
439 C4IW_QP_ATTR_MAX_IRD |
440 C4IW_QP_ATTR_LLP_STREAM_HANDLE |
441 C4IW_QP_ATTR_STREAM_MSG_BUFFER |
442 C4IW_QP_ATTR_MPA_ATTR |
443 C4IW_QP_ATTR_QP_CONTEXT_ACTIVATE)
444};
445
446int c4iw_modify_qp(struct c4iw_dev *rhp,
447 struct c4iw_qp *qhp,
448 enum c4iw_qp_attr_mask mask,
449 struct c4iw_qp_attributes *attrs,
450 int internal);
451
452enum c4iw_qp_state {
453 C4IW_QP_STATE_IDLE,
454 C4IW_QP_STATE_RTS,
455 C4IW_QP_STATE_ERROR,
456 C4IW_QP_STATE_TERMINATE,
457 C4IW_QP_STATE_CLOSING,
458 C4IW_QP_STATE_TOT
459};
460
461static inline int c4iw_convert_state(enum ib_qp_state ib_state)
462{
463 switch (ib_state) {
464 case IB_QPS_RESET:
465 case IB_QPS_INIT:
466 return C4IW_QP_STATE_IDLE;
467 case IB_QPS_RTS:
468 return C4IW_QP_STATE_RTS;
469 case IB_QPS_SQD:
470 return C4IW_QP_STATE_CLOSING;
471 case IB_QPS_SQE:
472 return C4IW_QP_STATE_TERMINATE;
473 case IB_QPS_ERR:
474 return C4IW_QP_STATE_ERROR;
475 default:
476 return -1;
477 }
478}
479
480static inline u32 c4iw_ib_to_tpt_access(int a)
481{
482 return (a & IB_ACCESS_REMOTE_WRITE ? FW_RI_MEM_ACCESS_REM_WRITE : 0) |
483 (a & IB_ACCESS_REMOTE_READ ? FW_RI_MEM_ACCESS_REM_READ : 0) |
484 (a & IB_ACCESS_LOCAL_WRITE ? FW_RI_MEM_ACCESS_LOCAL_WRITE : 0) |
485 FW_RI_MEM_ACCESS_LOCAL_READ;
486}
487
488static inline u32 c4iw_ib_to_tpt_bind_access(int acc)
489{
490 return (acc & IB_ACCESS_REMOTE_WRITE ? FW_RI_MEM_ACCESS_REM_WRITE : 0) |
491 (acc & IB_ACCESS_REMOTE_READ ? FW_RI_MEM_ACCESS_REM_READ : 0);
492}
493
494enum c4iw_mmid_state {
495 C4IW_STAG_STATE_VALID,
496 C4IW_STAG_STATE_INVALID
497};
498
499#define C4IW_NODE_DESC "cxgb4 Chelsio Communications"
500
501#define MPA_KEY_REQ "MPA ID Req Frame"
502#define MPA_KEY_REP "MPA ID Rep Frame"
503
504#define MPA_MAX_PRIVATE_DATA 256
505#define MPA_REJECT 0x20
506#define MPA_CRC 0x40
507#define MPA_MARKERS 0x80
508#define MPA_FLAGS_MASK 0xE0
509
510#define c4iw_put_ep(ep) { \
511 PDBG("put_ep (via %s:%u) ep %p refcnt %d\n", __func__, __LINE__, \
512 ep, atomic_read(&((ep)->kref.refcount))); \
513 WARN_ON(atomic_read(&((ep)->kref.refcount)) < 1); \
514 kref_put(&((ep)->kref), _c4iw_free_ep); \
515}
516
517#define c4iw_get_ep(ep) { \
518 PDBG("get_ep (via %s:%u) ep %p, refcnt %d\n", __func__, __LINE__, \
519 ep, atomic_read(&((ep)->kref.refcount))); \
520 kref_get(&((ep)->kref)); \
521}
522void _c4iw_free_ep(struct kref *kref);
523
524struct mpa_message {
525 u8 key[16];
526 u8 flags;
527 u8 revision;
528 __be16 private_data_size;
529 u8 private_data[0];
530};
531
532struct terminate_message {
533 u8 layer_etype;
534 u8 ecode;
535 __be16 hdrct_rsvd;
536 u8 len_hdrs[0];
537};
538
539#define TERM_MAX_LENGTH (sizeof(struct terminate_message) + 2 + 18 + 28)
540
541enum c4iw_layers_types {
542 LAYER_RDMAP = 0x00,
543 LAYER_DDP = 0x10,
544 LAYER_MPA = 0x20,
545 RDMAP_LOCAL_CATA = 0x00,
546 RDMAP_REMOTE_PROT = 0x01,
547 RDMAP_REMOTE_OP = 0x02,
548 DDP_LOCAL_CATA = 0x00,
549 DDP_TAGGED_ERR = 0x01,
550 DDP_UNTAGGED_ERR = 0x02,
551 DDP_LLP = 0x03
552};
553
554enum c4iw_rdma_ecodes {
555 RDMAP_INV_STAG = 0x00,
556 RDMAP_BASE_BOUNDS = 0x01,
557 RDMAP_ACC_VIOL = 0x02,
558 RDMAP_STAG_NOT_ASSOC = 0x03,
559 RDMAP_TO_WRAP = 0x04,
560 RDMAP_INV_VERS = 0x05,
561 RDMAP_INV_OPCODE = 0x06,
562 RDMAP_STREAM_CATA = 0x07,
563 RDMAP_GLOBAL_CATA = 0x08,
564 RDMAP_CANT_INV_STAG = 0x09,
565 RDMAP_UNSPECIFIED = 0xff
566};
567
568enum c4iw_ddp_ecodes {
569 DDPT_INV_STAG = 0x00,
570 DDPT_BASE_BOUNDS = 0x01,
571 DDPT_STAG_NOT_ASSOC = 0x02,
572 DDPT_TO_WRAP = 0x03,
573 DDPT_INV_VERS = 0x04,
574 DDPU_INV_QN = 0x01,
575 DDPU_INV_MSN_NOBUF = 0x02,
576 DDPU_INV_MSN_RANGE = 0x03,
577 DDPU_INV_MO = 0x04,
578 DDPU_MSG_TOOBIG = 0x05,
579 DDPU_INV_VERS = 0x06
580};
581
582enum c4iw_mpa_ecodes {
583 MPA_CRC_ERR = 0x02,
584 MPA_MARKER_ERR = 0x03
585};
586
587enum c4iw_ep_state {
588 IDLE = 0,
589 LISTEN,
590 CONNECTING,
591 MPA_REQ_WAIT,
592 MPA_REQ_SENT,
593 MPA_REQ_RCVD,
594 MPA_REP_SENT,
595 FPDU_MODE,
596 ABORTING,
597 CLOSING,
598 MORIBUND,
599 DEAD,
600};
601
602enum c4iw_ep_flags {
603 PEER_ABORT_IN_PROGRESS = 0,
604 ABORT_REQ_IN_PROGRESS = 1,
605 RELEASE_RESOURCES = 2,
606 CLOSE_SENT = 3,
607};
608
609struct c4iw_ep_common {
610 struct iw_cm_id *cm_id;
611 struct c4iw_qp *qp;
612 struct c4iw_dev *dev;
613 enum c4iw_ep_state state;
614 struct kref kref;
Steve Wise2f5b48c2010-09-10 11:15:36 -0500615 struct mutex mutex;
Steve Wisecfdda9d2010-04-21 15:30:06 -0700616 struct sockaddr_in local_addr;
617 struct sockaddr_in remote_addr;
Steve Wiseaadc4df2010-09-10 11:15:25 -0500618 struct c4iw_wr_wait wr_wait;
Steve Wisecfdda9d2010-04-21 15:30:06 -0700619 unsigned long flags;
620};
621
622struct c4iw_listen_ep {
623 struct c4iw_ep_common com;
624 unsigned int stid;
625 int backlog;
626};
627
628struct c4iw_ep {
629 struct c4iw_ep_common com;
630 struct c4iw_ep *parent_ep;
631 struct timer_list timer;
Roland Dreierbe4c9ba2010-05-05 14:45:40 -0700632 struct list_head entry;
Steve Wisecfdda9d2010-04-21 15:30:06 -0700633 unsigned int atid;
634 u32 hwtid;
635 u32 snd_seq;
636 u32 rcv_seq;
637 struct l2t_entry *l2t;
638 struct dst_entry *dst;
639 struct sk_buff *mpa_skb;
640 struct c4iw_mpa_attributes mpa_attr;
641 u8 mpa_pkt[sizeof(struct mpa_message) + MPA_MAX_PRIVATE_DATA];
642 unsigned int mpa_pkt_len;
643 u32 ird;
644 u32 ord;
645 u32 smac_idx;
646 u32 tx_chan;
647 u32 mtu;
648 u16 mss;
649 u16 emss;
650 u16 plen;
651 u16 rss_qid;
652 u16 txq_idx;
Steve Wised4f1a5c2010-07-23 19:12:32 +0000653 u16 ctrlq_idx;
Steve Wisecfdda9d2010-04-21 15:30:06 -0700654 u8 tos;
655};
656
657static inline struct c4iw_ep *to_ep(struct iw_cm_id *cm_id)
658{
659 return cm_id->provider_data;
660}
661
662static inline struct c4iw_listen_ep *to_listen_ep(struct iw_cm_id *cm_id)
663{
664 return cm_id->provider_data;
665}
666
667static inline int compute_wscale(int win)
668{
669 int wscale = 0;
670
671 while (wscale < 14 && (65535<<wscale) < win)
672 wscale++;
673 return wscale;
674}
675
676typedef int (*c4iw_handler_func)(struct c4iw_dev *dev, struct sk_buff *skb);
677
678int c4iw_ep_redirect(void *ctx, struct dst_entry *old, struct dst_entry *new,
679 struct l2t_entry *l2t);
680void c4iw_put_qpid(struct c4iw_rdev *rdev, u32 qpid,
681 struct c4iw_dev_ucontext *uctx);
682u32 c4iw_get_resource(struct kfifo *fifo, spinlock_t *lock);
683void c4iw_put_resource(struct kfifo *fifo, u32 entry, spinlock_t *lock);
684int c4iw_init_resource(struct c4iw_rdev *rdev, u32 nr_tpt, u32 nr_pdid);
685int c4iw_init_ctrl_qp(struct c4iw_rdev *rdev);
686int c4iw_pblpool_create(struct c4iw_rdev *rdev);
687int c4iw_rqtpool_create(struct c4iw_rdev *rdev);
Steve Wisec6d7b262010-09-13 11:23:57 -0500688int c4iw_ocqp_pool_create(struct c4iw_rdev *rdev);
Steve Wisecfdda9d2010-04-21 15:30:06 -0700689void c4iw_pblpool_destroy(struct c4iw_rdev *rdev);
690void c4iw_rqtpool_destroy(struct c4iw_rdev *rdev);
Steve Wisec6d7b262010-09-13 11:23:57 -0500691void c4iw_ocqp_pool_destroy(struct c4iw_rdev *rdev);
Steve Wisecfdda9d2010-04-21 15:30:06 -0700692void c4iw_destroy_resource(struct c4iw_resource *rscp);
693int c4iw_destroy_ctrl_qp(struct c4iw_rdev *rdev);
694int c4iw_register_device(struct c4iw_dev *dev);
695void c4iw_unregister_device(struct c4iw_dev *dev);
696int __init c4iw_cm_init(void);
697void __exit c4iw_cm_term(void);
698void c4iw_release_dev_ucontext(struct c4iw_rdev *rdev,
699 struct c4iw_dev_ucontext *uctx);
700void c4iw_init_dev_ucontext(struct c4iw_rdev *rdev,
701 struct c4iw_dev_ucontext *uctx);
702int c4iw_poll_cq(struct ib_cq *ibcq, int num_entries, struct ib_wc *wc);
703int c4iw_post_send(struct ib_qp *ibqp, struct ib_send_wr *wr,
704 struct ib_send_wr **bad_wr);
705int c4iw_post_receive(struct ib_qp *ibqp, struct ib_recv_wr *wr,
706 struct ib_recv_wr **bad_wr);
707int c4iw_bind_mw(struct ib_qp *qp, struct ib_mw *mw,
708 struct ib_mw_bind *mw_bind);
709int c4iw_connect(struct iw_cm_id *cm_id, struct iw_cm_conn_param *conn_param);
710int c4iw_create_listen(struct iw_cm_id *cm_id, int backlog);
711int c4iw_destroy_listen(struct iw_cm_id *cm_id);
712int c4iw_accept_cr(struct iw_cm_id *cm_id, struct iw_cm_conn_param *conn_param);
713int c4iw_reject_cr(struct iw_cm_id *cm_id, const void *pdata, u8 pdata_len);
714void c4iw_qp_add_ref(struct ib_qp *qp);
715void c4iw_qp_rem_ref(struct ib_qp *qp);
716void c4iw_free_fastreg_pbl(struct ib_fast_reg_page_list *page_list);
717struct ib_fast_reg_page_list *c4iw_alloc_fastreg_pbl(
718 struct ib_device *device,
719 int page_list_len);
720struct ib_mr *c4iw_alloc_fast_reg_mr(struct ib_pd *pd, int pbl_depth);
721int c4iw_dealloc_mw(struct ib_mw *mw);
722struct ib_mw *c4iw_alloc_mw(struct ib_pd *pd);
723struct ib_mr *c4iw_reg_user_mr(struct ib_pd *pd, u64 start,
724 u64 length, u64 virt, int acc,
725 struct ib_udata *udata);
726struct ib_mr *c4iw_get_dma_mr(struct ib_pd *pd, int acc);
727struct ib_mr *c4iw_register_phys_mem(struct ib_pd *pd,
728 struct ib_phys_buf *buffer_list,
729 int num_phys_buf,
730 int acc,
731 u64 *iova_start);
732int c4iw_reregister_phys_mem(struct ib_mr *mr,
733 int mr_rereg_mask,
734 struct ib_pd *pd,
735 struct ib_phys_buf *buffer_list,
736 int num_phys_buf,
737 int acc, u64 *iova_start);
738int c4iw_dereg_mr(struct ib_mr *ib_mr);
739int c4iw_destroy_cq(struct ib_cq *ib_cq);
740struct ib_cq *c4iw_create_cq(struct ib_device *ibdev, int entries,
741 int vector,
742 struct ib_ucontext *ib_context,
743 struct ib_udata *udata);
744int c4iw_resize_cq(struct ib_cq *cq, int cqe, struct ib_udata *udata);
745int c4iw_arm_cq(struct ib_cq *ibcq, enum ib_cq_notify_flags flags);
746int c4iw_destroy_qp(struct ib_qp *ib_qp);
747struct ib_qp *c4iw_create_qp(struct ib_pd *pd,
748 struct ib_qp_init_attr *attrs,
749 struct ib_udata *udata);
750int c4iw_ib_modify_qp(struct ib_qp *ibqp, struct ib_qp_attr *attr,
751 int attr_mask, struct ib_udata *udata);
752struct ib_qp *c4iw_get_qp(struct ib_device *dev, int qpn);
753u32 c4iw_rqtpool_alloc(struct c4iw_rdev *rdev, int size);
754void c4iw_rqtpool_free(struct c4iw_rdev *rdev, u32 addr, int size);
755u32 c4iw_pblpool_alloc(struct c4iw_rdev *rdev, int size);
756void c4iw_pblpool_free(struct c4iw_rdev *rdev, u32 addr, int size);
Steve Wisec6d7b262010-09-13 11:23:57 -0500757u32 c4iw_ocqp_pool_alloc(struct c4iw_rdev *rdev, int size);
758void c4iw_ocqp_pool_free(struct c4iw_rdev *rdev, u32 addr, int size);
Steve Wisecfdda9d2010-04-21 15:30:06 -0700759int c4iw_ofld_send(struct c4iw_rdev *rdev, struct sk_buff *skb);
760void c4iw_flush_hw_cq(struct t4_cq *cq);
761void c4iw_count_rcqes(struct t4_cq *cq, struct t4_wq *wq, int *count);
762void c4iw_count_scqes(struct t4_cq *cq, struct t4_wq *wq, int *count);
763int c4iw_ep_disconnect(struct c4iw_ep *ep, int abrupt, gfp_t gfp);
764int c4iw_flush_rq(struct t4_wq *wq, struct t4_cq *cq, int count);
765int c4iw_flush_sq(struct t4_wq *wq, struct t4_cq *cq, int count);
766int c4iw_ev_handler(struct c4iw_dev *rnicp, u32 qid);
767u16 c4iw_rqes_posted(struct c4iw_qp *qhp);
Steve Wisecfdda9d2010-04-21 15:30:06 -0700768int c4iw_post_terminate(struct c4iw_qp *qhp, struct t4_cqe *err_cqe);
769u32 c4iw_get_cqid(struct c4iw_rdev *rdev, struct c4iw_dev_ucontext *uctx);
770void c4iw_put_cqid(struct c4iw_rdev *rdev, u32 qid,
771 struct c4iw_dev_ucontext *uctx);
772u32 c4iw_get_qpid(struct c4iw_rdev *rdev, struct c4iw_dev_ucontext *uctx);
773void c4iw_put_qpid(struct c4iw_rdev *rdev, u32 qid,
774 struct c4iw_dev_ucontext *uctx);
775void c4iw_ev_dispatch(struct c4iw_dev *dev, struct t4_cqe *err_cqe);
776
777extern struct cxgb4_client t4c_client;
778extern c4iw_handler_func c4iw_handlers[NUM_CPL_CMDS];
Roland Dreierbe4c9ba2010-05-05 14:45:40 -0700779extern int c4iw_max_read_depth;
Steve Wisecfdda9d2010-04-21 15:30:06 -0700780
781#endif