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wanzongshun7ec80dd2008-12-03 03:55:38 +01001/*
2 * linux/arch/arm/mach-w90x900/time.c
3 *
4 * Based on linux/arch/arm/plat-s3c24xx/time.c by Ben Dooks
5 *
wanzongshun58b53692009-08-14 15:36:44 +01006 * Copyright (c) 2009 Nuvoton technology corporation
wanzongshun7ec80dd2008-12-03 03:55:38 +01007 * All rights reserved.
8 *
9 * Wan ZongShun <mcuos.com@gmail.com>
10 *
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2 of the License, or
14 * (at your option) any later version.
15 *
16 */
17
18#include <linux/kernel.h>
19#include <linux/sched.h>
20#include <linux/init.h>
21#include <linux/interrupt.h>
22#include <linux/err.h>
23#include <linux/clk.h>
24#include <linux/io.h>
25#include <linux/leds.h>
wanzongshun58b53692009-08-14 15:36:44 +010026#include <linux/clocksource.h>
27#include <linux/clockchips.h>
wanzongshun7ec80dd2008-12-03 03:55:38 +010028
29#include <asm/mach-types.h>
30#include <asm/mach/irq.h>
31#include <asm/mach/time.h>
32
wanzongshun7ec80dd2008-12-03 03:55:38 +010033#include <mach/map.h>
34#include <mach/regs-timer.h>
35
wanzongshun58b53692009-08-14 15:36:44 +010036#define RESETINT 0x1f
37#define PERIOD (0x01 << 27)
38#define ONESHOT (0x00 << 27)
39#define COUNTEN (0x01 << 30)
40#define INTEN (0x01 << 29)
41
42#define TICKS_PER_SEC 100
43#define PRESCALE 0x63 /* Divider = prescale + 1 */
44
45unsigned int timer0_load;
46
47static void w90p910_clockevent_setmode(enum clock_event_mode mode,
48 struct clock_event_device *clk)
wanzongshun7ec80dd2008-12-03 03:55:38 +010049{
wanzongshun58b53692009-08-14 15:36:44 +010050 unsigned int val;
51
52 val = __raw_readl(REG_TCSR0);
53 val &= ~(0x03 << 27);
54
55 switch (mode) {
56 case CLOCK_EVT_MODE_PERIODIC:
57 __raw_writel(timer0_load, REG_TICR0);
58 val |= (PERIOD | COUNTEN | INTEN | PRESCALE);
59 break;
60
61 case CLOCK_EVT_MODE_ONESHOT:
62 val |= (ONESHOT | COUNTEN | INTEN | PRESCALE);
63 break;
64
65 case CLOCK_EVT_MODE_UNUSED:
66 case CLOCK_EVT_MODE_SHUTDOWN:
67 case CLOCK_EVT_MODE_RESUME:
68 break;
69 }
70
71 __raw_writel(val, REG_TCSR0);
72}
73
74static int w90p910_clockevent_setnextevent(unsigned long evt,
75 struct clock_event_device *clk)
76{
77 unsigned int val;
78
79 __raw_writel(evt, REG_TICR0);
80
81 val = __raw_readl(REG_TCSR0);
82 val |= (COUNTEN | INTEN | PRESCALE);
83 __raw_writel(val, REG_TCSR0);
84
wanzongshun7ec80dd2008-12-03 03:55:38 +010085 return 0;
86}
87
wanzongshun58b53692009-08-14 15:36:44 +010088static struct clock_event_device w90p910_clockevent_device = {
89 .name = "w90p910-timer0",
90 .shift = 32,
91 .features = CLOCK_EVT_MODE_PERIODIC | CLOCK_EVT_FEAT_ONESHOT,
92 .set_mode = w90p910_clockevent_setmode,
93 .set_next_event = w90p910_clockevent_setnextevent,
94 .rating = 300,
95};
96
wanzongshun7ec80dd2008-12-03 03:55:38 +010097/*IRQ handler for the timer*/
98
wanzongshun58b53692009-08-14 15:36:44 +010099static irqreturn_t w90p910_timer0_interrupt(int irq, void *dev_id)
wanzongshun7ec80dd2008-12-03 03:55:38 +0100100{
wanzongshun58b53692009-08-14 15:36:44 +0100101 struct clock_event_device *evt = &w90p910_clockevent_device;
102
wanzongshun7ec80dd2008-12-03 03:55:38 +0100103 __raw_writel(0x01, REG_TISR); /* clear TIF0 */
wanzongshun58b53692009-08-14 15:36:44 +0100104
105 evt->event_handler(evt);
wanzongshun7ec80dd2008-12-03 03:55:38 +0100106 return IRQ_HANDLED;
107}
108
wanzongshun58b53692009-08-14 15:36:44 +0100109static struct irqaction w90p910_timer0_irq = {
110 .name = "w90p910-timer0",
wanzongshun7ec80dd2008-12-03 03:55:38 +0100111 .flags = IRQF_DISABLED | IRQF_TIMER | IRQF_IRQPOLL,
wanzongshun58b53692009-08-14 15:36:44 +0100112 .handler = w90p910_timer0_interrupt,
wanzongshun7ec80dd2008-12-03 03:55:38 +0100113};
114
wanzongshun58b53692009-08-14 15:36:44 +0100115static void __init w90p910_clockevents_init(unsigned int rate)
wanzongshun7ec80dd2008-12-03 03:55:38 +0100116{
wanzongshun58b53692009-08-14 15:36:44 +0100117 w90p910_clockevent_device.mult = div_sc(rate, NSEC_PER_SEC,
118 w90p910_clockevent_device.shift);
119 w90p910_clockevent_device.max_delta_ns = clockevent_delta2ns(0xffffffff,
120 &w90p910_clockevent_device);
121 w90p910_clockevent_device.min_delta_ns = clockevent_delta2ns(0xf,
122 &w90p910_clockevent_device);
123 w90p910_clockevent_device.cpumask = cpumask_of(0);
124
125 clockevents_register_device(&w90p910_clockevent_device);
wanzongshun7ec80dd2008-12-03 03:55:38 +0100126}
127
wanzongshun58b53692009-08-14 15:36:44 +0100128static cycle_t w90p910_get_cycles(struct clocksource *cs)
wanzongshun7ec80dd2008-12-03 03:55:38 +0100129{
wanzongshun58b53692009-08-14 15:36:44 +0100130 return ~__raw_readl(REG_TDR1);
131}
132
133static struct clocksource clocksource_w90p910 = {
134 .name = "w90p910-timer1",
135 .rating = 200,
136 .read = w90p910_get_cycles,
137 .mask = CLOCKSOURCE_MASK(32),
138 .shift = 20,
139 .flags = CLOCK_SOURCE_IS_CONTINUOUS,
140};
141
142static void __init w90p910_clocksource_init(unsigned int rate)
143{
144 unsigned int val;
145
146 __raw_writel(0xffffffff, REG_TICR1);
147
148 val = __raw_readl(REG_TCSR1);
149 val |= (COUNTEN | PERIOD);
150 __raw_writel(val, REG_TCSR1);
151
152 clocksource_w90p910.mult =
153 clocksource_khz2mult((rate / 1000), clocksource_w90p910.shift);
154 clocksource_register(&clocksource_w90p910);
155}
156
157static void __init w90p910_timer_init(void)
158{
159 struct clk *ck_ext = clk_get(NULL, "ext");
160 unsigned int rate;
161
162 BUG_ON(IS_ERR(ck_ext));
163
164 rate = clk_get_rate(ck_ext);
165 clk_put(ck_ext);
166 rate = rate / (PRESCALE + 0x01);
167
168 /* set a known state */
169 __raw_writel(0x00, REG_TCSR0);
170 __raw_writel(0x00, REG_TCSR1);
171 __raw_writel(RESETINT, REG_TISR);
172 timer0_load = (rate / TICKS_PER_SEC);
173
174 setup_irq(IRQ_TIMER0, &w90p910_timer0_irq);
175
176 w90p910_clocksource_init(rate);
177 w90p910_clockevents_init(rate);
wanzongshun7ec80dd2008-12-03 03:55:38 +0100178}
179
180struct sys_timer w90x900_timer = {
wanzongshun58b53692009-08-14 15:36:44 +0100181 .init = w90p910_timer_init,
wanzongshun7ec80dd2008-12-03 03:55:38 +0100182};