| Greg Ungerer | 5938084 | 2009-05-19 13:56:44 +1000 | [diff] [blame^] | 1 | /****************************************************************************/ |
| 2 | |
| 3 | /* |
| 4 | * mcfintc.h -- support definitions for the simple ColdFire |
| 5 | * Interrupt Controller |
| 6 | * |
| 7 | * (C) Copyright 2009, Greg Ungerer <gerg@uclinux.org> |
| 8 | */ |
| 9 | |
| 10 | /****************************************************************************/ |
| 11 | #ifndef mcfintc_h |
| 12 | #define mcfintc_h |
| 13 | /****************************************************************************/ |
| 14 | |
| 15 | /* |
| 16 | * Most of the older ColdFire parts use the same simple interrupt |
| 17 | * controller. This is currently used on the 5206, 5206e, 5249, 5307 |
| 18 | * and 5407 parts. |
| 19 | * |
| 20 | * The builtin peripherals are masked through dedicated bits in the |
| 21 | * Interrupt Mask register (IMR) - and this is not indexed (or in any way |
| 22 | * related to) the actual interrupt number they use. So knowing the IRQ |
| 23 | * number doesn't explicitly map to a certain internal device for |
| 24 | * interrupt control purposes. |
| 25 | */ |
| 26 | |
| 27 | /* |
| 28 | * Define the base address of the SIM within the MBAR address space. |
| 29 | */ |
| 30 | #define MCFSIM_BASE 0x0 /* Base address within SIM */ |
| 31 | |
| 32 | /* |
| 33 | * Bit definitions for the ICR family of registers. |
| 34 | */ |
| 35 | #define MCFSIM_ICR_AUTOVEC 0x80 /* Auto-vectored intr */ |
| 36 | #define MCFSIM_ICR_LEVEL0 0x00 /* Level 0 intr */ |
| 37 | #define MCFSIM_ICR_LEVEL1 0x04 /* Level 1 intr */ |
| 38 | #define MCFSIM_ICR_LEVEL2 0x08 /* Level 2 intr */ |
| 39 | #define MCFSIM_ICR_LEVEL3 0x0c /* Level 3 intr */ |
| 40 | #define MCFSIM_ICR_LEVEL4 0x10 /* Level 4 intr */ |
| 41 | #define MCFSIM_ICR_LEVEL5 0x14 /* Level 5 intr */ |
| 42 | #define MCFSIM_ICR_LEVEL6 0x18 /* Level 6 intr */ |
| 43 | #define MCFSIM_ICR_LEVEL7 0x1c /* Level 7 intr */ |
| 44 | |
| 45 | #define MCFSIM_ICR_PRI0 0x00 /* Priority 0 intr */ |
| 46 | #define MCFSIM_ICR_PRI1 0x01 /* Priority 1 intr */ |
| 47 | #define MCFSIM_ICR_PRI2 0x02 /* Priority 2 intr */ |
| 48 | #define MCFSIM_ICR_PRI3 0x03 /* Priority 3 intr */ |
| 49 | |
| 50 | /* |
| 51 | * Bit definitions for the ICR family of registers. |
| 52 | */ |
| 53 | #define MCFSIM_ICR_AUTOVEC 0x80 /* Auto-vectored intr */ |
| 54 | #define MCFSIM_ICR_LEVEL0 0x00 /* Level 0 intr */ |
| 55 | #define MCFSIM_ICR_LEVEL1 0x04 /* Level 1 intr */ |
| 56 | #define MCFSIM_ICR_LEVEL2 0x08 /* Level 2 intr */ |
| 57 | #define MCFSIM_ICR_LEVEL3 0x0c /* Level 3 intr */ |
| 58 | #define MCFSIM_ICR_LEVEL4 0x10 /* Level 4 intr */ |
| 59 | #define MCFSIM_ICR_LEVEL5 0x14 /* Level 5 intr */ |
| 60 | #define MCFSIM_ICR_LEVEL6 0x18 /* Level 6 intr */ |
| 61 | #define MCFSIM_ICR_LEVEL7 0x1c /* Level 7 intr */ |
| 62 | |
| 63 | #define MCFSIM_ICR_PRI0 0x00 /* Priority 0 intr */ |
| 64 | #define MCFSIM_ICR_PRI1 0x01 /* Priority 1 intr */ |
| 65 | #define MCFSIM_ICR_PRI2 0x02 /* Priority 2 intr */ |
| 66 | #define MCFSIM_ICR_PRI3 0x03 /* Priority 3 intr */ |
| 67 | |
| 68 | /* |
| 69 | * Bit definitions for the Interrupt Mask register (IMR). |
| 70 | */ |
| 71 | #define MCFSIM_IMR_EINT1 0x0002 /* External intr # 1 */ |
| 72 | #define MCFSIM_IMR_EINT2 0x0004 /* External intr # 2 */ |
| 73 | #define MCFSIM_IMR_EINT3 0x0008 /* External intr # 3 */ |
| 74 | #define MCFSIM_IMR_EINT4 0x0010 /* External intr # 4 */ |
| 75 | #define MCFSIM_IMR_EINT5 0x0020 /* External intr # 5 */ |
| 76 | #define MCFSIM_IMR_EINT6 0x0040 /* External intr # 6 */ |
| 77 | #define MCFSIM_IMR_EINT7 0x0080 /* External intr # 7 */ |
| 78 | |
| 79 | #define MCFSIM_IMR_SWD 0x0100 /* Software Watchdog intr */ |
| 80 | #define MCFSIM_IMR_TIMER1 0x0200 /* TIMER 1 intr */ |
| 81 | #define MCFSIM_IMR_TIMER2 0x0400 /* TIMER 2 intr */ |
| 82 | #define MCFSIM_IMR_MBUS 0x0800 /* MBUS intr */ |
| 83 | #define MCFSIM_IMR_UART1 0x1000 /* UART 1 intr */ |
| 84 | #define MCFSIM_IMR_UART2 0x2000 /* UART 2 intr */ |
| 85 | |
| 86 | #if defined(CONFIG_M5206e) |
| 87 | #define MCFSIM_IMR_DMA1 0x4000 /* DMA 1 intr */ |
| 88 | #define MCFSIM_IMR_DMA2 0x8000 /* DMA 2 intr */ |
| 89 | #elif defined(CONFIG_M5249) || defined(CONFIG_M5307) |
| 90 | #define MCFSIM_IMR_DMA0 0x4000 /* DMA 0 intr */ |
| 91 | #define MCFSIM_IMR_DMA1 0x8000 /* DMA 1 intr */ |
| 92 | #define MCFSIM_IMR_DMA2 0x10000 /* DMA 2 intr */ |
| 93 | #define MCFSIM_IMR_DMA3 0x20000 /* DMA 3 intr */ |
| 94 | #endif |
| 95 | |
| 96 | /* |
| 97 | * Mask for all of the SIM devices. Some parts have more or less |
| 98 | * SIM devices. This is a catchall for the sandard set. |
| 99 | */ |
| 100 | #ifndef MCFSIM_IMR_MASKALL |
| 101 | #define MCFSIM_IMR_MASKALL 0x3ffe /* All intr sources */ |
| 102 | #endif |
| 103 | |
| 104 | |
| 105 | /****************************************************************************/ |
| 106 | #endif /* mcfintc_h */ |