Ben Skeggs | 6ee7386 | 2009-12-11 19:24:15 +1000 | [diff] [blame] | 1 | /* |
| 2 | * Copyright (C) 2007 Ben Skeggs. |
| 3 | * All Rights Reserved. |
| 4 | * |
| 5 | * Permission is hereby granted, free of charge, to any person obtaining |
| 6 | * a copy of this software and associated documentation files (the |
| 7 | * "Software"), to deal in the Software without restriction, including |
| 8 | * without limitation the rights to use, copy, modify, merge, publish, |
| 9 | * distribute, sublicense, and/or sell copies of the Software, and to |
| 10 | * permit persons to whom the Software is furnished to do so, subject to |
| 11 | * the following conditions: |
| 12 | * |
| 13 | * The above copyright notice and this permission notice (including the |
| 14 | * next paragraph) shall be included in all copies or substantial |
| 15 | * portions of the Software. |
| 16 | * |
| 17 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, |
| 18 | * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF |
| 19 | * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. |
| 20 | * IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE |
| 21 | * LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION |
| 22 | * OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION |
| 23 | * WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. |
| 24 | * |
| 25 | */ |
| 26 | |
| 27 | #include "drmP.h" |
| 28 | #include "nouveau_drv.h" |
| 29 | #include "nouveau_drm.h" |
Ben Skeggs | e05c5a3 | 2010-09-01 15:24:35 +1000 | [diff] [blame] | 30 | #include "nouveau_ramht.h" |
Ben Skeggs | 6ee7386 | 2009-12-11 19:24:15 +1000 | [diff] [blame] | 31 | |
Ben Skeggs | e05c5a3 | 2010-09-01 15:24:35 +1000 | [diff] [blame] | 32 | #define NV40_RAMFC(c) (dev_priv->ramfc->pinst + ((c) * NV40_RAMFC__SIZE)) |
Ben Skeggs | 6ee7386 | 2009-12-11 19:24:15 +1000 | [diff] [blame] | 33 | #define NV40_RAMFC__SIZE 128 |
| 34 | |
| 35 | int |
| 36 | nv40_fifo_create_context(struct nouveau_channel *chan) |
| 37 | { |
| 38 | struct drm_device *dev = chan->dev; |
| 39 | struct drm_nouveau_private *dev_priv = dev->dev_private; |
| 40 | uint32_t fc = NV40_RAMFC(chan->id); |
Maarten Maathuis | ff9e527 | 2010-02-01 20:58:27 +0100 | [diff] [blame] | 41 | unsigned long flags; |
Ben Skeggs | 6ee7386 | 2009-12-11 19:24:15 +1000 | [diff] [blame] | 42 | int ret; |
| 43 | |
| 44 | ret = nouveau_gpuobj_new_fake(dev, NV40_RAMFC(chan->id), ~0, |
| 45 | NV40_RAMFC__SIZE, NVOBJ_FLAG_ZERO_ALLOC | |
Ben Skeggs | a8eaebc | 2010-09-01 15:24:31 +1000 | [diff] [blame] | 46 | NVOBJ_FLAG_ZERO_FREE, &chan->ramfc); |
Ben Skeggs | 6ee7386 | 2009-12-11 19:24:15 +1000 | [diff] [blame] | 47 | if (ret) |
| 48 | return ret; |
| 49 | |
Ben Skeggs | d908175 | 2010-11-22 16:05:54 +1000 | [diff] [blame] | 50 | chan->user = ioremap(pci_resource_start(dev->pdev, 0) + |
| 51 | NV40_USER(chan->id), PAGE_SIZE); |
| 52 | if (!chan->user) |
| 53 | return -ENOMEM; |
| 54 | |
Maarten Maathuis | ff9e527 | 2010-02-01 20:58:27 +0100 | [diff] [blame] | 55 | spin_lock_irqsave(&dev_priv->context_switch_lock, flags); |
| 56 | |
Ben Skeggs | 6ee7386 | 2009-12-11 19:24:15 +1000 | [diff] [blame] | 57 | nv_wi32(dev, fc + 0, chan->pushbuf_base); |
| 58 | nv_wi32(dev, fc + 4, chan->pushbuf_base); |
Ben Skeggs | a8eaebc | 2010-09-01 15:24:31 +1000 | [diff] [blame] | 59 | nv_wi32(dev, fc + 12, chan->pushbuf->pinst >> 4); |
Ben Skeggs | 6ee7386 | 2009-12-11 19:24:15 +1000 | [diff] [blame] | 60 | nv_wi32(dev, fc + 24, NV_PFIFO_CACHE1_DMA_FETCH_TRIG_128_BYTES | |
| 61 | NV_PFIFO_CACHE1_DMA_FETCH_SIZE_128_BYTES | |
| 62 | NV_PFIFO_CACHE1_DMA_FETCH_MAX_REQS_8 | |
| 63 | #ifdef __BIG_ENDIAN |
| 64 | NV_PFIFO_CACHE1_BIG_ENDIAN | |
| 65 | #endif |
| 66 | 0x30000000 /* no idea.. */); |
Ben Skeggs | 6ee7386 | 2009-12-11 19:24:15 +1000 | [diff] [blame] | 67 | nv_wi32(dev, fc + 60, 0x0001FFFF); |
Ben Skeggs | 6ee7386 | 2009-12-11 19:24:15 +1000 | [diff] [blame] | 68 | |
| 69 | /* enable the fifo dma operation */ |
| 70 | nv_wr32(dev, NV04_PFIFO_MODE, |
| 71 | nv_rd32(dev, NV04_PFIFO_MODE) | (1 << chan->id)); |
Maarten Maathuis | ff9e527 | 2010-02-01 20:58:27 +0100 | [diff] [blame] | 72 | |
| 73 | spin_unlock_irqrestore(&dev_priv->context_switch_lock, flags); |
Ben Skeggs | 6ee7386 | 2009-12-11 19:24:15 +1000 | [diff] [blame] | 74 | return 0; |
| 75 | } |
| 76 | |
Ben Skeggs | 6ee7386 | 2009-12-11 19:24:15 +1000 | [diff] [blame] | 77 | static void |
| 78 | nv40_fifo_do_load_context(struct drm_device *dev, int chid) |
| 79 | { |
| 80 | struct drm_nouveau_private *dev_priv = dev->dev_private; |
| 81 | uint32_t fc = NV40_RAMFC(chid), tmp, tmp2; |
| 82 | |
Ben Skeggs | 6ee7386 | 2009-12-11 19:24:15 +1000 | [diff] [blame] | 83 | nv_wr32(dev, NV04_PFIFO_CACHE1_DMA_PUT, nv_ri32(dev, fc + 0)); |
| 84 | nv_wr32(dev, NV04_PFIFO_CACHE1_DMA_GET, nv_ri32(dev, fc + 4)); |
| 85 | nv_wr32(dev, NV10_PFIFO_CACHE1_REF_CNT, nv_ri32(dev, fc + 8)); |
| 86 | nv_wr32(dev, NV04_PFIFO_CACHE1_DMA_INSTANCE, nv_ri32(dev, fc + 12)); |
| 87 | nv_wr32(dev, NV04_PFIFO_CACHE1_DMA_DCOUNT, nv_ri32(dev, fc + 16)); |
| 88 | nv_wr32(dev, NV04_PFIFO_CACHE1_DMA_STATE, nv_ri32(dev, fc + 20)); |
| 89 | |
| 90 | /* No idea what 0x2058 is.. */ |
| 91 | tmp = nv_ri32(dev, fc + 24); |
| 92 | tmp2 = nv_rd32(dev, 0x2058) & 0xFFF; |
| 93 | tmp2 |= (tmp & 0x30000000); |
| 94 | nv_wr32(dev, 0x2058, tmp2); |
| 95 | tmp &= ~0x30000000; |
| 96 | nv_wr32(dev, NV04_PFIFO_CACHE1_DMA_FETCH, tmp); |
| 97 | |
| 98 | nv_wr32(dev, NV04_PFIFO_CACHE1_ENGINE, nv_ri32(dev, fc + 28)); |
| 99 | nv_wr32(dev, NV04_PFIFO_CACHE1_PULL1, nv_ri32(dev, fc + 32)); |
| 100 | nv_wr32(dev, NV10_PFIFO_CACHE1_ACQUIRE_VALUE, nv_ri32(dev, fc + 36)); |
| 101 | tmp = nv_ri32(dev, fc + 40); |
| 102 | nv_wr32(dev, NV10_PFIFO_CACHE1_ACQUIRE_TIMESTAMP, tmp); |
| 103 | nv_wr32(dev, NV10_PFIFO_CACHE1_ACQUIRE_TIMEOUT, nv_ri32(dev, fc + 44)); |
| 104 | nv_wr32(dev, NV10_PFIFO_CACHE1_SEMAPHORE, nv_ri32(dev, fc + 48)); |
| 105 | nv_wr32(dev, NV10_PFIFO_CACHE1_DMA_SUBROUTINE, nv_ri32(dev, fc + 52)); |
| 106 | nv_wr32(dev, NV40_PFIFO_GRCTX_INSTANCE, nv_ri32(dev, fc + 56)); |
| 107 | |
| 108 | /* Don't clobber the TIMEOUT_ENABLED flag when restoring from RAMFC */ |
| 109 | tmp = nv_rd32(dev, NV04_PFIFO_DMA_TIMESLICE) & ~0x1FFFF; |
| 110 | tmp |= nv_ri32(dev, fc + 60) & 0x1FFFF; |
| 111 | nv_wr32(dev, NV04_PFIFO_DMA_TIMESLICE, tmp); |
| 112 | |
| 113 | nv_wr32(dev, 0x32e4, nv_ri32(dev, fc + 64)); |
| 114 | /* NVIDIA does this next line twice... */ |
| 115 | nv_wr32(dev, 0x32e8, nv_ri32(dev, fc + 68)); |
| 116 | nv_wr32(dev, 0x2088, nv_ri32(dev, fc + 76)); |
| 117 | nv_wr32(dev, 0x3300, nv_ri32(dev, fc + 80)); |
Ben Skeggs | a02ccc7 | 2011-04-04 16:08:24 +1000 | [diff] [blame] | 118 | nv_wr32(dev, 0x330c, nv_ri32(dev, fc + 84)); |
Ben Skeggs | 6ee7386 | 2009-12-11 19:24:15 +1000 | [diff] [blame] | 119 | |
Ben Skeggs | 6ee7386 | 2009-12-11 19:24:15 +1000 | [diff] [blame] | 120 | nv_wr32(dev, NV03_PFIFO_CACHE1_GET, 0); |
| 121 | nv_wr32(dev, NV03_PFIFO_CACHE1_PUT, 0); |
| 122 | } |
| 123 | |
| 124 | int |
| 125 | nv40_fifo_load_context(struct nouveau_channel *chan) |
| 126 | { |
| 127 | struct drm_device *dev = chan->dev; |
| 128 | uint32_t tmp; |
| 129 | |
| 130 | nv40_fifo_do_load_context(dev, chan->id); |
| 131 | |
| 132 | /* Set channel active, and in DMA mode */ |
| 133 | nv_wr32(dev, NV03_PFIFO_CACHE1_PUSH1, |
| 134 | NV40_PFIFO_CACHE1_PUSH1_DMA | chan->id); |
| 135 | nv_wr32(dev, NV04_PFIFO_CACHE1_DMA_PUSH, 1); |
| 136 | |
| 137 | /* Reset DMA_CTL_AT_INFO to INVALID */ |
| 138 | tmp = nv_rd32(dev, NV04_PFIFO_CACHE1_DMA_CTL) & ~(1 << 31); |
| 139 | nv_wr32(dev, NV04_PFIFO_CACHE1_DMA_CTL, tmp); |
| 140 | |
| 141 | return 0; |
| 142 | } |
| 143 | |
| 144 | int |
| 145 | nv40_fifo_unload_context(struct drm_device *dev) |
| 146 | { |
| 147 | struct drm_nouveau_private *dev_priv = dev->dev_private; |
| 148 | struct nouveau_fifo_engine *pfifo = &dev_priv->engine.fifo; |
| 149 | uint32_t fc, tmp; |
| 150 | int chid; |
| 151 | |
| 152 | chid = pfifo->channel_id(dev); |
| 153 | if (chid < 0 || chid >= dev_priv->engine.fifo.channels) |
| 154 | return 0; |
| 155 | fc = NV40_RAMFC(chid); |
| 156 | |
Ben Skeggs | 6ee7386 | 2009-12-11 19:24:15 +1000 | [diff] [blame] | 157 | nv_wi32(dev, fc + 0, nv_rd32(dev, NV04_PFIFO_CACHE1_DMA_PUT)); |
| 158 | nv_wi32(dev, fc + 4, nv_rd32(dev, NV04_PFIFO_CACHE1_DMA_GET)); |
| 159 | nv_wi32(dev, fc + 8, nv_rd32(dev, NV10_PFIFO_CACHE1_REF_CNT)); |
| 160 | nv_wi32(dev, fc + 12, nv_rd32(dev, NV04_PFIFO_CACHE1_DMA_INSTANCE)); |
| 161 | nv_wi32(dev, fc + 16, nv_rd32(dev, NV04_PFIFO_CACHE1_DMA_DCOUNT)); |
| 162 | nv_wi32(dev, fc + 20, nv_rd32(dev, NV04_PFIFO_CACHE1_DMA_STATE)); |
| 163 | tmp = nv_rd32(dev, NV04_PFIFO_CACHE1_DMA_FETCH); |
| 164 | tmp |= nv_rd32(dev, 0x2058) & 0x30000000; |
| 165 | nv_wi32(dev, fc + 24, tmp); |
| 166 | nv_wi32(dev, fc + 28, nv_rd32(dev, NV04_PFIFO_CACHE1_ENGINE)); |
| 167 | nv_wi32(dev, fc + 32, nv_rd32(dev, NV04_PFIFO_CACHE1_PULL1)); |
| 168 | nv_wi32(dev, fc + 36, nv_rd32(dev, NV10_PFIFO_CACHE1_ACQUIRE_VALUE)); |
| 169 | tmp = nv_rd32(dev, NV10_PFIFO_CACHE1_ACQUIRE_TIMESTAMP); |
| 170 | nv_wi32(dev, fc + 40, tmp); |
| 171 | nv_wi32(dev, fc + 44, nv_rd32(dev, NV10_PFIFO_CACHE1_ACQUIRE_TIMEOUT)); |
| 172 | nv_wi32(dev, fc + 48, nv_rd32(dev, NV10_PFIFO_CACHE1_SEMAPHORE)); |
| 173 | /* NVIDIA read 0x3228 first, then write DMA_GET here.. maybe something |
| 174 | * more involved depending on the value of 0x3228? |
| 175 | */ |
| 176 | nv_wi32(dev, fc + 52, nv_rd32(dev, NV04_PFIFO_CACHE1_DMA_GET)); |
| 177 | nv_wi32(dev, fc + 56, nv_rd32(dev, NV40_PFIFO_GRCTX_INSTANCE)); |
| 178 | nv_wi32(dev, fc + 60, nv_rd32(dev, NV04_PFIFO_DMA_TIMESLICE) & 0x1ffff); |
| 179 | /* No idea what the below is for exactly, ripped from a mmio-trace */ |
| 180 | nv_wi32(dev, fc + 64, nv_rd32(dev, NV40_PFIFO_UNK32E4)); |
| 181 | /* NVIDIA do this next line twice.. bug? */ |
| 182 | nv_wi32(dev, fc + 68, nv_rd32(dev, 0x32e8)); |
| 183 | nv_wi32(dev, fc + 76, nv_rd32(dev, 0x2088)); |
| 184 | nv_wi32(dev, fc + 80, nv_rd32(dev, 0x3300)); |
| 185 | #if 0 /* no real idea which is PUT/GET in UNK_48.. */ |
| 186 | tmp = nv_rd32(dev, NV04_PFIFO_CACHE1_GET); |
| 187 | tmp |= (nv_rd32(dev, NV04_PFIFO_CACHE1_PUT) << 16); |
| 188 | nv_wi32(dev, fc + 72, tmp); |
| 189 | #endif |
Ben Skeggs | a02ccc7 | 2011-04-04 16:08:24 +1000 | [diff] [blame] | 190 | nv_wi32(dev, fc + 84, nv_rd32(dev, 0x330c)); |
Ben Skeggs | 6ee7386 | 2009-12-11 19:24:15 +1000 | [diff] [blame] | 191 | |
| 192 | nv40_fifo_do_load_context(dev, pfifo->channels - 1); |
| 193 | nv_wr32(dev, NV03_PFIFO_CACHE1_PUSH1, |
| 194 | NV40_PFIFO_CACHE1_PUSH1_DMA | (pfifo->channels - 1)); |
| 195 | return 0; |
| 196 | } |
| 197 | |
| 198 | static void |
| 199 | nv40_fifo_init_reset(struct drm_device *dev) |
| 200 | { |
| 201 | int i; |
| 202 | |
| 203 | nv_wr32(dev, NV03_PMC_ENABLE, |
| 204 | nv_rd32(dev, NV03_PMC_ENABLE) & ~NV_PMC_ENABLE_PFIFO); |
| 205 | nv_wr32(dev, NV03_PMC_ENABLE, |
| 206 | nv_rd32(dev, NV03_PMC_ENABLE) | NV_PMC_ENABLE_PFIFO); |
| 207 | |
| 208 | nv_wr32(dev, 0x003224, 0x000f0078); |
| 209 | nv_wr32(dev, 0x003210, 0x00000000); |
| 210 | nv_wr32(dev, 0x003270, 0x00000000); |
| 211 | nv_wr32(dev, 0x003240, 0x00000000); |
| 212 | nv_wr32(dev, 0x003244, 0x00000000); |
| 213 | nv_wr32(dev, 0x003258, 0x00000000); |
| 214 | nv_wr32(dev, 0x002504, 0x00000000); |
| 215 | for (i = 0; i < 16; i++) |
| 216 | nv_wr32(dev, 0x002510 + (i * 4), 0x00000000); |
| 217 | nv_wr32(dev, 0x00250c, 0x0000ffff); |
| 218 | nv_wr32(dev, 0x002048, 0x00000000); |
| 219 | nv_wr32(dev, 0x003228, 0x00000000); |
| 220 | nv_wr32(dev, 0x0032e8, 0x00000000); |
| 221 | nv_wr32(dev, 0x002410, 0x00000000); |
| 222 | nv_wr32(dev, 0x002420, 0x00000000); |
| 223 | nv_wr32(dev, 0x002058, 0x00000001); |
| 224 | nv_wr32(dev, 0x00221c, 0x00000000); |
| 225 | /* something with 0x2084, read/modify/write, no change */ |
| 226 | nv_wr32(dev, 0x002040, 0x000000ff); |
| 227 | nv_wr32(dev, 0x002500, 0x00000000); |
| 228 | nv_wr32(dev, 0x003200, 0x00000000); |
| 229 | |
| 230 | nv_wr32(dev, NV04_PFIFO_DMA_TIMESLICE, 0x2101ffff); |
| 231 | } |
| 232 | |
| 233 | static void |
| 234 | nv40_fifo_init_ramxx(struct drm_device *dev) |
| 235 | { |
| 236 | struct drm_nouveau_private *dev_priv = dev->dev_private; |
| 237 | |
| 238 | nv_wr32(dev, NV03_PFIFO_RAMHT, (0x03 << 24) /* search 128 */ | |
Ben Skeggs | e05c5a3 | 2010-09-01 15:24:35 +1000 | [diff] [blame] | 239 | ((dev_priv->ramht->bits - 9) << 16) | |
| 240 | (dev_priv->ramht->gpuobj->pinst >> 8)); |
| 241 | nv_wr32(dev, NV03_PFIFO_RAMRO, dev_priv->ramro->pinst >> 8); |
Ben Skeggs | 6ee7386 | 2009-12-11 19:24:15 +1000 | [diff] [blame] | 242 | |
| 243 | switch (dev_priv->chipset) { |
| 244 | case 0x47: |
| 245 | case 0x49: |
| 246 | case 0x4b: |
| 247 | nv_wr32(dev, 0x2230, 1); |
| 248 | break; |
| 249 | default: |
| 250 | break; |
| 251 | } |
| 252 | |
| 253 | switch (dev_priv->chipset) { |
| 254 | case 0x40: |
| 255 | case 0x41: |
| 256 | case 0x42: |
| 257 | case 0x43: |
| 258 | case 0x45: |
| 259 | case 0x47: |
| 260 | case 0x48: |
| 261 | case 0x49: |
| 262 | case 0x4b: |
| 263 | nv_wr32(dev, NV40_PFIFO_RAMFC, 0x30002); |
| 264 | break; |
| 265 | default: |
| 266 | nv_wr32(dev, 0x2230, 0); |
| 267 | nv_wr32(dev, NV40_PFIFO_RAMFC, |
Ben Skeggs | a76fb4e | 2010-03-18 09:45:20 +1000 | [diff] [blame] | 268 | ((dev_priv->vram_size - 512 * 1024 + |
Ben Skeggs | e05c5a3 | 2010-09-01 15:24:35 +1000 | [diff] [blame] | 269 | dev_priv->ramfc->pinst) >> 16) | (3 << 16)); |
Ben Skeggs | 6ee7386 | 2009-12-11 19:24:15 +1000 | [diff] [blame] | 270 | break; |
| 271 | } |
| 272 | } |
| 273 | |
| 274 | static void |
| 275 | nv40_fifo_init_intr(struct drm_device *dev) |
| 276 | { |
Ben Skeggs | 5178d40 | 2010-11-03 10:56:05 +1000 | [diff] [blame] | 277 | nouveau_irq_register(dev, 8, nv04_fifo_isr); |
Ben Skeggs | 6ee7386 | 2009-12-11 19:24:15 +1000 | [diff] [blame] | 278 | nv_wr32(dev, 0x002100, 0xffffffff); |
| 279 | nv_wr32(dev, 0x002140, 0xffffffff); |
| 280 | } |
| 281 | |
| 282 | int |
| 283 | nv40_fifo_init(struct drm_device *dev) |
| 284 | { |
| 285 | struct drm_nouveau_private *dev_priv = dev->dev_private; |
| 286 | struct nouveau_fifo_engine *pfifo = &dev_priv->engine.fifo; |
| 287 | int i; |
| 288 | |
| 289 | nv40_fifo_init_reset(dev); |
| 290 | nv40_fifo_init_ramxx(dev); |
| 291 | |
| 292 | nv40_fifo_do_load_context(dev, pfifo->channels - 1); |
| 293 | nv_wr32(dev, NV03_PFIFO_CACHE1_PUSH1, pfifo->channels - 1); |
| 294 | |
| 295 | nv40_fifo_init_intr(dev); |
| 296 | pfifo->enable(dev); |
| 297 | pfifo->reassign(dev, true); |
| 298 | |
| 299 | for (i = 0; i < dev_priv->engine.fifo.channels; i++) { |
Ben Skeggs | cff5c13 | 2010-10-06 16:16:59 +1000 | [diff] [blame] | 300 | if (dev_priv->channels.ptr[i]) { |
Ben Skeggs | 6ee7386 | 2009-12-11 19:24:15 +1000 | [diff] [blame] | 301 | uint32_t mode = nv_rd32(dev, NV04_PFIFO_MODE); |
| 302 | nv_wr32(dev, NV04_PFIFO_MODE, mode | (1 << i)); |
| 303 | } |
| 304 | } |
| 305 | |
| 306 | return 0; |
| 307 | } |