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Stephen M. Cameronedd16362009-12-08 14:09:11 -08001/*
2 * Disk Array driver for HP Smart Array SAS controllers
3 * Copyright 2000, 2009 Hewlett-Packard Development Company, L.P.
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation; version 2 of the License.
8 *
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
12 * NON INFRINGEMENT. See the GNU General Public License for more details.
13 *
14 * You should have received a copy of the GNU General Public License
15 * along with this program; if not, write to the Free Software
16 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
17 *
18 * Questions/Comments/Bugfixes to iss_storagedev@hp.com
19 *
20 */
21#ifndef HPSA_CMD_H
22#define HPSA_CMD_H
23
24/* general boundary defintions */
25#define SENSEINFOBYTES 32 /* may vary between hbas */
Stephen M. Cameron33a2ffc2010-02-25 14:03:27 -060026#define MAXSGENTRIES 32
27#define HPSA_SG_CHAIN 0x80000000
Stephen M. Cameronedd16362009-12-08 14:09:11 -080028#define MAXREPLYQS 256
29
30/* Command Status value */
31#define CMD_SUCCESS 0x0000
32#define CMD_TARGET_STATUS 0x0001
33#define CMD_DATA_UNDERRUN 0x0002
34#define CMD_DATA_OVERRUN 0x0003
35#define CMD_INVALID 0x0004
36#define CMD_PROTOCOL_ERR 0x0005
37#define CMD_HARDWARE_ERR 0x0006
38#define CMD_CONNECTION_LOST 0x0007
39#define CMD_ABORTED 0x0008
40#define CMD_ABORT_FAILED 0x0009
41#define CMD_UNSOLICITED_ABORT 0x000A
42#define CMD_TIMEOUT 0x000B
43#define CMD_UNABORTABLE 0x000C
44
45/* Unit Attentions ASC's as defined for the MSA2012sa */
46#define POWER_OR_RESET 0x29
47#define STATE_CHANGED 0x2a
48#define UNIT_ATTENTION_CLEARED 0x2f
49#define LUN_FAILED 0x3e
50#define REPORT_LUNS_CHANGED 0x3f
51
52/* Unit Attentions ASCQ's as defined for the MSA2012sa */
53
54 /* These ASCQ's defined for ASC = POWER_OR_RESET */
55#define POWER_ON_RESET 0x00
56#define POWER_ON_REBOOT 0x01
57#define SCSI_BUS_RESET 0x02
58#define MSA_TARGET_RESET 0x03
59#define CONTROLLER_FAILOVER 0x04
60#define TRANSCEIVER_SE 0x05
61#define TRANSCEIVER_LVD 0x06
62
63 /* These ASCQ's defined for ASC = STATE_CHANGED */
64#define RESERVATION_PREEMPTED 0x03
65#define ASYM_ACCESS_CHANGED 0x06
66#define LUN_CAPACITY_CHANGED 0x09
67
68/* transfer direction */
69#define XFER_NONE 0x00
70#define XFER_WRITE 0x01
71#define XFER_READ 0x02
72#define XFER_RSVD 0x03
73
74/* task attribute */
75#define ATTR_UNTAGGED 0x00
76#define ATTR_SIMPLE 0x04
77#define ATTR_HEADOFQUEUE 0x05
78#define ATTR_ORDERED 0x06
79#define ATTR_ACA 0x07
80
81/* cdb type */
82#define TYPE_CMD 0x00
83#define TYPE_MSG 0x01
84
85/* config space register offsets */
86#define CFG_VENDORID 0x00
87#define CFG_DEVICEID 0x02
88#define CFG_I2OBAR 0x10
89#define CFG_MEM1BAR 0x14
90
91/* i2o space register offsets */
92#define I2O_IBDB_SET 0x20
93#define I2O_IBDB_CLEAR 0x70
94#define I2O_INT_STATUS 0x30
95#define I2O_INT_MASK 0x34
96#define I2O_IBPOST_Q 0x40
97#define I2O_OBPOST_Q 0x44
98#define I2O_DMA1_CFG 0x214
99
100/* Configuration Table */
101#define CFGTBL_ChangeReq 0x00000001l
102#define CFGTBL_AccCmds 0x00000001l
Stephen M. Cameron1df85522010-06-16 13:51:40 -0500103#define DOORBELL_CTLR_RESET 0x00000004l
Stephen M. Cameronedd16362009-12-08 14:09:11 -0800104
105#define CFGTBL_Trans_Simple 0x00000002l
Don Brace303932f2010-02-04 08:42:40 -0600106#define CFGTBL_Trans_Performant 0x00000004l
Stephen M. Cameron960a30e2011-02-15 15:33:03 -0600107#define CFGTBL_Trans_use_short_tags 0x20000000l
Stephen M. Cameronedd16362009-12-08 14:09:11 -0800108
109#define CFGTBL_BusType_Ultra2 0x00000001l
110#define CFGTBL_BusType_Ultra3 0x00000002l
111#define CFGTBL_BusType_Fibre1G 0x00000100l
112#define CFGTBL_BusType_Fibre2G 0x00000200l
113struct vals32 {
Stephen M. Cameron01a02ff2010-02-04 08:41:33 -0600114 u32 lower;
115 u32 upper;
Stephen M. Cameronedd16362009-12-08 14:09:11 -0800116};
117
118union u64bit {
119 struct vals32 val32;
Stephen M. Cameron01a02ff2010-02-04 08:41:33 -0600120 u64 val;
Stephen M. Cameronedd16362009-12-08 14:09:11 -0800121};
122
123/* FIXME this is a per controller value (barf!) */
124#define HPSA_MAX_TARGETS_PER_CTLR 16
125#define HPSA_MAX_LUN 256
126#define HPSA_MAX_PHYS_LUN 1024
127
128/* SCSI-3 Commands */
129#pragma pack(1)
130
131#define HPSA_INQUIRY 0x12
132struct InquiryData {
Stephen M. Cameron01a02ff2010-02-04 08:41:33 -0600133 u8 data_byte[36];
Stephen M. Cameronedd16362009-12-08 14:09:11 -0800134};
135
136#define HPSA_REPORT_LOG 0xc2 /* Report Logical LUNs */
137#define HPSA_REPORT_PHYS 0xc3 /* Report Physical LUNs */
138struct ReportLUNdata {
Stephen M. Cameron01a02ff2010-02-04 08:41:33 -0600139 u8 LUNListLength[4];
140 u32 reserved;
141 u8 LUN[HPSA_MAX_LUN][8];
Stephen M. Cameronedd16362009-12-08 14:09:11 -0800142};
143
144struct ReportExtendedLUNdata {
Stephen M. Cameron01a02ff2010-02-04 08:41:33 -0600145 u8 LUNListLength[4];
146 u8 extended_response_flag;
147 u8 reserved[3];
148 u8 LUN[HPSA_MAX_LUN][24];
Stephen M. Cameronedd16362009-12-08 14:09:11 -0800149};
150
151struct SenseSubsystem_info {
Stephen M. Cameron01a02ff2010-02-04 08:41:33 -0600152 u8 reserved[36];
153 u8 portname[8];
154 u8 reserved1[1108];
Stephen M. Cameronedd16362009-12-08 14:09:11 -0800155};
156
Stephen M. Cameronedd16362009-12-08 14:09:11 -0800157/* BMIC commands */
158#define BMIC_READ 0x26
159#define BMIC_WRITE 0x27
160#define BMIC_CACHE_FLUSH 0xc2
161#define HPSA_CACHE_FLUSH 0x01 /* C2 was already being used by HPSA */
162
163/* Command List Structure */
164union SCSI3Addr {
165 struct {
Stephen M. Cameron01a02ff2010-02-04 08:41:33 -0600166 u8 Dev;
167 u8 Bus:6;
168 u8 Mode:2; /* b00 */
Stephen M. Cameronedd16362009-12-08 14:09:11 -0800169 } PeripDev;
170 struct {
Stephen M. Cameron01a02ff2010-02-04 08:41:33 -0600171 u8 DevLSB;
172 u8 DevMSB:6;
173 u8 Mode:2; /* b01 */
Stephen M. Cameronedd16362009-12-08 14:09:11 -0800174 } LogDev;
175 struct {
Stephen M. Cameron01a02ff2010-02-04 08:41:33 -0600176 u8 Dev:5;
177 u8 Bus:3;
178 u8 Targ:6;
179 u8 Mode:2; /* b10 */
Stephen M. Cameronedd16362009-12-08 14:09:11 -0800180 } LogUnit;
181};
182
183struct PhysDevAddr {
Stephen M. Cameron01a02ff2010-02-04 08:41:33 -0600184 u32 TargetId:24;
185 u32 Bus:6;
186 u32 Mode:2;
Stephen M. Cameronedd16362009-12-08 14:09:11 -0800187 /* 2 level target device addr */
188 union SCSI3Addr Target[2];
189};
190
191struct LogDevAddr {
Stephen M. Cameron01a02ff2010-02-04 08:41:33 -0600192 u32 VolId:30;
193 u32 Mode:2;
194 u8 reserved[4];
Stephen M. Cameronedd16362009-12-08 14:09:11 -0800195};
196
197union LUNAddr {
Stephen M. Cameron01a02ff2010-02-04 08:41:33 -0600198 u8 LunAddrBytes[8];
Stephen M. Cameronedd16362009-12-08 14:09:11 -0800199 union SCSI3Addr SCSI3Lun[4];
200 struct PhysDevAddr PhysDev;
201 struct LogDevAddr LogDev;
202};
203
204struct CommandListHeader {
Stephen M. Cameron01a02ff2010-02-04 08:41:33 -0600205 u8 ReplyQueue;
206 u8 SGList;
207 u16 SGTotal;
Stephen M. Cameronedd16362009-12-08 14:09:11 -0800208 struct vals32 Tag;
209 union LUNAddr LUN;
210};
211
212struct RequestBlock {
Stephen M. Cameron01a02ff2010-02-04 08:41:33 -0600213 u8 CDBLen;
Stephen M. Cameronedd16362009-12-08 14:09:11 -0800214 struct {
Stephen M. Cameron01a02ff2010-02-04 08:41:33 -0600215 u8 Type:3;
216 u8 Attribute:3;
217 u8 Direction:2;
Stephen M. Cameronedd16362009-12-08 14:09:11 -0800218 } Type;
Stephen M. Cameron01a02ff2010-02-04 08:41:33 -0600219 u16 Timeout;
220 u8 CDB[16];
Stephen M. Cameronedd16362009-12-08 14:09:11 -0800221};
222
223struct ErrDescriptor {
224 struct vals32 Addr;
Stephen M. Cameron01a02ff2010-02-04 08:41:33 -0600225 u32 Len;
Stephen M. Cameronedd16362009-12-08 14:09:11 -0800226};
227
228struct SGDescriptor {
229 struct vals32 Addr;
Stephen M. Cameron01a02ff2010-02-04 08:41:33 -0600230 u32 Len;
231 u32 Ext;
Stephen M. Cameronedd16362009-12-08 14:09:11 -0800232};
233
234union MoreErrInfo {
235 struct {
Stephen M. Cameron01a02ff2010-02-04 08:41:33 -0600236 u8 Reserved[3];
237 u8 Type;
238 u32 ErrorInfo;
Stephen M. Cameronedd16362009-12-08 14:09:11 -0800239 } Common_Info;
240 struct {
Stephen M. Cameron01a02ff2010-02-04 08:41:33 -0600241 u8 Reserved[2];
242 u8 offense_size; /* size of offending entry */
243 u8 offense_num; /* byte # of offense 0-base */
244 u32 offense_value;
Stephen M. Cameronedd16362009-12-08 14:09:11 -0800245 } Invalid_Cmd;
246};
247struct ErrorInfo {
Stephen M. Cameron01a02ff2010-02-04 08:41:33 -0600248 u8 ScsiStatus;
249 u8 SenseLen;
250 u16 CommandStatus;
251 u32 ResidualCnt;
Stephen M. Cameronedd16362009-12-08 14:09:11 -0800252 union MoreErrInfo MoreErrInfo;
Stephen M. Cameron01a02ff2010-02-04 08:41:33 -0600253 u8 SenseInfo[SENSEINFOBYTES];
Stephen M. Cameronedd16362009-12-08 14:09:11 -0800254};
255/* Command types */
256#define CMD_IOCTL_PEND 0x01
257#define CMD_SCSI 0x03
258
Don Brace303932f2010-02-04 08:42:40 -0600259/* This structure needs to be divisible by 32 for new
260 * indexing method and performant mode.
Stephen M. Cameronedd16362009-12-08 14:09:11 -0800261 */
Don Brace303932f2010-02-04 08:42:40 -0600262#define PAD32 32
263#define PAD64DIFF 0
264#define USEEXTRA ((sizeof(void *) - 4)/4)
265#define PADSIZE (PAD32 + PAD64DIFF * USEEXTRA)
266
267#define DIRECT_LOOKUP_SHIFT 5
268#define DIRECT_LOOKUP_BIT 0x10
Stephen M. Camerond896f3f2011-01-06 14:47:53 -0600269#define DIRECT_LOOKUP_MASK (~((1 << DIRECT_LOOKUP_SHIFT) - 1))
Don Brace303932f2010-02-04 08:42:40 -0600270
271#define HPSA_ERROR_BIT 0x02
272struct ctlr_info; /* defined in hpsa.h */
273/* The size of this structure needs to be divisible by 32
274 * on all architectures because low 5 bits of the addresses
275 * are used as follows:
276 *
277 * bit 0: to device, used to indicate "performant mode" command
278 * from device, indidcates error status.
279 * bit 1-3: to device, indicates block fetch table entry for
280 * reducing DMA in fetching commands from host memory.
281 * bit 4: used to indicate whether tag is "direct lookup" (index),
282 * or a bus address.
283 */
284
Stephen M. Cameronedd16362009-12-08 14:09:11 -0800285struct CommandList {
286 struct CommandListHeader Header;
287 struct RequestBlock Request;
288 struct ErrDescriptor ErrDesc;
289 struct SGDescriptor SG[MAXSGENTRIES];
290 /* information associated with the command */
Stephen M. Cameron01a02ff2010-02-04 08:41:33 -0600291 u32 busaddr; /* physical addr of this record */
Stephen M. Cameronedd16362009-12-08 14:09:11 -0800292 struct ErrorInfo *err_info; /* pointer to the allocated mem */
293 struct ctlr_info *h;
294 int cmd_type;
295 long cmdindex;
Stephen M. Cameron9e0fc762011-02-15 15:32:48 -0600296 struct list_head list;
Stephen M. Cameronedd16362009-12-08 14:09:11 -0800297 struct request *rq;
298 struct completion *waiting;
Stephen M. Cameronedd16362009-12-08 14:09:11 -0800299 void *scsi_cmd;
Don Brace303932f2010-02-04 08:42:40 -0600300
301/* on 64 bit architectures, to get this to be 32-byte-aligned
Stephen M. Camerondb61bfc2010-02-25 14:03:22 -0600302 * it so happens we need PAD_64 bytes of padding, on 32 bit systems,
303 * we need PAD_32 bytes of padding (see below). This does that.
304 * If it happens that 64 bit and 32 bit systems need different
305 * padding, PAD_32 and PAD_64 can be set independently, and.
306 * the code below will do the right thing.
Don Brace303932f2010-02-04 08:42:40 -0600307 */
Stephen M. Camerondb61bfc2010-02-25 14:03:22 -0600308#define IS_32_BIT ((8 - sizeof(long))/4)
309#define IS_64_BIT (!IS_32_BIT)
Stephen M. Cameron43aebfa2010-02-25 14:03:32 -0600310#define PAD_32 (4)
311#define PAD_64 (4)
Stephen M. Camerondb61bfc2010-02-25 14:03:22 -0600312#define COMMANDLIST_PAD (IS_32_BIT * PAD_32 + IS_64_BIT * PAD_64)
Don Brace303932f2010-02-04 08:42:40 -0600313 u8 pad[COMMANDLIST_PAD];
Stephen M. Cameronedd16362009-12-08 14:09:11 -0800314};
315
316/* Configuration Table Structure */
317struct HostWrite {
Stephen M. Cameron01a02ff2010-02-04 08:41:33 -0600318 u32 TransportRequest;
319 u32 Reserved;
320 u32 CoalIntDelay;
321 u32 CoalIntCount;
Stephen M. Cameronedd16362009-12-08 14:09:11 -0800322};
323
Don Brace303932f2010-02-04 08:42:40 -0600324#define SIMPLE_MODE 0x02
325#define PERFORMANT_MODE 0x04
326#define MEMQ_MODE 0x08
327
Stephen M. Cameronedd16362009-12-08 14:09:11 -0800328struct CfgTable {
Don Brace303932f2010-02-04 08:42:40 -0600329 u8 Signature[4];
330 u32 SpecValence;
331 u32 TransportSupport;
332 u32 TransportActive;
333 struct HostWrite HostWrite;
334 u32 CmdsOutMax;
335 u32 BusTypes;
336 u32 TransMethodOffset;
337 u8 ServerName[16];
338 u32 HeartBeat;
339 u32 SCSI_Prefetch;
340 u32 MaxScatterGatherElements;
341 u32 MaxLogicalUnits;
342 u32 MaxPhysicalDevices;
343 u32 MaxPhysicalDrivesPerLogicalUnit;
344 u32 MaxPerformantModeCommands;
Stephen M. Cameron1df85522010-06-16 13:51:40 -0500345 u8 reserved[0x78 - 0x58];
346 u32 misc_fw_support; /* offset 0x78 */
347#define MISC_FW_DOORBELL_RESET (0x02)
Don Brace303932f2010-02-04 08:42:40 -0600348};
349
350#define NUM_BLOCKFETCH_ENTRIES 8
351struct TransTable_struct {
352 u32 BlockFetch[NUM_BLOCKFETCH_ENTRIES];
353 u32 RepQSize;
354 u32 RepQCount;
355 u32 RepQCtrAddrLow32;
356 u32 RepQCtrAddrHigh32;
357 u32 RepQAddr0Low32;
358 u32 RepQAddr0High32;
Stephen M. Cameronedd16362009-12-08 14:09:11 -0800359};
360
361struct hpsa_pci_info {
362 unsigned char bus;
363 unsigned char dev_fn;
364 unsigned short domain;
Stephen M. Cameron01a02ff2010-02-04 08:41:33 -0600365 u32 board_id;
Stephen M. Cameronedd16362009-12-08 14:09:11 -0800366};
367
368#pragma pack()
369#endif /* HPSA_CMD_H */