blob: d840865c70e0c7eb4dd7bc7817048879a57d5ca3 [file] [log] [blame]
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07001/* Copyright (c) 2009-2011, Code Aurora Forum. All rights reserved.
2 *
3 * This program is free software; you can redistribute it and/or modify
4 * it under the terms of the GNU General Public License version 2 and
5 * only version 2 as published by the Free Software Foundation.
6 *
7 * This program is distributed in the hope that it will be useful,
8 * but WITHOUT ANY WARRANTY; without even the implied warranty of
9 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
10 * GNU General Public License for more details.
11 */
12
13#include <linux/kernel.h>
14#include <linux/init.h>
15#include <linux/io.h>
16#include <linux/delay.h>
17#include <linux/mutex.h>
18#include <linux/spinlock.h>
19#include <linux/errno.h>
20#include <linux/cpufreq.h>
21#include <linux/cpu.h>
22#include <linux/regulator/consumer.h>
23
24#include <asm/cpu.h>
25
26#include <mach/board.h>
27#include <mach/msm_iomap.h>
28#include <mach/msm_bus.h>
29#include <mach/msm_bus_board.h>
30#include <mach/socinfo.h>
31#include <mach/rpm-regulator.h>
32
33#include "acpuclock.h"
34#include "avs.h"
35
36/* Frequency switch modes. */
37#define SHOT_SWITCH 4
38#define HOP_SWITCH 5
39#define SIMPLE_SLEW 6
40#define COMPLEX_SLEW 7
41
42/* PLL calibration limits.
43 * The PLL hardware is capable of 384MHz to 1536MHz. The L_VALs
44 * used for calibration should respect these limits. */
45#define L_VAL_SCPLL_CAL_MIN 0x08 /* = 432 MHz with 27MHz source */
46#define L_VAL_SCPLL_CAL_MAX 0x1C /* = 1512 MHz with 27MHz source */
47
48#define MAX_VDD_SC 1250000 /* uV */
49#define MAX_VDD_MEM 1250000 /* uV */
50#define MAX_VDD_DIG 1200000 /* uV */
51#define MAX_AXI 310500 /* KHz */
52#define SCPLL_LOW_VDD_FMAX 594000 /* KHz */
53#define SCPLL_LOW_VDD 1000000 /* uV */
54#define SCPLL_NOMINAL_VDD 1100000 /* uV */
55
56/* SCPLL Modes. */
57#define SCPLL_POWER_DOWN 0
58#define SCPLL_BYPASS 1
59#define SCPLL_STANDBY 2
60#define SCPLL_FULL_CAL 4
61#define SCPLL_HALF_CAL 5
62#define SCPLL_STEP_CAL 6
63#define SCPLL_NORMAL 7
64
65#define SCPLL_DEBUG_NONE 0
66#define SCPLL_DEBUG_FULL 3
67
68/* SCPLL registers offsets. */
69#define SCPLL_DEBUG_OFFSET 0x0
70#define SCPLL_CTL_OFFSET 0x4
71#define SCPLL_CAL_OFFSET 0x8
72#define SCPLL_STATUS_OFFSET 0x10
73#define SCPLL_CFG_OFFSET 0x1C
74#define SCPLL_FSM_CTL_EXT_OFFSET 0x24
75#define SCPLL_LUT_A_HW_MAX (0x38 + ((L_VAL_SCPLL_CAL_MAX / 4) * 4))
76
77/* Clock registers. */
78#define SPSS0_CLK_CTL_ADDR (MSM_ACC0_BASE + 0x04)
79#define SPSS0_CLK_SEL_ADDR (MSM_ACC0_BASE + 0x08)
80#define SPSS1_CLK_CTL_ADDR (MSM_ACC1_BASE + 0x04)
81#define SPSS1_CLK_SEL_ADDR (MSM_ACC1_BASE + 0x08)
82#define SPSS_L2_CLK_SEL_ADDR (MSM_GCC_BASE + 0x38)
83
84/* PTE EFUSE register. */
85#define QFPROM_PTE_EFUSE_ADDR (MSM_QFPROM_BASE + 0x00C0)
86
87static const void * const clk_ctl_addr[] = {SPSS0_CLK_CTL_ADDR,
88 SPSS1_CLK_CTL_ADDR};
89static const void * const clk_sel_addr[] = {SPSS0_CLK_SEL_ADDR,
90 SPSS1_CLK_SEL_ADDR, SPSS_L2_CLK_SEL_ADDR};
91
92static const int rpm_vreg_voter[] = { RPM_VREG_VOTER1, RPM_VREG_VOTER2 };
93static struct regulator *regulator_sc[NR_CPUS];
94
95enum scplls {
96 CPU0 = 0,
97 CPU1,
98 L2,
99};
100
101static const void * const sc_pll_base[] = {
102 [CPU0] = MSM_SCPLL_BASE + 0x200,
103 [CPU1] = MSM_SCPLL_BASE + 0x300,
104 [L2] = MSM_SCPLL_BASE + 0x400,
105};
106
107enum sc_src {
108 ACPU_AFAB,
109 ACPU_PLL_8,
110 ACPU_SCPLL,
111};
112
113static struct clock_state {
114 struct clkctl_acpu_speed *current_speed[NR_CPUS];
115 struct clkctl_l2_speed *current_l2_speed;
116 spinlock_t l2_lock;
117 struct mutex lock;
118 uint32_t acpu_switch_time_us;
119 uint32_t vdd_switch_time_us;
120 uint32_t max_speed_delta_khz;
121} drv_state;
122
123struct clkctl_l2_speed {
124 unsigned int khz;
125 unsigned int src_sel;
126 unsigned int l_val;
127 unsigned int vdd_dig;
128 unsigned int vdd_mem;
129 unsigned int bw_level;
130};
131
132static struct clkctl_l2_speed *l2_vote[NR_CPUS];
133
134struct clkctl_acpu_speed {
135 unsigned int use_for_scaling[2]; /* One for each CPU. */
136 unsigned int acpuclk_khz;
137 int pll;
138 unsigned int acpuclk_src_sel;
139 unsigned int acpuclk_src_div;
140 unsigned int core_src_sel;
141 unsigned int l_val;
142 struct clkctl_l2_speed *l2_level;
143 unsigned int vdd_sc;
144 unsigned int avsdscr_setting;
145};
146
147/* Instantaneous bandwidth requests in MB/s. */
148#define BW_MBPS(_bw) \
149 { \
150 .vectors = &(struct msm_bus_vectors){ \
151 .src = MSM_BUS_MASTER_AMPSS_M0, \
152 .dst = MSM_BUS_SLAVE_EBI_CH0, \
153 .ib = (_bw) * 1000000UL, \
154 .ab = 0, \
155 }, \
156 .num_paths = 1, \
157 }
158static struct msm_bus_paths bw_level_tbl[] = {
159 [0] = BW_MBPS(824), /* At least 103 MHz on bus. */
160 [1] = BW_MBPS(1336), /* At least 167 MHz on bus. */
161 [2] = BW_MBPS(2008), /* At least 251 MHz on bus. */
162 [3] = BW_MBPS(2480), /* At least 310 MHz on bus. */
163};
164
165static struct msm_bus_scale_pdata bus_client_pdata = {
166 .usecase = bw_level_tbl,
167 .num_usecases = ARRAY_SIZE(bw_level_tbl),
168 .active_only = 1,
169 .name = "acpuclock",
170};
171
172static uint32_t bus_perf_client;
173
174/* L2 frequencies = 2 * 27 MHz * L_VAL */
175static struct clkctl_l2_speed l2_freq_tbl_v2[] = {
176 [0] = { MAX_AXI, 0, 0, 1000000, 1100000, 0},
177 [1] = { 432000, 1, 0x08, 1000000, 1100000, 0},
178 [2] = { 486000, 1, 0x09, 1000000, 1100000, 0},
179 [3] = { 540000, 1, 0x0A, 1000000, 1100000, 0},
180 [4] = { 594000, 1, 0x0B, 1000000, 1100000, 0},
181 [5] = { 648000, 1, 0x0C, 1000000, 1100000, 1},
182 [6] = { 702000, 1, 0x0D, 1100000, 1100000, 1},
183 [7] = { 756000, 1, 0x0E, 1100000, 1100000, 1},
184 [8] = { 810000, 1, 0x0F, 1100000, 1100000, 1},
185 [9] = { 864000, 1, 0x10, 1100000, 1100000, 1},
186 [10] = { 918000, 1, 0x11, 1100000, 1100000, 2},
187 [11] = { 972000, 1, 0x12, 1100000, 1100000, 2},
188 [12] = {1026000, 1, 0x13, 1100000, 1100000, 2},
189 [13] = {1080000, 1, 0x14, 1100000, 1200000, 2},
190 [14] = {1134000, 1, 0x15, 1100000, 1200000, 2},
191 [15] = {1188000, 1, 0x16, 1200000, 1200000, 3},
192 [16] = {1242000, 1, 0x17, 1200000, 1212500, 3},
193 [17] = {1296000, 1, 0x18, 1200000, 1225000, 3},
194 [18] = {1350000, 1, 0x19, 1200000, 1225000, 3},
195 [19] = {1404000, 1, 0x1A, 1200000, 1250000, 3},
196};
197
198#define L2(x) (&l2_freq_tbl_v2[(x)])
199/* SCPLL frequencies = 2 * 27 MHz * L_VAL */
200static struct clkctl_acpu_speed acpu_freq_tbl_1188mhz[] = {
201 { {1, 1}, 192000, ACPU_PLL_8, 3, 1, 0, 0, L2(1), 812500, 0x03006000},
202 /* MAX_AXI row is used to source CPU cores and L2 from the AFAB clock. */
203 { {0, 0}, MAX_AXI, ACPU_AFAB, 1, 0, 0, 0, L2(0), 875000, 0x03006000},
204 { {1, 1}, 384000, ACPU_PLL_8, 3, 0, 0, 0, L2(1), 875000, 0x03006000},
205 { {1, 1}, 432000, ACPU_SCPLL, 0, 0, 1, 0x08, L2(1), 887500, 0x03006000},
206 { {1, 1}, 486000, ACPU_SCPLL, 0, 0, 1, 0x09, L2(2), 912500, 0x03006000},
207 { {1, 1}, 540000, ACPU_SCPLL, 0, 0, 1, 0x0A, L2(3), 925000, 0x03006000},
208 { {1, 1}, 594000, ACPU_SCPLL, 0, 0, 1, 0x0B, L2(4), 937500, 0x03006000},
209 { {1, 1}, 648000, ACPU_SCPLL, 0, 0, 1, 0x0C, L2(5), 950000, 0x03006000},
210 { {1, 1}, 702000, ACPU_SCPLL, 0, 0, 1, 0x0D, L2(6), 975000, 0x03006000},
211 { {1, 1}, 756000, ACPU_SCPLL, 0, 0, 1, 0x0E, L2(7), 1000000, 0x03006000},
212 { {1, 1}, 810000, ACPU_SCPLL, 0, 0, 1, 0x0F, L2(8), 1012500, 0x03006000},
213 { {1, 1}, 864000, ACPU_SCPLL, 0, 0, 1, 0x10, L2(9), 1037500, 0x03006000},
214 { {1, 1}, 918000, ACPU_SCPLL, 0, 0, 1, 0x11, L2(10), 1062500, 0x03006000},
215 { {1, 1}, 972000, ACPU_SCPLL, 0, 0, 1, 0x12, L2(11), 1087500, 0x03006000},
216 { {1, 1}, 1026000, ACPU_SCPLL, 0, 0, 1, 0x13, L2(12), 1125000, 0x03006000},
217 { {1, 1}, 1080000, ACPU_SCPLL, 0, 0, 1, 0x14, L2(13), 1137500, 0x03006000},
218 { {1, 1}, 1134000, ACPU_SCPLL, 0, 0, 1, 0x15, L2(14), 1162500, 0x03006000},
219 { {1, 1}, 1188000, ACPU_SCPLL, 0, 0, 1, 0x16, L2(15), 1187500, 0x03006000},
220 { {0, 0}, 0 },
221};
222
223/* SCPLL frequencies = 2 * 27 MHz * L_VAL */
224static struct clkctl_acpu_speed acpu_freq_tbl_slow[] = {
225 { {1, 1}, 192000, ACPU_PLL_8, 3, 1, 0, 0, L2(1), 812500, 0x03006000},
226 /* MAX_AXI row is used to source CPU cores and L2 from the AFAB clock. */
227 { {0, 0}, MAX_AXI, ACPU_AFAB, 1, 0, 0, 0, L2(0), 875000, 0x03006000},
228 { {1, 1}, 384000, ACPU_PLL_8, 3, 0, 0, 0, L2(1), 875000, 0x03006000},
229 { {1, 1}, 432000, ACPU_SCPLL, 0, 0, 1, 0x08, L2(1), 887500, 0x03006000},
230 { {1, 1}, 486000, ACPU_SCPLL, 0, 0, 1, 0x09, L2(2), 912500, 0x03006000},
231 { {1, 1}, 540000, ACPU_SCPLL, 0, 0, 1, 0x0A, L2(3), 925000, 0x03006000},
232 { {1, 1}, 594000, ACPU_SCPLL, 0, 0, 1, 0x0B, L2(4), 937500, 0x03006000},
233 { {1, 1}, 648000, ACPU_SCPLL, 0, 0, 1, 0x0C, L2(5), 950000, 0x03006000},
234 { {1, 1}, 702000, ACPU_SCPLL, 0, 0, 1, 0x0D, L2(6), 975000, 0x03006000},
235 { {1, 1}, 756000, ACPU_SCPLL, 0, 0, 1, 0x0E, L2(7), 1000000, 0x03006000},
236 { {1, 1}, 810000, ACPU_SCPLL, 0, 0, 1, 0x0F, L2(8), 1012500, 0x03006000},
237 { {1, 1}, 864000, ACPU_SCPLL, 0, 0, 1, 0x10, L2(9), 1037500, 0x03006000},
238 { {1, 1}, 918000, ACPU_SCPLL, 0, 0, 1, 0x11, L2(10), 1062500, 0x03006000},
239 { {1, 1}, 972000, ACPU_SCPLL, 0, 0, 1, 0x12, L2(11), 1087500, 0x03006000},
240 { {1, 1}, 1026000, ACPU_SCPLL, 0, 0, 1, 0x13, L2(12), 1100000, 0x03006000},
241 { {1, 1}, 1080000, ACPU_SCPLL, 0, 0, 1, 0x14, L2(13), 1112500, 0x03006000},
242 { {1, 1}, 1134000, ACPU_SCPLL, 0, 0, 1, 0x15, L2(14), 1125000, 0x03006000},
243 { {1, 1}, 1188000, ACPU_SCPLL, 0, 0, 1, 0x16, L2(15), 1137500, 0x03006000},
244 { {1, 1}, 1242000, ACPU_SCPLL, 0, 0, 1, 0x17, L2(16), 1150000, 0x03006000},
245 { {1, 1}, 1296000, ACPU_SCPLL, 0, 0, 1, 0x18, L2(17), 1175000, 0x03006000},
246 { {1, 1}, 1350000, ACPU_SCPLL, 0, 0, 1, 0x19, L2(18), 1200000, 0x03006000},
247 { {1, 1}, 1404000, ACPU_SCPLL, 0, 0, 1, 0x1A, L2(19), 1225000, 0x03006000},
248 { {1, 1}, 1458000, ACPU_SCPLL, 0, 0, 1, 0x1B, L2(19), 1237500, 0x03006000},
249 { {1, 1}, 1512000, ACPU_SCPLL, 0, 0, 1, 0x1C, L2(19), 1250000, 0x03006000},
250 { {0, 0}, 0 },
251};
252
253/* SCPLL frequencies = 2 * 27 MHz * L_VAL */
254static struct clkctl_acpu_speed acpu_freq_tbl_nom[] = {
255 { {1, 1}, 192000, ACPU_PLL_8, 3, 1, 0, 0, L2(1), 812500, 0x03006000},
256 /* MAX_AXI row is used to source CPU cores and L2 from the AFAB clock. */
257 { {0, 0}, MAX_AXI, ACPU_AFAB, 1, 0, 0, 0, L2(0), 875000, 0x03006000},
258 { {1, 1}, 384000, ACPU_PLL_8, 3, 0, 0, 0, L2(1), 875000, 0x03006000},
259 { {1, 1}, 432000, ACPU_SCPLL, 0, 0, 1, 0x08, L2(1), 887500, 0x03006000},
260 { {1, 1}, 486000, ACPU_SCPLL, 0, 0, 1, 0x09, L2(2), 912500, 0x03006000},
261 { {1, 1}, 540000, ACPU_SCPLL, 0, 0, 1, 0x0A, L2(3), 925000, 0x03006000},
262 { {1, 1}, 594000, ACPU_SCPLL, 0, 0, 1, 0x0B, L2(4), 937500, 0x03006000},
263 { {1, 1}, 648000, ACPU_SCPLL, 0, 0, 1, 0x0C, L2(5), 950000, 0x03006000},
264 { {1, 1}, 702000, ACPU_SCPLL, 0, 0, 1, 0x0D, L2(6), 975000, 0x03006000},
265 { {1, 1}, 756000, ACPU_SCPLL, 0, 0, 1, 0x0E, L2(7), 1000000, 0x03006000},
266 { {1, 1}, 810000, ACPU_SCPLL, 0, 0, 1, 0x0F, L2(8), 1012500, 0x03006000},
267 { {1, 1}, 864000, ACPU_SCPLL, 0, 0, 1, 0x10, L2(9), 1037500, 0x03006000},
268 { {1, 1}, 918000, ACPU_SCPLL, 0, 0, 1, 0x11, L2(10), 1062500, 0x03006000},
269 { {1, 1}, 972000, ACPU_SCPLL, 0, 0, 1, 0x12, L2(11), 1062500, 0x03006000},
270 { {1, 1}, 1026000, ACPU_SCPLL, 0, 0, 1, 0x13, L2(12), 1075000, 0x03006000},
271 { {1, 1}, 1080000, ACPU_SCPLL, 0, 0, 1, 0x14, L2(13), 1087500, 0x03006000},
272 { {1, 1}, 1134000, ACPU_SCPLL, 0, 0, 1, 0x15, L2(14), 1100000, 0x03006000},
273 { {1, 1}, 1188000, ACPU_SCPLL, 0, 0, 1, 0x16, L2(15), 1112500, 0x03006000},
274 { {1, 1}, 1242000, ACPU_SCPLL, 0, 0, 1, 0x17, L2(16), 1125000, 0x03006000},
275 { {1, 1}, 1296000, ACPU_SCPLL, 0, 0, 1, 0x18, L2(17), 1150000, 0x03006000},
276 { {1, 1}, 1350000, ACPU_SCPLL, 0, 0, 1, 0x19, L2(18), 1175000, 0x03006000},
277 { {1, 1}, 1404000, ACPU_SCPLL, 0, 0, 1, 0x1A, L2(19), 1200000, 0x03006000},
278 { {1, 1}, 1458000, ACPU_SCPLL, 0, 0, 1, 0x1B, L2(19), 1212500, 0x03006000},
279 { {1, 1}, 1512000, ACPU_SCPLL, 0, 0, 1, 0x1C, L2(19), 1225000, 0x03006000},
280 { {0, 0}, 0 },
281};
282
283/* SCPLL frequencies = 2 * 27 MHz * L_VAL */
284static struct clkctl_acpu_speed acpu_freq_tbl_fast[] = {
285 { {1, 1}, 192000, ACPU_PLL_8, 3, 1, 0, 0, L2(1), 812500, 0x03006000},
286 /* MAX_AXI row is used to source CPU cores and L2 from the AFAB clock. */
287 { {0, 0}, MAX_AXI, ACPU_AFAB, 1, 0, 0, 0, L2(0), 875000, 0x03006000},
288 { {1, 1}, 384000, ACPU_PLL_8, 3, 0, 0, 0, L2(1), 875000, 0x03006000},
289 { {1, 1}, 432000, ACPU_SCPLL, 0, 0, 1, 0x08, L2(1), 887500, 0x03006000},
290 { {1, 1}, 486000, ACPU_SCPLL, 0, 0, 1, 0x09, L2(2), 912500, 0x03006000},
291 { {1, 1}, 540000, ACPU_SCPLL, 0, 0, 1, 0x0A, L2(3), 925000, 0x03006000},
292 { {1, 1}, 594000, ACPU_SCPLL, 0, 0, 1, 0x0B, L2(4), 937500, 0x03006000},
293 { {1, 1}, 648000, ACPU_SCPLL, 0, 0, 1, 0x0C, L2(5), 950000, 0x03006000},
294 { {1, 1}, 702000, ACPU_SCPLL, 0, 0, 1, 0x0D, L2(6), 975000, 0x03006000},
295 { {1, 1}, 756000, ACPU_SCPLL, 0, 0, 1, 0x0E, L2(7), 1000000, 0x03006000},
296 { {1, 1}, 810000, ACPU_SCPLL, 0, 0, 1, 0x0F, L2(8), 1012500, 0x03006000},
297 { {1, 1}, 864000, ACPU_SCPLL, 0, 0, 1, 0x10, L2(9), 1037500, 0x03006000},
298 { {1, 1}, 918000, ACPU_SCPLL, 0, 0, 1, 0x11, L2(10), 1037500, 0x03006000},
299 { {1, 1}, 972000, ACPU_SCPLL, 0, 0, 1, 0x12, L2(11), 1037500, 0x03006000},
300 { {1, 1}, 1026000, ACPU_SCPLL, 0, 0, 1, 0x13, L2(12), 1050000, 0x03006000},
301 { {1, 1}, 1080000, ACPU_SCPLL, 0, 0, 1, 0x14, L2(13), 1062500, 0x03006000},
302 { {1, 1}, 1134000, ACPU_SCPLL, 0, 0, 1, 0x15, L2(14), 1075000, 0x03006000},
303 { {1, 1}, 1188000, ACPU_SCPLL, 0, 0, 1, 0x16, L2(15), 1087500, 0x03006000},
304 { {1, 1}, 1242000, ACPU_SCPLL, 0, 0, 1, 0x17, L2(16), 1100000, 0x03006000},
305 { {1, 1}, 1296000, ACPU_SCPLL, 0, 0, 1, 0x18, L2(17), 1125000, 0x03006000},
306 { {1, 1}, 1350000, ACPU_SCPLL, 0, 0, 1, 0x19, L2(18), 1150000, 0x03006000},
307 { {1, 1}, 1404000, ACPU_SCPLL, 0, 0, 1, 0x1A, L2(19), 1175000, 0x03006000},
308 { {1, 1}, 1458000, ACPU_SCPLL, 0, 0, 1, 0x1B, L2(19), 1187500, 0x03006000},
309 { {1, 1}, 1512000, ACPU_SCPLL, 0, 0, 1, 0x1C, L2(19), 1200000, 0x03006000},
310 { {0, 0}, 0 },
311};
312
313
314/* acpu_freq_tbl row to use when reconfiguring SC/L2 PLLs. */
315#define CAL_IDX 1
316
317static struct clkctl_acpu_speed *acpu_freq_tbl;
318static struct clkctl_l2_speed *l2_freq_tbl = l2_freq_tbl_v2;
319static unsigned int l2_freq_tbl_size = ARRAY_SIZE(l2_freq_tbl_v2);
320
321unsigned long acpuclk_get_rate(int cpu)
322{
323 return drv_state.current_speed[cpu]->acpuclk_khz;
324}
325
326uint32_t acpuclk_get_switch_time(void)
327{
328 return drv_state.acpu_switch_time_us;
329}
330
331#define POWER_COLLAPSE_KHZ MAX_AXI
332unsigned long acpuclk_power_collapse(void)
333{
334 int ret = acpuclk_get_rate(smp_processor_id());
335 acpuclk_set_rate(smp_processor_id(), POWER_COLLAPSE_KHZ, SETRATE_PC);
336 return ret;
337}
338
339#define WAIT_FOR_IRQ_KHZ MAX_AXI
340unsigned long acpuclk_wait_for_irq(void)
341{
342 int ret = acpuclk_get_rate(smp_processor_id());
343 acpuclk_set_rate(smp_processor_id(), WAIT_FOR_IRQ_KHZ, SETRATE_SWFI);
344 return ret;
345}
346
347static void select_core_source(unsigned int id, unsigned int src)
348{
349 uint32_t regval;
350 int shift;
351
352 shift = (id == L2) ? 0 : 1;
353 regval = readl_relaxed(clk_sel_addr[id]);
354 regval &= ~(0x3 << shift);
355 regval |= (src << shift);
356 writel_relaxed(regval, clk_sel_addr[id]);
357}
358
359static void select_clk_source_div(unsigned int id, struct clkctl_acpu_speed *s)
360{
361 uint32_t reg_clksel, reg_clkctl, src_sel;
362
363 /* Configure the PLL divider mux if we plan to use it. */
364 if (s->core_src_sel == 0) {
365
366 reg_clksel = readl_relaxed(clk_sel_addr[id]);
367
368 /* CLK_SEL_SRC1N0 (bank) bit. */
369 src_sel = reg_clksel & 1;
370
371 /* Program clock source and divider. */
372 reg_clkctl = readl_relaxed(clk_ctl_addr[id]);
373 reg_clkctl &= ~(0xFF << (8 * src_sel));
374 reg_clkctl |= s->acpuclk_src_sel << (4 + 8 * src_sel);
375 reg_clkctl |= s->acpuclk_src_div << (0 + 8 * src_sel);
376 writel_relaxed(reg_clkctl, clk_ctl_addr[id]);
377
378 /* Toggle clock source. */
379 reg_clksel ^= 1;
380
381 /* Program clock source selection. */
382 writel_relaxed(reg_clksel, clk_sel_addr[id]);
383 }
384}
385
386static void scpll_enable(int sc_pll, uint32_t l_val)
387{
388 uint32_t regval;
389
390 /* Power-up SCPLL into standby mode. */
391 writel_relaxed(SCPLL_STANDBY, sc_pll_base[sc_pll] + SCPLL_CTL_OFFSET);
392 mb();
393 udelay(10);
394
395 /* Shot-switch to target frequency. */
396 regval = (l_val << 3) | SHOT_SWITCH;
397 writel_relaxed(regval, sc_pll_base[sc_pll] + SCPLL_FSM_CTL_EXT_OFFSET);
398 writel_relaxed(SCPLL_NORMAL, sc_pll_base[sc_pll] + SCPLL_CTL_OFFSET);
399 mb();
400 udelay(20);
401}
402
403static void scpll_disable(int sc_pll)
404{
405 /* Power down SCPLL. */
406 writel_relaxed(SCPLL_POWER_DOWN,
407 sc_pll_base[sc_pll] + SCPLL_CTL_OFFSET);
408}
409
410static void scpll_change_freq(int sc_pll, uint32_t l_val)
411{
412 uint32_t regval;
413 const void *base_addr = sc_pll_base[sc_pll];
414
415 /* Complex-slew switch to target frequency. */
416 regval = (l_val << 3) | COMPLEX_SLEW;
417 writel_relaxed(regval, base_addr + SCPLL_FSM_CTL_EXT_OFFSET);
418 writel_relaxed(SCPLL_NORMAL, base_addr + SCPLL_CTL_OFFSET);
419
420 /* Wait for frequency switch to start. */
421 while (((readl_relaxed(base_addr + SCPLL_CTL_OFFSET) >> 3) & 0x3F)
422 != l_val)
423 cpu_relax();
424 /* Wait for frequency switch to finish. */
425 while (readl_relaxed(base_addr + SCPLL_STATUS_OFFSET) & 0x1)
426 cpu_relax();
427}
428
429/* Vote for the L2 speed and return the speed that should be applied. */
430static struct clkctl_l2_speed *compute_l2_speed(unsigned int voting_cpu,
431 struct clkctl_l2_speed *tgt_s)
432{
433 struct clkctl_l2_speed *new_s;
434 int cpu;
435
436 /* Bounds check. */
437 BUG_ON(tgt_s >= (l2_freq_tbl + l2_freq_tbl_size));
438
439 /* Find max L2 speed vote. */
440 l2_vote[voting_cpu] = tgt_s;
441 new_s = l2_freq_tbl;
442 for_each_present_cpu(cpu)
443 new_s = max(new_s, l2_vote[cpu]);
444
445 return new_s;
446}
447
448/* Set the L2's clock speed. */
449static void set_l2_speed(struct clkctl_l2_speed *tgt_s)
450{
451 if (tgt_s == drv_state.current_l2_speed)
452 return;
453
454 if (drv_state.current_l2_speed->src_sel == 1
455 && tgt_s->src_sel == 1)
456 scpll_change_freq(L2, tgt_s->l_val);
457 else {
458 if (tgt_s->src_sel == 1) {
459 scpll_enable(L2, tgt_s->l_val);
460 mb();
461 select_core_source(L2, tgt_s->src_sel);
462 } else {
463 select_core_source(L2, tgt_s->src_sel);
464 mb();
465 scpll_disable(L2);
466 }
467 }
468 drv_state.current_l2_speed = tgt_s;
469}
470
471/* Update the bus bandwidth request. */
472static void set_bus_bw(unsigned int bw)
473{
474 int ret;
475
476 /* Bounds check. */
477 if (bw >= ARRAY_SIZE(bw_level_tbl)) {
478 pr_err("%s: invalid bandwidth request (%d)\n", __func__, bw);
479 return;
480 }
481
482 /* Update bandwidth if requst has changed. This may sleep. */
483 ret = msm_bus_scale_client_update_request(bus_perf_client, bw);
484 if (ret)
485 pr_err("%s: bandwidth request failed (%d)\n", __func__, ret);
486
487 return;
488}
489
490/* Apply any per-cpu voltage increases. */
491static int increase_vdd(int cpu, unsigned int vdd_sc, unsigned int vdd_mem,
492 unsigned int vdd_dig, enum setrate_reason reason)
493{
494 int rc = 0;
495
496 /* Increase vdd_mem active-set before vdd_dig and vdd_sc.
497 * vdd_mem should be >= both vdd_sc and vdd_dig. */
498 rc = rpm_vreg_set_voltage(RPM_VREG_ID_PM8058_S0, rpm_vreg_voter[cpu],
499 vdd_mem, MAX_VDD_MEM, 0);
500 if (rc) {
501 pr_err("%s: vdd_mem (cpu%d) increase failed (%d)\n",
502 __func__, cpu, rc);
503 return rc;
504 }
505
506 /* Increase vdd_dig active-set vote. */
507 rc = rpm_vreg_set_voltage(RPM_VREG_ID_PM8058_S1, rpm_vreg_voter[cpu],
508 vdd_dig, MAX_VDD_DIG, 0);
509 if (rc) {
510 pr_err("%s: vdd_dig (cpu%d) increase failed (%d)\n",
511 __func__, cpu, rc);
512 return rc;
513 }
514
515 /* Don't update the Scorpion voltage in the hotplug path. It should
516 * already be correct. Attempting to set it is bad because we don't
517 * know what CPU we are running on at this point, but the Scorpion
518 * regulator API requires we call it from the affected CPU. */
519 if (reason == SETRATE_HOTPLUG)
520 return rc;
521
522 /* Update per-core Scorpion voltage. */
523 rc = regulator_set_voltage(regulator_sc[cpu], vdd_sc, MAX_VDD_SC);
524 if (rc) {
525 pr_err("%s: vdd_sc (cpu%d) increase failed (%d)\n",
526 __func__, cpu, rc);
527 return rc;
528 }
529
530 return rc;
531}
532
533/* Apply any per-cpu voltage decreases. */
534static void decrease_vdd(int cpu, unsigned int vdd_sc, unsigned int vdd_mem,
535 unsigned int vdd_dig, enum setrate_reason reason)
536{
537 int ret;
538
539 /* Update per-core Scorpion voltage. This must be called on the CPU
540 * that's being affected. Don't do this in the hotplug remove path,
541 * where the rail is off and we're executing on the other CPU. */
542 if (reason != SETRATE_HOTPLUG) {
543 ret = regulator_set_voltage(regulator_sc[cpu], vdd_sc,
544 MAX_VDD_SC);
545 if (ret) {
546 pr_err("%s: vdd_sc (cpu%d) decrease failed (%d)\n",
547 __func__, cpu, ret);
548 return;
549 }
550 }
551
552 /* Decrease vdd_dig active-set vote. */
553 ret = rpm_vreg_set_voltage(RPM_VREG_ID_PM8058_S1, rpm_vreg_voter[cpu],
554 vdd_dig, MAX_VDD_DIG, 0);
555 if (ret) {
556 pr_err("%s: vdd_dig (cpu%d) decrease failed (%d)\n",
557 __func__, cpu, ret);
558 return;
559 }
560
561 /* Decrease vdd_mem active-set after vdd_dig and vdd_sc.
562 * vdd_mem should be >= both vdd_sc and vdd_dig. */
563 ret = rpm_vreg_set_voltage(RPM_VREG_ID_PM8058_S0, rpm_vreg_voter[cpu],
564 vdd_mem, MAX_VDD_MEM, 0);
565 if (ret) {
566 pr_err("%s: vdd_mem (cpu%d) decrease failed (%d)\n",
567 __func__, cpu, ret);
568 return;
569 }
570}
571
572static void switch_sc_speed(int cpu, struct clkctl_acpu_speed *tgt_s)
573{
574 struct clkctl_acpu_speed *strt_s = drv_state.current_speed[cpu];
575
576 if (strt_s->pll != ACPU_SCPLL && tgt_s->pll != ACPU_SCPLL) {
577 select_clk_source_div(cpu, tgt_s);
578 /* Select core source because target may be AFAB. */
579 select_core_source(cpu, tgt_s->core_src_sel);
580 } else if (strt_s->pll != ACPU_SCPLL && tgt_s->pll == ACPU_SCPLL) {
581 scpll_enable(cpu, tgt_s->l_val);
582 mb();
583 select_core_source(cpu, tgt_s->core_src_sel);
584 } else if (strt_s->pll == ACPU_SCPLL && tgt_s->pll != ACPU_SCPLL) {
585 select_clk_source_div(cpu, tgt_s);
586 select_core_source(cpu, tgt_s->core_src_sel);
587 /* Core source switch must complete before disabling SCPLL. */
588 mb();
589 udelay(1);
590 scpll_disable(cpu);
591 } else
592 scpll_change_freq(cpu, tgt_s->l_val);
593
594 /* Update the driver state with the new clock freq */
595 drv_state.current_speed[cpu] = tgt_s;
596}
597
598int acpuclk_set_rate(int cpu, unsigned long rate, enum setrate_reason reason)
599{
600 struct clkctl_acpu_speed *tgt_s, *strt_s;
601 struct clkctl_l2_speed *tgt_l2;
602 unsigned int vdd_mem, vdd_dig, pll_vdd_dig;
603 unsigned long flags;
604 int rc = 0;
605
606 if (cpu > num_possible_cpus()) {
607 rc = -EINVAL;
608 goto out;
609 }
610
611 if (reason == SETRATE_CPUFREQ || reason == SETRATE_HOTPLUG)
612 mutex_lock(&drv_state.lock);
613
614 strt_s = drv_state.current_speed[cpu];
615
616 /* Return early if rate didn't change. */
617 if (rate == strt_s->acpuclk_khz)
618 goto out;
619
620 /* Find target frequency. */
621 for (tgt_s = acpu_freq_tbl; tgt_s->acpuclk_khz != 0; tgt_s++)
622 if (tgt_s->acpuclk_khz == rate)
623 break;
624 if (tgt_s->acpuclk_khz == 0) {
625 rc = -EINVAL;
626 goto out;
627 }
628
629 /* AVS needs SAW_VCTL to be intitialized correctly, before enable,
630 * and is not initialized at acpuclk_init().
631 */
632 if (reason == SETRATE_CPUFREQ)
633 AVS_DISABLE(cpu);
634
635 /* Calculate vdd_mem and vdd_dig requirements.
636 * vdd_mem must be >= vdd_sc */
637 vdd_mem = max(tgt_s->vdd_sc, tgt_s->l2_level->vdd_mem);
638 /* Factor-in PLL vdd_dig requirements. */
639 if ((tgt_s->l2_level->khz > SCPLL_LOW_VDD_FMAX) ||
640 (tgt_s->pll == ACPU_SCPLL
641 && tgt_s->acpuclk_khz > SCPLL_LOW_VDD_FMAX))
642 pll_vdd_dig = SCPLL_NOMINAL_VDD;
643 else
644 pll_vdd_dig = SCPLL_LOW_VDD;
645 vdd_dig = max(tgt_s->l2_level->vdd_dig, pll_vdd_dig);
646
647 /* Increase VDD levels if needed. */
648 if ((reason == SETRATE_CPUFREQ || reason == SETRATE_HOTPLUG
649 || reason == SETRATE_INIT)
650 && (tgt_s->acpuclk_khz > strt_s->acpuclk_khz)) {
651 rc = increase_vdd(cpu, tgt_s->vdd_sc, vdd_mem, vdd_dig, reason);
652 if (rc)
653 goto out;
654 }
655
656 pr_debug("Switching from ACPU%d rate %u KHz -> %u KHz\n",
657 cpu, strt_s->acpuclk_khz, tgt_s->acpuclk_khz);
658
659 /* Switch CPU speed. */
660 switch_sc_speed(cpu, tgt_s);
661
662 /* Update the L2 vote and apply the rate change. */
663 spin_lock_irqsave(&drv_state.l2_lock, flags);
664 tgt_l2 = compute_l2_speed(cpu, tgt_s->l2_level);
665 set_l2_speed(tgt_l2);
666 spin_unlock_irqrestore(&drv_state.l2_lock, flags);
667
668 /* Nothing else to do for SWFI. */
669 if (reason == SETRATE_SWFI)
670 goto out;
671
672 /* Nothing else to do for power collapse. */
673 if (reason == SETRATE_PC)
674 goto out;
675
676 /* Update bus bandwith request. */
677 set_bus_bw(tgt_l2->bw_level);
678
679 /* Drop VDD levels if we can. */
680 if (tgt_s->acpuclk_khz < strt_s->acpuclk_khz)
681 decrease_vdd(cpu, tgt_s->vdd_sc, vdd_mem, vdd_dig, reason);
682
683 pr_debug("ACPU%d speed change complete\n", cpu);
684
685 /* Re-enable AVS */
686 if (reason == SETRATE_CPUFREQ)
687 AVS_ENABLE(cpu, tgt_s->avsdscr_setting);
688
689out:
690 if (reason == SETRATE_CPUFREQ || reason == SETRATE_HOTPLUG)
691 mutex_unlock(&drv_state.lock);
692 return rc;
693}
694
695static void __init scpll_init(int sc_pll)
696{
697 uint32_t regval;
698
699 pr_debug("Initializing SCPLL%d\n", sc_pll);
700
701 /* Clear calibration LUT registers containing max frequency entry.
702 * LUT registers are only writeable in debug mode. */
703 writel_relaxed(SCPLL_DEBUG_FULL,
704 sc_pll_base[sc_pll] + SCPLL_DEBUG_OFFSET);
705 writel_relaxed(0x0, sc_pll_base[sc_pll] + SCPLL_LUT_A_HW_MAX);
706 writel_relaxed(SCPLL_DEBUG_NONE,
707 sc_pll_base[sc_pll] + SCPLL_DEBUG_OFFSET);
708
709 /* Power-up SCPLL into standby mode. */
710 writel_relaxed(SCPLL_STANDBY, sc_pll_base[sc_pll] + SCPLL_CTL_OFFSET);
711 mb();
712 udelay(10);
713
714 /* Calibrate the SCPLL to the maximum range supported by the h/w. We
715 * might not use the full range of calibrated frequencies, but this
716 * simplifies changes required for future increases in max CPU freq.
717 */
718 regval = (L_VAL_SCPLL_CAL_MAX << 24) | (L_VAL_SCPLL_CAL_MIN << 16);
719 writel_relaxed(regval, sc_pll_base[sc_pll] + SCPLL_CAL_OFFSET);
720
721 /* Start calibration */
722 writel_relaxed(SCPLL_FULL_CAL, sc_pll_base[sc_pll] + SCPLL_CTL_OFFSET);
723
724 /* Wait for proof that calibration has started before checking the
725 * 'calibration done' bit in the status register. Waiting for the
726 * LUT register we cleared to contain data accomplishes this.
727 * This is required since the 'calibration done' bit takes time to
728 * transition from 'done' to 'not done' when starting a calibration.
729 */
730 while (readl_relaxed(sc_pll_base[sc_pll] + SCPLL_LUT_A_HW_MAX) == 0)
731 cpu_relax();
732
733 /* Wait for calibration to complete. */
734 while (readl_relaxed(sc_pll_base[sc_pll] + SCPLL_STATUS_OFFSET) & 0x2)
735 cpu_relax();
736
737 /* Power-down SCPLL. */
738 scpll_disable(sc_pll);
739}
740
741/* Force ACPU core and L2 cache clocks to rates that don't require SCPLLs. */
742static void __init unselect_scplls(void)
743{
744 int cpu;
745
746 /* Ensure CAL_IDX frequency uses AFAB sources for CPU cores and L2. */
747 BUG_ON(acpu_freq_tbl[CAL_IDX].core_src_sel != 0);
748 BUG_ON(acpu_freq_tbl[CAL_IDX].l2_level->src_sel != 0);
749
750 for_each_possible_cpu(cpu) {
751 select_clk_source_div(cpu, &acpu_freq_tbl[CAL_IDX]);
752 select_core_source(cpu, acpu_freq_tbl[CAL_IDX].core_src_sel);
753 drv_state.current_speed[cpu] = &acpu_freq_tbl[CAL_IDX];
754 l2_vote[cpu] = acpu_freq_tbl[CAL_IDX].l2_level;
755 }
756
757 select_core_source(L2, acpu_freq_tbl[CAL_IDX].l2_level->src_sel);
758 drv_state.current_l2_speed = acpu_freq_tbl[CAL_IDX].l2_level;
759}
760
761/* Ensure SCPLLs use the 27MHz PXO. */
762static void __init scpll_set_refs(void)
763{
764 int cpu;
765 uint32_t regval;
766
767 /* Bit 4 = 0:PXO, 1:MXO. */
768 for_each_possible_cpu(cpu) {
769 regval = readl_relaxed(sc_pll_base[cpu] + SCPLL_CFG_OFFSET);
770 regval &= ~BIT(4);
771 writel_relaxed(regval, sc_pll_base[cpu] + SCPLL_CFG_OFFSET);
772 }
773 regval = readl_relaxed(sc_pll_base[L2] + SCPLL_CFG_OFFSET);
774 regval &= ~BIT(4);
775 writel_relaxed(regval, sc_pll_base[L2] + SCPLL_CFG_OFFSET);
776}
777
778/* Voltage regulator initialization. */
779static void __init regulator_init(void)
780{
781 struct clkctl_acpu_speed **freq = drv_state.current_speed;
782 const char *regulator_sc_name[] = {"8901_s0", "8901_s1"};
783 int cpu, ret;
784
785 for_each_possible_cpu(cpu) {
786 /* VDD_SC0, VDD_SC1 */
787 regulator_sc[cpu] = regulator_get(NULL, regulator_sc_name[cpu]);
788 if (IS_ERR(regulator_sc[cpu]))
789 goto err;
790 ret = regulator_set_voltage(regulator_sc[cpu],
791 freq[cpu]->vdd_sc, MAX_VDD_SC);
792 if (ret)
793 goto err;
794 ret = regulator_enable(regulator_sc[cpu]);
795 if (ret)
796 goto err;
797 }
798
799 return;
800
801err:
802 pr_err("%s: Failed to initialize voltage regulators\n", __func__);
803 BUG();
804}
805
806/* Register with bus driver. */
807static void __init bus_init(void)
808{
809 bus_perf_client = msm_bus_scale_register_client(&bus_client_pdata);
810 if (!bus_perf_client) {
811 pr_err("%s: unable register bus client\n", __func__);
812 BUG();
813 }
814}
815
816#ifdef CONFIG_CPU_FREQ_MSM
817static struct cpufreq_frequency_table freq_table[NR_CPUS][30];
818
819static void __init cpufreq_table_init(void)
820{
821 int cpu;
822
823 for_each_possible_cpu(cpu) {
824 int i, freq_cnt = 0;
825 /* Construct the freq_table tables from acpu_freq_tbl. */
826 for (i = 0; acpu_freq_tbl[i].acpuclk_khz != 0
827 && freq_cnt < ARRAY_SIZE(*freq_table); i++) {
828 if (acpu_freq_tbl[i].use_for_scaling[cpu]) {
829 freq_table[cpu][freq_cnt].index = freq_cnt;
830 freq_table[cpu][freq_cnt].frequency
831 = acpu_freq_tbl[i].acpuclk_khz;
832 freq_cnt++;
833 }
834 }
835 /* freq_table not big enough to store all usable freqs. */
836 BUG_ON(acpu_freq_tbl[i].acpuclk_khz != 0);
837
838 freq_table[cpu][freq_cnt].index = freq_cnt;
839 freq_table[cpu][freq_cnt].frequency = CPUFREQ_TABLE_END;
840
841 pr_info("CPU%d: %d scaling frequencies supported.\n",
842 cpu, freq_cnt);
843
844 /* Register table with CPUFreq. */
845 cpufreq_frequency_table_get_attr(freq_table[cpu], cpu);
846 }
847}
848#else
849static void __init cpufreq_table_init(void) {}
850#endif
851
852#define HOT_UNPLUG_KHZ MAX_AXI
853static int __cpuinit acpuclock_cpu_callback(struct notifier_block *nfb,
854 unsigned long action, void *hcpu)
855{
856 static int prev_khz[NR_CPUS];
857 int cpu = (int)hcpu;
858
859 switch (action) {
860 case CPU_DEAD:
861 case CPU_DEAD_FROZEN:
862 prev_khz[cpu] = acpuclk_get_rate(cpu);
863 /* Fall through. */
864 case CPU_UP_CANCELED:
865 case CPU_UP_CANCELED_FROZEN:
866 acpuclk_set_rate(cpu, HOT_UNPLUG_KHZ, SETRATE_HOTPLUG);
867 break;
868 case CPU_UP_PREPARE:
869 case CPU_UP_PREPARE_FROZEN:
870 if (WARN_ON(!prev_khz[cpu]))
871 prev_khz[cpu] = acpu_freq_tbl->acpuclk_khz;
872 acpuclk_set_rate(cpu, prev_khz[cpu], SETRATE_HOTPLUG);
873 break;
874 default:
875 break;
876 }
877
878 return NOTIFY_OK;
879}
880
881static struct notifier_block __cpuinitdata acpuclock_cpu_notifier = {
882 .notifier_call = acpuclock_cpu_callback,
883};
884
885static unsigned int __init select_freq_plan(void)
886{
887 uint32_t pte_efuse, speed_bin, pvs, max_khz;
888 struct clkctl_acpu_speed *f;
889
890 pte_efuse = readl_relaxed(QFPROM_PTE_EFUSE_ADDR);
891
892 speed_bin = pte_efuse & 0xF;
893 if (speed_bin == 0xF)
894 speed_bin = (pte_efuse >> 4) & 0xF;
895
896 if (speed_bin == 0x1) {
897 max_khz = 1512000;
898 pvs = (pte_efuse >> 10) & 0x7;
899 if (pvs == 0x7)
900 pvs = (pte_efuse >> 13) & 0x7;
901
902 switch (pvs) {
903 case 0x0:
904 case 0x7:
905 acpu_freq_tbl = acpu_freq_tbl_slow;
906 pr_info("ACPU PVS: Slow\n");
907 break;
908 case 0x1:
909 acpu_freq_tbl = acpu_freq_tbl_nom;
910 pr_info("ACPU PVS: Nominal\n");
911 break;
912 case 0x3:
913 acpu_freq_tbl = acpu_freq_tbl_fast;
914 pr_info("ACPU PVS: Fast\n");
915 break;
916 default:
917 acpu_freq_tbl = acpu_freq_tbl_slow;
918 pr_warn("ACPU PVS: Unknown. Defaulting to slow.\n");
919 break;
920 }
921 } else {
922 max_khz = 1188000;
923 acpu_freq_tbl = acpu_freq_tbl_1188mhz;
924 }
925
926 /* Truncate the table based to max_khz. */
927 for (f = acpu_freq_tbl; f->acpuclk_khz != 0; f++) {
928 if (f->acpuclk_khz > max_khz) {
929 f->acpuclk_khz = 0;
930 break;
931 }
932 }
933 f--;
934 pr_info("Max ACPU freq: %u KHz\n", f->acpuclk_khz);
935
936 return f->acpuclk_khz;
937}
938
939void __init msm_acpu_clock_init(struct msm_acpu_clock_platform_data *clkdata)
940{
941 unsigned int max_cpu_khz;
942 int cpu;
943
944 mutex_init(&drv_state.lock);
945 spin_lock_init(&drv_state.l2_lock);
946 drv_state.acpu_switch_time_us = clkdata->acpu_switch_time_us;
947 drv_state.vdd_switch_time_us = clkdata->vdd_switch_time_us;
948
949 /* Configure hardware. */
950 max_cpu_khz = select_freq_plan();
951 unselect_scplls();
952 scpll_set_refs();
953 for_each_possible_cpu(cpu)
954 scpll_init(cpu);
955 scpll_init(L2);
956 regulator_init();
957 bus_init();
958
959 /* Improve boot time by ramping up CPUs immediately. */
960 for_each_online_cpu(cpu)
961 acpuclk_set_rate(cpu, max_cpu_khz, SETRATE_INIT);
962
963 cpufreq_table_init();
964 register_hotcpu_notifier(&acpuclock_cpu_notifier);
965}