blob: 3732de89adc935a7849122acb2be9125ed06c72b [file] [log] [blame]
Sascha Hauer1f1846c2010-10-06 10:25:55 +02001/*
2 * drivers/dma/imx-dma.c
3 *
4 * This file contains a driver for the Freescale i.MX DMA engine
5 * found on i.MX1/21/27
6 *
7 * Copyright 2010 Sascha Hauer, Pengutronix <s.hauer@pengutronix.de>
8 *
9 * The code contained herein is licensed under the GNU General Public
10 * License. You may obtain a copy of the GNU General Public License
11 * Version 2 or later at the following locations:
12 *
13 * http://www.opensource.org/licenses/gpl-license.html
14 * http://www.gnu.org/copyleft/gpl.html
15 */
16#include <linux/init.h>
17#include <linux/types.h>
18#include <linux/mm.h>
19#include <linux/interrupt.h>
20#include <linux/spinlock.h>
21#include <linux/device.h>
22#include <linux/dma-mapping.h>
23#include <linux/slab.h>
24#include <linux/platform_device.h>
25#include <linux/dmaengine.h>
Paul Gortmaker5c45ad72011-07-31 16:14:17 -040026#include <linux/module.h>
Sascha Hauer1f1846c2010-10-06 10:25:55 +020027
28#include <asm/irq.h>
29#include <mach/dma-v1.h>
30#include <mach/hardware.h>
31
32struct imxdma_channel {
33 struct imxdma_engine *imxdma;
34 unsigned int channel;
35 unsigned int imxdma_channel;
36
37 enum dma_slave_buswidth word_size;
38 dma_addr_t per_address;
39 u32 watermark_level;
40 struct dma_chan chan;
41 spinlock_t lock;
42 struct dma_async_tx_descriptor desc;
43 dma_cookie_t last_completed;
44 enum dma_status status;
45 int dma_request;
46 struct scatterlist *sg_list;
47};
48
49#define MAX_DMA_CHANNELS 8
50
51struct imxdma_engine {
52 struct device *dev;
Sascha Hauer1e070a62011-01-12 13:14:37 +010053 struct device_dma_parameters dma_parms;
Sascha Hauer1f1846c2010-10-06 10:25:55 +020054 struct dma_device dma_device;
55 struct imxdma_channel channel[MAX_DMA_CHANNELS];
56};
57
58static struct imxdma_channel *to_imxdma_chan(struct dma_chan *chan)
59{
60 return container_of(chan, struct imxdma_channel, chan);
61}
62
63static void imxdma_handle(struct imxdma_channel *imxdmac)
64{
65 if (imxdmac->desc.callback)
66 imxdmac->desc.callback(imxdmac->desc.callback_param);
67 imxdmac->last_completed = imxdmac->desc.cookie;
68}
69
70static void imxdma_irq_handler(int channel, void *data)
71{
72 struct imxdma_channel *imxdmac = data;
73
74 imxdmac->status = DMA_SUCCESS;
75 imxdma_handle(imxdmac);
76}
77
78static void imxdma_err_handler(int channel, void *data, int error)
79{
80 struct imxdma_channel *imxdmac = data;
81
82 imxdmac->status = DMA_ERROR;
83 imxdma_handle(imxdmac);
84}
85
86static void imxdma_progression(int channel, void *data,
87 struct scatterlist *sg)
88{
89 struct imxdma_channel *imxdmac = data;
90
91 imxdmac->status = DMA_SUCCESS;
92 imxdma_handle(imxdmac);
93}
94
95static int imxdma_control(struct dma_chan *chan, enum dma_ctrl_cmd cmd,
96 unsigned long arg)
97{
98 struct imxdma_channel *imxdmac = to_imxdma_chan(chan);
99 struct dma_slave_config *dmaengine_cfg = (void *)arg;
100 int ret;
101 unsigned int mode = 0;
102
103 switch (cmd) {
104 case DMA_TERMINATE_ALL:
105 imxdmac->status = DMA_ERROR;
106 imx_dma_disable(imxdmac->imxdma_channel);
107 return 0;
108 case DMA_SLAVE_CONFIG:
109 if (dmaengine_cfg->direction == DMA_FROM_DEVICE) {
110 imxdmac->per_address = dmaengine_cfg->src_addr;
111 imxdmac->watermark_level = dmaengine_cfg->src_maxburst;
112 imxdmac->word_size = dmaengine_cfg->src_addr_width;
113 } else {
114 imxdmac->per_address = dmaengine_cfg->dst_addr;
115 imxdmac->watermark_level = dmaengine_cfg->dst_maxburst;
116 imxdmac->word_size = dmaengine_cfg->dst_addr_width;
117 }
118
119 switch (imxdmac->word_size) {
120 case DMA_SLAVE_BUSWIDTH_1_BYTE:
121 mode = IMX_DMA_MEMSIZE_8;
122 break;
123 case DMA_SLAVE_BUSWIDTH_2_BYTES:
124 mode = IMX_DMA_MEMSIZE_16;
125 break;
126 default:
127 case DMA_SLAVE_BUSWIDTH_4_BYTES:
128 mode = IMX_DMA_MEMSIZE_32;
129 break;
130 }
131 ret = imx_dma_config_channel(imxdmac->imxdma_channel,
132 mode | IMX_DMA_TYPE_FIFO,
133 IMX_DMA_MEMSIZE_32 | IMX_DMA_TYPE_LINEAR,
134 imxdmac->dma_request, 1);
135
136 if (ret)
137 return ret;
138
Sascha Hauer6584cb82011-07-06 11:18:33 +0200139 imx_dma_config_burstlen(imxdmac->imxdma_channel,
140 imxdmac->watermark_level * imxdmac->word_size);
Sascha Hauer1f1846c2010-10-06 10:25:55 +0200141
142 return 0;
143 default:
144 return -ENOSYS;
145 }
146
147 return -EINVAL;
148}
149
150static enum dma_status imxdma_tx_status(struct dma_chan *chan,
151 dma_cookie_t cookie,
152 struct dma_tx_state *txstate)
153{
154 struct imxdma_channel *imxdmac = to_imxdma_chan(chan);
155 dma_cookie_t last_used;
156 enum dma_status ret;
157
158 last_used = chan->cookie;
159
160 ret = dma_async_is_complete(cookie, imxdmac->last_completed, last_used);
161 dma_set_tx_state(txstate, imxdmac->last_completed, last_used, 0);
162
163 return ret;
164}
165
166static dma_cookie_t imxdma_assign_cookie(struct imxdma_channel *imxdma)
167{
168 dma_cookie_t cookie = imxdma->chan.cookie;
169
170 if (++cookie < 0)
171 cookie = 1;
172
173 imxdma->chan.cookie = cookie;
174 imxdma->desc.cookie = cookie;
175
176 return cookie;
177}
178
179static dma_cookie_t imxdma_tx_submit(struct dma_async_tx_descriptor *tx)
180{
181 struct imxdma_channel *imxdmac = to_imxdma_chan(tx->chan);
182 dma_cookie_t cookie;
183
184 spin_lock_irq(&imxdmac->lock);
185
186 cookie = imxdma_assign_cookie(imxdmac);
187
188 imx_dma_enable(imxdmac->imxdma_channel);
189
190 spin_unlock_irq(&imxdmac->lock);
191
192 return cookie;
193}
194
195static int imxdma_alloc_chan_resources(struct dma_chan *chan)
196{
197 struct imxdma_channel *imxdmac = to_imxdma_chan(chan);
198 struct imx_dma_data *data = chan->private;
199
200 imxdmac->dma_request = data->dma_request;
201
202 dma_async_tx_descriptor_init(&imxdmac->desc, chan);
203 imxdmac->desc.tx_submit = imxdma_tx_submit;
204 /* txd.flags will be overwritten in prep funcs */
205 imxdmac->desc.flags = DMA_CTRL_ACK;
206
207 imxdmac->status = DMA_SUCCESS;
208
209 return 0;
210}
211
212static void imxdma_free_chan_resources(struct dma_chan *chan)
213{
214 struct imxdma_channel *imxdmac = to_imxdma_chan(chan);
215
216 imx_dma_disable(imxdmac->imxdma_channel);
217
218 if (imxdmac->sg_list) {
219 kfree(imxdmac->sg_list);
220 imxdmac->sg_list = NULL;
221 }
222}
223
224static struct dma_async_tx_descriptor *imxdma_prep_slave_sg(
225 struct dma_chan *chan, struct scatterlist *sgl,
226 unsigned int sg_len, enum dma_data_direction direction,
227 unsigned long flags)
228{
229 struct imxdma_channel *imxdmac = to_imxdma_chan(chan);
230 struct scatterlist *sg;
231 int i, ret, dma_length = 0;
232 unsigned int dmamode;
233
234 if (imxdmac->status == DMA_IN_PROGRESS)
235 return NULL;
236
237 imxdmac->status = DMA_IN_PROGRESS;
238
239 for_each_sg(sgl, sg, sg_len, i) {
240 dma_length += sg->length;
241 }
242
243 if (direction == DMA_FROM_DEVICE)
244 dmamode = DMA_MODE_READ;
245 else
246 dmamode = DMA_MODE_WRITE;
247
Sascha Hauerd07102a2011-01-12 14:13:23 +0100248 switch (imxdmac->word_size) {
249 case DMA_SLAVE_BUSWIDTH_4_BYTES:
250 if (sgl->length & 3 || sgl->dma_address & 3)
251 return NULL;
252 break;
253 case DMA_SLAVE_BUSWIDTH_2_BYTES:
254 if (sgl->length & 1 || sgl->dma_address & 1)
255 return NULL;
256 break;
257 case DMA_SLAVE_BUSWIDTH_1_BYTE:
258 break;
259 default:
260 return NULL;
261 }
262
Sascha Hauer1f1846c2010-10-06 10:25:55 +0200263 ret = imx_dma_setup_sg(imxdmac->imxdma_channel, sgl, sg_len,
264 dma_length, imxdmac->per_address, dmamode);
265 if (ret)
266 return NULL;
267
268 return &imxdmac->desc;
269}
270
271static struct dma_async_tx_descriptor *imxdma_prep_dma_cyclic(
272 struct dma_chan *chan, dma_addr_t dma_addr, size_t buf_len,
273 size_t period_len, enum dma_data_direction direction)
274{
275 struct imxdma_channel *imxdmac = to_imxdma_chan(chan);
276 struct imxdma_engine *imxdma = imxdmac->imxdma;
277 int i, ret;
278 unsigned int periods = buf_len / period_len;
279 unsigned int dmamode;
280
281 dev_dbg(imxdma->dev, "%s channel: %d buf_len=%d period_len=%d\n",
282 __func__, imxdmac->channel, buf_len, period_len);
283
284 if (imxdmac->status == DMA_IN_PROGRESS)
285 return NULL;
286 imxdmac->status = DMA_IN_PROGRESS;
287
288 ret = imx_dma_setup_progression_handler(imxdmac->imxdma_channel,
289 imxdma_progression);
290 if (ret) {
291 dev_err(imxdma->dev, "Failed to setup the DMA handler\n");
292 return NULL;
293 }
294
295 if (imxdmac->sg_list)
296 kfree(imxdmac->sg_list);
297
298 imxdmac->sg_list = kcalloc(periods + 1,
299 sizeof(struct scatterlist), GFP_KERNEL);
300 if (!imxdmac->sg_list)
301 return NULL;
302
303 sg_init_table(imxdmac->sg_list, periods);
304
305 for (i = 0; i < periods; i++) {
306 imxdmac->sg_list[i].page_link = 0;
307 imxdmac->sg_list[i].offset = 0;
308 imxdmac->sg_list[i].dma_address = dma_addr;
309 imxdmac->sg_list[i].length = period_len;
310 dma_addr += period_len;
311 }
312
313 /* close the loop */
314 imxdmac->sg_list[periods].offset = 0;
315 imxdmac->sg_list[periods].length = 0;
316 imxdmac->sg_list[periods].page_link =
317 ((unsigned long)imxdmac->sg_list | 0x01) & ~0x02;
318
319 if (direction == DMA_FROM_DEVICE)
320 dmamode = DMA_MODE_READ;
321 else
322 dmamode = DMA_MODE_WRITE;
323
324 ret = imx_dma_setup_sg(imxdmac->imxdma_channel, imxdmac->sg_list, periods,
325 IMX_DMA_LENGTH_LOOP, imxdmac->per_address, dmamode);
326 if (ret)
327 return NULL;
328
329 return &imxdmac->desc;
330}
331
332static void imxdma_issue_pending(struct dma_chan *chan)
333{
334 /*
335 * Nothing to do. We only have a single descriptor
336 */
337}
338
339static int __init imxdma_probe(struct platform_device *pdev)
340{
341 struct imxdma_engine *imxdma;
342 int ret, i;
343
344 imxdma = kzalloc(sizeof(*imxdma), GFP_KERNEL);
345 if (!imxdma)
346 return -ENOMEM;
347
348 INIT_LIST_HEAD(&imxdma->dma_device.channels);
349
Sascha Hauerf8a356f2011-01-31 11:35:59 +0100350 dma_cap_set(DMA_SLAVE, imxdma->dma_device.cap_mask);
351 dma_cap_set(DMA_CYCLIC, imxdma->dma_device.cap_mask);
352
Sascha Hauer1f1846c2010-10-06 10:25:55 +0200353 /* Initialize channel parameters */
354 for (i = 0; i < MAX_DMA_CHANNELS; i++) {
355 struct imxdma_channel *imxdmac = &imxdma->channel[i];
356
357 imxdmac->imxdma_channel = imx_dma_request_by_prio("dmaengine",
358 DMA_PRIO_MEDIUM);
Sascha Hauer8267f162010-10-20 08:37:19 +0200359 if ((int)imxdmac->channel < 0) {
360 ret = -ENODEV;
Sascha Hauer1f1846c2010-10-06 10:25:55 +0200361 goto err_init;
Sascha Hauer8267f162010-10-20 08:37:19 +0200362 }
Sascha Hauer1f1846c2010-10-06 10:25:55 +0200363
364 imx_dma_setup_handlers(imxdmac->imxdma_channel,
365 imxdma_irq_handler, imxdma_err_handler, imxdmac);
366
367 imxdmac->imxdma = imxdma;
368 spin_lock_init(&imxdmac->lock);
369
Sascha Hauer1f1846c2010-10-06 10:25:55 +0200370 imxdmac->chan.device = &imxdma->dma_device;
Sascha Hauer1f1846c2010-10-06 10:25:55 +0200371 imxdmac->channel = i;
372
373 /* Add the channel to the DMAC list */
374 list_add_tail(&imxdmac->chan.device_node, &imxdma->dma_device.channels);
375 }
376
377 imxdma->dev = &pdev->dev;
378 imxdma->dma_device.dev = &pdev->dev;
379
380 imxdma->dma_device.device_alloc_chan_resources = imxdma_alloc_chan_resources;
381 imxdma->dma_device.device_free_chan_resources = imxdma_free_chan_resources;
382 imxdma->dma_device.device_tx_status = imxdma_tx_status;
383 imxdma->dma_device.device_prep_slave_sg = imxdma_prep_slave_sg;
384 imxdma->dma_device.device_prep_dma_cyclic = imxdma_prep_dma_cyclic;
385 imxdma->dma_device.device_control = imxdma_control;
386 imxdma->dma_device.device_issue_pending = imxdma_issue_pending;
387
388 platform_set_drvdata(pdev, imxdma);
389
Sascha Hauer1e070a62011-01-12 13:14:37 +0100390 imxdma->dma_device.dev->dma_parms = &imxdma->dma_parms;
391 dma_set_max_seg_size(imxdma->dma_device.dev, 0xffffff);
392
Sascha Hauer1f1846c2010-10-06 10:25:55 +0200393 ret = dma_async_device_register(&imxdma->dma_device);
394 if (ret) {
395 dev_err(&pdev->dev, "unable to register\n");
396 goto err_init;
397 }
398
399 return 0;
400
401err_init:
Axel Lincbeae412010-11-02 09:12:57 +0800402 while (--i >= 0) {
Sascha Hauer1f1846c2010-10-06 10:25:55 +0200403 struct imxdma_channel *imxdmac = &imxdma->channel[i];
404 imx_dma_free(imxdmac->imxdma_channel);
405 }
406
407 kfree(imxdma);
408 return ret;
409}
410
411static int __exit imxdma_remove(struct platform_device *pdev)
412{
413 struct imxdma_engine *imxdma = platform_get_drvdata(pdev);
414 int i;
415
416 dma_async_device_unregister(&imxdma->dma_device);
417
418 for (i = 0; i < MAX_DMA_CHANNELS; i++) {
419 struct imxdma_channel *imxdmac = &imxdma->channel[i];
420
421 imx_dma_free(imxdmac->imxdma_channel);
422 }
423
424 kfree(imxdma);
425
426 return 0;
427}
428
429static struct platform_driver imxdma_driver = {
430 .driver = {
431 .name = "imx-dma",
432 },
433 .remove = __exit_p(imxdma_remove),
434};
435
436static int __init imxdma_module_init(void)
437{
438 return platform_driver_probe(&imxdma_driver, imxdma_probe);
439}
440subsys_initcall(imxdma_module_init);
441
442MODULE_AUTHOR("Sascha Hauer, Pengutronix <s.hauer@pengutronix.de>");
443MODULE_DESCRIPTION("i.MX dma driver");
444MODULE_LICENSE("GPL");