Greg Kroah-Hartman | 5db6b77 | 2008-08-21 14:04:55 -0700 | [diff] [blame^] | 1 | /************************************************************************** |
| 2 | * |
| 3 | * Copyright © 2000-2008 Alacritech, Inc. All rights reserved. |
| 4 | * |
| 5 | * $Id: sxg.h,v 1.3 2008/07/24 17:25:08 chris Exp $ |
| 6 | * |
| 7 | * Redistribution and use in source and binary forms, with or without |
| 8 | * modification, are permitted provided that the following conditions |
| 9 | * are met: |
| 10 | * |
| 11 | * 1. Redistributions of source code must retain the above copyright |
| 12 | * notice, this list of conditions and the following disclaimer. |
| 13 | * 2. Redistributions in binary form must reproduce the above |
| 14 | * copyright notice, this list of conditions and the following |
| 15 | * disclaimer in the documentation and/or other materials provided |
| 16 | * with the distribution. |
| 17 | * |
| 18 | * THIS SOFTWARE IS PROVIDED BY ALACRITECH, INC. ``AS IS'' AND ANY |
| 19 | * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
| 20 | * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR |
| 21 | * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL ALACRITECH, INC. OR |
| 22 | * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, |
| 23 | * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT |
| 24 | * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF |
| 25 | * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND |
| 26 | * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, |
| 27 | * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT |
| 28 | * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF |
| 29 | * SUCH DAMAGE. |
| 30 | * |
| 31 | * The views and conclusions contained in the software and documentation |
| 32 | * are those of the authors and should not be interpreted as representing |
| 33 | * official policies, either expressed or implied, of Alacritech, Inc. |
| 34 | * |
| 35 | **************************************************************************/ |
| 36 | |
| 37 | /* |
| 38 | * FILENAME: sxg.h |
| 39 | * |
| 40 | * This is the base set of header definitions for the SXG driver. |
| 41 | */ |
| 42 | #ifndef __SXG_DRIVER_H__ |
| 43 | #define __SXG_DRIVER_H__ |
| 44 | |
| 45 | #define p_net_device struct net_device * |
| 46 | // SXG_STATS - Probably move these to someplace where |
| 47 | // the slicstat (sxgstat?) program can get them. |
| 48 | typedef struct _SXG_STATS { |
| 49 | // Xmt |
| 50 | u32 XmtNBL; // Offload send NBL count |
| 51 | u64 DumbXmtBytes; // Dumbnic send bytes |
| 52 | u64 SlowXmtBytes; // Slowpath send bytes |
| 53 | u64 FastXmtBytes; // Fastpath send bytes |
| 54 | u64 DumbXmtPkts; // Dumbnic send packets |
| 55 | u64 SlowXmtPkts; // Slowpath send packets |
| 56 | u64 FastXmtPkts; // Fastpath send packets |
| 57 | u64 DumbXmtUcastPkts; // directed packets |
| 58 | u64 DumbXmtMcastPkts; // Multicast packets |
| 59 | u64 DumbXmtBcastPkts; // OID_GEN_BROADCAST_FRAMES_RCV |
| 60 | u64 DumbXmtUcastBytes; // OID_GEN_DIRECTED_BYTES_XMIT |
| 61 | u64 DumbXmtMcastBytes; // OID_GEN_MULTICAST_BYTES_XMIT |
| 62 | u64 DumbXmtBcastBytes; // OID_GEN_BROADCAST_BYTES_XMIT |
| 63 | u64 XmtErrors; // OID_GEN_XMIT_ERROR |
| 64 | u64 XmtDiscards; // OID_GEN_XMIT_DISCARDS |
| 65 | u64 XmtOk; // OID_GEN_XMIT_OK |
| 66 | u64 XmtQLen; // OID_GEN_TRANSMIT_QUEUE_LENGTH |
| 67 | u64 XmtZeroFull; // Transmit ring zero full |
| 68 | // Rcv |
| 69 | u32 RcvNBL; // Offload recieve NBL count |
| 70 | u64 DumbRcvBytes; // dumbnic recv bytes |
| 71 | u64 DumbRcvUcastBytes; // OID_GEN_DIRECTED_BYTES_RCV |
| 72 | u64 DumbRcvMcastBytes; // OID_GEN_MULTICAST_BYTES_RCV |
| 73 | u64 DumbRcvBcastBytes; // OID_GEN_BROADCAST_BYTES_RCV |
| 74 | u64 SlowRcvBytes; // Slowpath recv bytes |
| 75 | u64 FastRcvBytes; // Fastpath recv bytes |
| 76 | u64 DumbRcvPkts; // OID_GEN_DIRECTED_FRAMES_RCV |
| 77 | u64 DumbRcvTcpPkts; // See SxgCollectStats |
| 78 | u64 DumbRcvUcastPkts; // directed packets |
| 79 | u64 DumbRcvMcastPkts; // Multicast packets |
| 80 | u64 DumbRcvBcastPkts; // OID_GEN_BROADCAST_FRAMES_RCV |
| 81 | u64 SlowRcvPkts; // OID_GEN_DIRECTED_FRAMES_RCV |
| 82 | u64 RcvErrors; // OID_GEN_RCV_ERROR |
| 83 | u64 RcvDiscards; // OID_GEN_RCV_DISCARDS |
| 84 | u64 RcvNoBuffer; // OID_GEN_RCV_NO_BUFFER |
| 85 | u64 PdqFull; // Processed Data Queue Full |
| 86 | u64 EventRingFull; // Event ring full |
| 87 | // Verbose stats |
| 88 | u64 MaxSends; // Max sends outstanding |
| 89 | u64 NoSglBuf; // SGL buffer allocation failure |
| 90 | u64 SglFail; // NDIS SGL failure |
| 91 | u64 SglAsync; // NDIS SGL failure |
| 92 | u64 NoMem; // Memory allocation failure |
| 93 | u64 NumInts; // Interrupts |
| 94 | u64 FalseInts; // Interrupt with ISR == 0 |
| 95 | u64 XmtDrops; // No sahara DRAM buffer for xmt |
| 96 | // Sahara receive status |
| 97 | u64 TransportCsum; // SXG_RCV_STATUS_TRANSPORT_CSUM |
| 98 | u64 TransportUflow; // SXG_RCV_STATUS_TRANSPORT_UFLOW |
| 99 | u64 TransportHdrLen; // SXG_RCV_STATUS_TRANSPORT_HDRLEN |
| 100 | u64 NetworkCsum; // SXG_RCV_STATUS_NETWORK_CSUM: |
| 101 | u64 NetworkUflow; // SXG_RCV_STATUS_NETWORK_UFLOW: |
| 102 | u64 NetworkHdrLen; // SXG_RCV_STATUS_NETWORK_HDRLEN: |
| 103 | u64 Parity; // SXG_RCV_STATUS_PARITY |
| 104 | u64 LinkParity; // SXG_RCV_STATUS_LINK_PARITY: |
| 105 | u64 LinkEarly; // SXG_RCV_STATUS_LINK_EARLY: |
| 106 | u64 LinkBufOflow; // SXG_RCV_STATUS_LINK_BUFOFLOW: |
| 107 | u64 LinkCode; // SXG_RCV_STATUS_LINK_CODE: |
| 108 | u64 LinkDribble; // SXG_RCV_STATUS_LINK_DRIBBLE: |
| 109 | u64 LinkCrc; // SXG_RCV_STATUS_LINK_CRC: |
| 110 | u64 LinkOflow; // SXG_RCV_STATUS_LINK_OFLOW: |
| 111 | u64 LinkUflow; // SXG_RCV_STATUS_LINK_UFLOW: |
| 112 | } SXG_STATS, *PSXG_STATS; |
| 113 | |
| 114 | |
| 115 | /**************************************************************************** |
| 116 | * DUMB-NIC Send path definitions |
| 117 | ****************************************************************************/ |
| 118 | |
| 119 | #define SXG_COMPLETE_DUMB_SEND(_pAdapt, _skb) { \ |
| 120 | ASSERT(_skb); \ |
| 121 | dev_kfree_skb_irq(_skb); \ |
| 122 | } |
| 123 | |
| 124 | #define SXG_DROP_DUMB_SEND(_pAdapt, _skb) { \ |
| 125 | ASSERT(_skb); \ |
| 126 | dev_kfree_skb(_skb); \ |
| 127 | } |
| 128 | |
| 129 | // Locate current receive header buffer location. Use this |
| 130 | // instead of RcvDataHdr->VirtualAddress since the data |
| 131 | // may have been offset by SXG_ADVANCE_MDL_OFFSET |
| 132 | #define SXG_RECEIVE_DATA_LOCATION(_RcvDataHdr) (_RcvDataHdr)->skb->data |
| 133 | |
| 134 | /************************************************************************ |
| 135 | * Dumb-NIC receive processing |
| 136 | ************************************************************************/ |
| 137 | // Define an SXG_PACKET as an NDIS_PACKET |
| 138 | #define PSXG_PACKET struct sk_buff * |
| 139 | // Indications array size |
| 140 | #define SXG_RCV_ARRAYSIZE 64 |
| 141 | |
| 142 | #define SXG_ALLOCATE_RCV_PACKET(_pAdapt, _RcvDataBufferHdr) { \ |
| 143 | struct sk_buff * skb; \ |
| 144 | skb = alloc_skb(2048, GFP_ATOMIC); \ |
| 145 | if (skb) { \ |
| 146 | (_RcvDataBufferHdr)->skb = skb; \ |
| 147 | skb->next = NULL; \ |
| 148 | } else { \ |
| 149 | (_RcvDataBufferHdr)->skb = NULL; \ |
| 150 | } \ |
| 151 | } |
| 152 | |
| 153 | #define SXG_FREE_RCV_PACKET(_RcvDataBufferHdr) { \ |
| 154 | if((_RcvDataBufferHdr)->skb) { \ |
| 155 | dev_kfree_skb((_RcvDataBufferHdr)->skb); \ |
| 156 | } \ |
| 157 | } |
| 158 | |
| 159 | // Macro to add a NDIS_PACKET to an indication array |
| 160 | // If we fill up our array of packet pointers, then indicate this |
| 161 | // block up now and start on a new one. |
| 162 | #define SXG_ADD_RCV_PACKET(_pAdapt, _Packet, _PrevPacket, _IndicationList, _NumPackets) { \ |
| 163 | (_IndicationList)[_NumPackets] = (_Packet); \ |
| 164 | (_NumPackets)++; \ |
| 165 | if((_NumPackets) == SXG_RCV_ARRAYSIZE) { \ |
| 166 | SXG_TRACE(TRACE_SXG, SxgTraceBuffer, TRACE_NOISY, "IndicRcv", \ |
| 167 | (_NumPackets), 0, 0, 0); \ |
| 168 | netif_rx((_IndicationList),(_NumPackets)); \ |
| 169 | (_NumPackets) = 0; \ |
| 170 | } \ |
| 171 | } |
| 172 | |
| 173 | #define SXG_INDICATE_PACKETS(_pAdapt, _IndicationList, _NumPackets) { \ |
| 174 | if(_NumPackets) { \ |
| 175 | SXG_TRACE(TRACE_SXG, SxgTraceBuffer, TRACE_NOISY, "IndicRcv", \ |
| 176 | (_NumPackets), 0, 0, 0); \ |
| 177 | netif_rx((_IndicationList),(_NumPackets)); \ |
| 178 | (_NumPackets) = 0; \ |
| 179 | } \ |
| 180 | } |
| 181 | |
| 182 | #define SXG_REINIATIALIZE_PACKET(_Packet) \ |
| 183 | {} /*_NdisReinitializePacket(_Packet)*/ /* this is not necessary with an skb */ |
| 184 | |
| 185 | // Definitions to initialize Dumb-nic Receive NBLs |
| 186 | #define SXG_RCV_PACKET_BUFFER_HDR(_Packet) (((PSXG_RCV_NBL_RESERVED)((_Packet)->MiniportReservedEx))->RcvDataBufferHdr) |
| 187 | |
| 188 | #define SXG_RCV_SET_CHECKSUM_INFO(_Packet, _Cpi) \ |
| 189 | NDIS_PER_PACKET_INFO_FROM_PACKET((_Packet), TcpIpChecksumPacketInfo) = (PVOID)(_Cpi) |
| 190 | |
| 191 | #define SXG_RCV_SET_TOEPLITZ(_Packet, _Toeplitz, _Type, _Function) { \ |
| 192 | NDIS_PACKET_SET_HASH_VALUE((_Packet), (_Toeplitz)); \ |
| 193 | NDIS_PACKET_SET_HASH_TYPE((_Packet), (_Type)); \ |
| 194 | NDIS_PACKET_SET_HASH_FUNCTION((_Packet), (_Function)); \ |
| 195 | } |
| 196 | |
| 197 | #define SXG_RCV_SET_VLAN_INFO(_Packet, _VlanId, _Priority) { \ |
| 198 | NDIS_PACKET_8021Q_INFO _Packet8021qInfo; \ |
| 199 | _Packet8021qInfo.TagHeader.VlanId = (_VlanId); \ |
| 200 | _Packet8021qInfo.TagHeader.UserPriority = (_Priority); \ |
| 201 | NDIS_PER_PACKET_INFO_FROM_PACKET((_Packet), Ieee8021QNetBufferListInfo) = \ |
| 202 | _Packet8021qInfo.Value; \ |
| 203 | } |
| 204 | |
| 205 | #define SXG_ADJUST_RCV_PACKET(_Packet, _RcvDataBufferHdr, _Event) { \ |
| 206 | SXG_TRACE(TRACE_SXG, SxgTraceBuffer, TRACE_NOISY, "DumbRcv", \ |
| 207 | (_RcvDataBufferHdr), (_Packet), \ |
| 208 | (_Event)->Status, 0); \ |
| 209 | ASSERT((_Event)->Length <= (_RcvDataBufferHdr)->Size); \ |
| 210 | Packet->len = (_Event)->Length; \ |
| 211 | } |
| 212 | |
| 213 | /////////////////////////////////////////////////////////////////////////////// |
| 214 | // Macros to free a receive data buffer and receive data descriptor block |
| 215 | /////////////////////////////////////////////////////////////////////////////// |
| 216 | // NOTE - Lock must be held with RCV macros |
| 217 | #define SXG_GET_RCV_DATA_BUFFER(_pAdapt, _Hdr) { \ |
| 218 | PLIST_ENTRY _ple; \ |
| 219 | _Hdr = NULL; \ |
| 220 | if((_pAdapt)->FreeRcvBufferCount) { \ |
| 221 | ASSERT(!(IsListEmpty(&(_pAdapt)->FreeRcvBuffers))); \ |
| 222 | _ple = RemoveHeadList(&(_pAdapt)->FreeRcvBuffers); \ |
| 223 | (_Hdr) = container_of(_ple, SXG_RCV_DATA_BUFFER_HDR, FreeList); \ |
| 224 | (_pAdapt)->FreeRcvBufferCount--; \ |
| 225 | ASSERT((_Hdr)->State == SXG_BUFFER_FREE); \ |
| 226 | } \ |
| 227 | } |
| 228 | |
| 229 | #define SXG_FREE_RCV_DATA_BUFFER(_pAdapt, _Hdr) { \ |
| 230 | SXG_TRACE(TRACE_SXG, SxgTraceBuffer, TRACE_NOISY, "RtnDHdr", \ |
| 231 | (_Hdr), (_pAdapt)->FreeRcvBufferCount, \ |
| 232 | (_Hdr)->State, (_Hdr)->VirtualAddress); \ |
| 233 | /* SXG_RESTORE_MDL_OFFSET(_Hdr); */ \ |
| 234 | (_pAdapt)->FreeRcvBufferCount++; \ |
| 235 | ASSERT(((_pAdapt)->AllRcvBlockCount * SXG_RCV_DESCRIPTORS_PER_BLOCK) >= (_pAdapt)->FreeRcvBufferCount); \ |
| 236 | ASSERT((_Hdr)->State != SXG_BUFFER_FREE); \ |
| 237 | (_Hdr)->State = SXG_BUFFER_FREE; \ |
| 238 | InsertTailList(&(_pAdapt)->FreeRcvBuffers, &((_Hdr)->FreeList)); \ |
| 239 | } |
| 240 | |
| 241 | #define SXG_FREE_RCV_DESCRIPTOR_BLOCK(_pAdapt, _Hdr) { \ |
| 242 | ASSERT((_Hdr)->State != SXG_BUFFER_FREE); \ |
| 243 | (_Hdr)->State = SXG_BUFFER_FREE; \ |
| 244 | (_pAdapt)->FreeRcvBlockCount++; \ |
| 245 | ASSERT((_pAdapt)->AllRcvBlockCount >= (_pAdapt)->FreeRcvBlockCount); \ |
| 246 | InsertTailList(&(_pAdapt)->FreeRcvBlocks, &(_Hdr)->FreeList); \ |
| 247 | } |
| 248 | |
| 249 | // SGL macros |
| 250 | #define SXG_FREE_SGL_BUFFER(_pAdapt, _Sgl, _NB) { \ |
| 251 | spin_lock(&(_pAdapt)->SglQLock); \ |
| 252 | (_pAdapt)->FreeSglBufferCount++; \ |
| 253 | ASSERT((_pAdapt)->AllSglBufferCount >= (_pAdapt)->FreeSglBufferCount);\ |
| 254 | ASSERT(!((_Sgl)->State & SXG_BUFFER_FREE)); \ |
| 255 | (_Sgl)->State = SXG_BUFFER_FREE; \ |
| 256 | InsertTailList(&(_pAdapt)->FreeSglBuffers, &(_Sgl)->FreeList); \ |
| 257 | spin_unlock(&(_pAdapt)->SglQLock); \ |
| 258 | } |
| 259 | |
| 260 | // Get an SGL buffer from the free queue. The first part of this macro |
| 261 | // attempts to keep ahead of buffer depletion by allocating more when |
| 262 | // we hit a minimum threshold. Note that we don't grab the lock |
| 263 | // until after that. We're dealing with round numbers here, so we don't need to, |
| 264 | // and not grabbing it avoids a possible double-trip. |
| 265 | #define SXG_GET_SGL_BUFFER(_pAdapt, _Sgl) { \ |
| 266 | PLIST_ENTRY _ple; \ |
| 267 | if ((_pAdapt->FreeSglBufferCount < SXG_MIN_SGL_BUFFERS) && \ |
| 268 | (_pAdapt->AllSglBufferCount < SXG_MAX_SGL_BUFFERS) && \ |
| 269 | (_pAdapt->AllocationsPending == 0)) { \ |
| 270 | sxg_allocate_buffer_memory(_pAdapt, \ |
| 271 | (sizeof(SXG_SCATTER_GATHER) + SXG_SGL_BUF_SIZE),\ |
| 272 | SXG_BUFFER_TYPE_SGL); \ |
| 273 | } \ |
| 274 | _Sgl = NULL; \ |
| 275 | spin_lock(&(_pAdapt)->SglQLock); \ |
| 276 | if((_pAdapt)->FreeSglBufferCount) { \ |
| 277 | ASSERT(!(IsListEmpty(&(_pAdapt)->FreeSglBuffers))); \ |
| 278 | _ple = RemoveHeadList(&(_pAdapt)->FreeSglBuffers); \ |
| 279 | (_Sgl) = container_of(_ple, SXG_SCATTER_GATHER, FreeList); \ |
| 280 | (_pAdapt)->FreeSglBufferCount--; \ |
| 281 | ASSERT((_Sgl)->State == SXG_BUFFER_FREE); \ |
| 282 | (_Sgl)->State = SXG_BUFFER_BUSY; \ |
| 283 | (_Sgl)->pSgl = NULL; \ |
| 284 | } \ |
| 285 | spin_unlock(&(_pAdapt)->SglQLock); \ |
| 286 | } |
| 287 | |
| 288 | // |
| 289 | // SXG_MULTICAST_ADDRESS |
| 290 | // |
| 291 | // Linked list of multicast addresses. |
| 292 | typedef struct _SXG_MULTICAST_ADDRESS { |
| 293 | unsigned char Address[6]; |
| 294 | struct _SXG_MULTICAST_ADDRESS *Next; |
| 295 | } SXG_MULTICAST_ADDRESS, *PSXG_MULTICAST_ADDRESS; |
| 296 | |
| 297 | // Structure to maintain chimney send and receive buffer queues. |
| 298 | // This structure maintains NET_BUFFER_LIST queues that are |
| 299 | // given to us via the Chimney MiniportTcpOffloadSend and |
| 300 | // MiniportTcpOffloadReceive routines. This structure DOES NOT |
| 301 | // manage our data buffer queue |
| 302 | typedef struct _SXG_BUFFER_QUEUE { |
| 303 | u32 Type; // Slow or fast - See below |
| 304 | u32 Direction; // Xmt or Rcv |
| 305 | u32 Bytes; // Byte count |
| 306 | u32 * Head; // Send queue head |
| 307 | u32 * Tail; // Send queue tail |
| 308 | // PNET_BUFFER_LIST NextNBL; // Short cut - next NBL |
| 309 | // PNET_BUFFER NextNB; // Short cut - next NB |
| 310 | } SXG_BUFFER_QUEUE, *PSXG_BUFFER_QUEUE; |
| 311 | |
| 312 | #define SXG_SLOW_SEND_BUFFER 0 |
| 313 | #define SXG_FAST_SEND_BUFFER 1 |
| 314 | #define SXG_RECEIVE_BUFFER 2 |
| 315 | |
| 316 | #define SXG_INIT_BUFFER(_Buffer, _Type) { \ |
| 317 | (_Buffer)->Type = (_Type); \ |
| 318 | if((_Type) == SXG_RECEIVE_BUFFER) { \ |
| 319 | (_Buffer)->Direction = 0; \ |
| 320 | } else { \ |
| 321 | (_Buffer)->Direction = NDIS_SG_LIST_WRITE_TO_DEVICE; \ |
| 322 | } \ |
| 323 | (_Buffer)->Bytes = 0; \ |
| 324 | (_Buffer)->Head = NULL; \ |
| 325 | (_Buffer)->Tail = NULL; \ |
| 326 | } |
| 327 | |
| 328 | |
| 329 | #define SXG_RSS_CPU_COUNT(_pAdapt) \ |
| 330 | ((_pAdapt)->RssEnabled ? NR_CPUS : 1) |
| 331 | |
| 332 | /**************************************************************************** |
| 333 | * DRIVER and ADAPTER structures |
| 334 | ****************************************************************************/ |
| 335 | |
| 336 | // Adapter states - These states closely match the adapter states |
| 337 | // documented in the DDK (with a few exceptions). |
| 338 | typedef enum _SXG_STATE { |
| 339 | SXG_STATE_INITIALIZING, // Initializing |
| 340 | SXG_STATE_BOOTDIAG, // Boot-Diagnostic mode |
| 341 | SXG_STATE_PAUSING, // Pausing |
| 342 | SXG_STATE_PAUSED, // Paused |
| 343 | SXG_STATE_RUNNING, // Running |
| 344 | SXG_STATE_RESETTING, // Reset in progress |
| 345 | SXG_STATE_SLEEP, // Sleeping |
| 346 | SXG_STATE_DIAG, // Diagnostic mode |
| 347 | SXG_STATE_HALTING, // Halting |
| 348 | SXG_STATE_HALTED, // Down or not-initialized |
| 349 | SXG_STATE_SHUTDOWN // shutdown |
| 350 | } SXG_STATE, *PSXG_STATE; |
| 351 | |
| 352 | // Link state |
| 353 | typedef enum _SXG_LINK_STATE { |
| 354 | SXG_LINK_DOWN, |
| 355 | SXG_LINK_UP |
| 356 | } SXG_LINK_STATE, *PSXG_LINK_STATE; |
| 357 | |
| 358 | // Link initialization timeout in 100us units |
| 359 | #define SXG_LINK_TIMEOUT 100000 // 10 Seconds - REDUCE! |
| 360 | |
| 361 | |
| 362 | // Microcode file selection codes |
| 363 | typedef enum _SXG_UCODE_SEL { |
| 364 | SXG_UCODE_SAHARA, // Sahara ucode |
| 365 | SXG_UCODE_SDIAGCPU, // Sahara CPU diagnostic ucode |
| 366 | SXG_UCODE_SDIAGSYS // Sahara system diagnostic ucode |
| 367 | } SXG_UCODE_SEL; |
| 368 | |
| 369 | |
| 370 | #define SXG_DISABLE_ALL_INTERRUPTS(_padapt) sxg_disable_interrupt(_padapt) |
| 371 | #define SXG_ENABLE_ALL_INTERRUPTS(_padapt) sxg_enable_interrupt(_padapt) |
| 372 | |
| 373 | // This probably lives in a proto.h file. Move later |
| 374 | #define SXG_MULTICAST_PACKET(_pether) ((_pether)->ether_dhost[0] & 0x01) |
| 375 | #define SXG_BROADCAST_PACKET(_pether) ((*(u32 *)(_pether)->ether_dhost == 0xFFFFFFFF) && \ |
| 376 | (*(u16 *)&(_pether)->ether_dhost[4] == 0xFFFF)) |
| 377 | |
| 378 | // For DbgPrints |
| 379 | #define SXG_ID DPFLTR_IHVNETWORK_ID |
| 380 | #define SXG_ERROR DPFLTR_ERROR_LEVEL |
| 381 | |
| 382 | // |
| 383 | // SXG_DRIVER structure - |
| 384 | // |
| 385 | // contains information about the sxg driver. There is only |
| 386 | // one of these, and it is defined as a global. |
| 387 | typedef struct _SXG_DRIVER { |
| 388 | struct _adapter_t *Adapters; // Linked list of adapters |
| 389 | ushort AdapterID; // Maintain unique adapter ID |
| 390 | } SXG_DRIVER, *PSXG_DRIVER; |
| 391 | |
| 392 | #ifdef STATUS_SUCCESS |
| 393 | #undef STATUS_SUCCESS |
| 394 | #endif |
| 395 | |
| 396 | #define STATUS_SUCCESS 0 |
| 397 | #define STATUS_PENDING 0 |
| 398 | #define STATUS_FAILURE -1 |
| 399 | #define STATUS_ERROR -2 |
| 400 | #define STATUS_NOT_SUPPORTED -3 |
| 401 | #define STATUS_BUFFER_TOO_SHORT -4 |
| 402 | #define STATUS_RESOURCES -5 |
| 403 | |
| 404 | #define SLIC_MAX_CARDS 32 |
| 405 | #define SLIC_MAX_PORTS 4 /* Max # of ports per card */ |
| 406 | #if SLIC_DUMP_ENABLED |
| 407 | // Dump buffer size |
| 408 | // |
| 409 | // This cannot be bigger than the max DMA size the card supports, |
| 410 | // given the current code structure in the host and ucode. |
| 411 | // Mojave supports 16K, Oasis supports 16K-1, so |
| 412 | // just set this at 15K, shouldnt make that much of a diff. |
| 413 | #define DUMP_BUF_SIZE 0x3C00 |
| 414 | #endif |
| 415 | |
| 416 | #define MIN(a, b) ((u32)(a) < (u32)(b) ? (a) : (b)) |
| 417 | #define MAX(a, b) ((u32)(a) > (u32)(b) ? (a) : (b)) |
| 418 | |
| 419 | typedef struct _mcast_address_t |
| 420 | { |
| 421 | unsigned char address[6]; |
| 422 | struct _mcast_address_t *next; |
| 423 | } mcast_address_t, *p_mcast_address_t; |
| 424 | |
| 425 | #define CARD_DOWN 0x00000000 |
| 426 | #define CARD_UP 0x00000001 |
| 427 | #define CARD_FAIL 0x00000002 |
| 428 | #define CARD_DIAG 0x00000003 |
| 429 | #define CARD_SLEEP 0x00000004 |
| 430 | |
| 431 | #define ADAPT_DOWN 0x00 |
| 432 | #define ADAPT_UP 0x01 |
| 433 | #define ADAPT_FAIL 0x02 |
| 434 | #define ADAPT_RESET 0x03 |
| 435 | #define ADAPT_SLEEP 0x04 |
| 436 | |
| 437 | #define ADAPT_FLAGS_BOOTTIME 0x0001 |
| 438 | #define ADAPT_FLAGS_IS64BIT 0x0002 |
| 439 | #define ADAPT_FLAGS_PENDINGLINKDOWN 0x0004 |
| 440 | #define ADAPT_FLAGS_FIBERMEDIA 0x0008 |
| 441 | #define ADAPT_FLAGS_LOCKS_ALLOCED 0x0010 |
| 442 | #define ADAPT_FLAGS_INT_REGISTERED 0x0020 |
| 443 | #define ADAPT_FLAGS_LOAD_TIMER_SET 0x0040 |
| 444 | #define ADAPT_FLAGS_STATS_TIMER_SET 0x0080 |
| 445 | #define ADAPT_FLAGS_RESET_TIMER_SET 0x0100 |
| 446 | |
| 447 | #define LINK_DOWN 0x00 |
| 448 | #define LINK_CONFIG 0x01 |
| 449 | #define LINK_UP 0x02 |
| 450 | |
| 451 | #define LINK_10MB 0x00 |
| 452 | #define LINK_100MB 0x01 |
| 453 | #define LINK_AUTOSPEED 0x02 |
| 454 | #define LINK_1000MB 0x03 |
| 455 | #define LINK_10000MB 0x04 |
| 456 | |
| 457 | #define LINK_HALFD 0x00 |
| 458 | #define LINK_FULLD 0x01 |
| 459 | #define LINK_AUTOD 0x02 |
| 460 | |
| 461 | #define MAC_DIRECTED 0x00000001 |
| 462 | #define MAC_BCAST 0x00000002 |
| 463 | #define MAC_MCAST 0x00000004 |
| 464 | #define MAC_PROMISC 0x00000008 |
| 465 | #define MAC_LOOPBACK 0x00000010 |
| 466 | #define MAC_ALLMCAST 0x00000020 |
| 467 | |
| 468 | #define SLIC_DUPLEX(x) ((x==LINK_FULLD) ? "FDX" : "HDX") |
| 469 | #define SLIC_SPEED(x) ((x==LINK_100MB) ? "100Mb" : ((x==LINK_1000MB) ? "1000Mb" : " 10Mb")) |
| 470 | #define SLIC_LINKSTATE(x) ((x==LINK_DOWN) ? "Down" : "Up ") |
| 471 | #define SLIC_ADAPTER_STATE(x) ((x==ADAPT_UP) ? "UP" : "Down") |
| 472 | #define SLIC_CARD_STATE(x) ((x==CARD_UP) ? "UP" : "Down") |
| 473 | |
| 474 | |
| 475 | typedef struct _ether_header |
| 476 | { |
| 477 | unsigned char ether_dhost[6]; |
| 478 | unsigned char ether_shost[6]; |
| 479 | ushort ether_type; |
| 480 | } ether_header, *p_ether_header; |
| 481 | |
| 482 | |
| 483 | #define NUM_CFG_SPACES 2 |
| 484 | #define NUM_CFG_REGS 64 |
| 485 | |
| 486 | typedef struct _physcard_t |
| 487 | { |
| 488 | struct _adapter_t *adapter[SLIC_MAX_PORTS]; |
| 489 | struct _physcard_t *next; |
| 490 | unsigned int adapters_allocd; |
| 491 | } physcard_t, *p_physcard_t; |
| 492 | |
| 493 | typedef struct _sxgbase_driver |
| 494 | { |
| 495 | spinlock_t driver_lock; |
| 496 | unsigned long flags; /* irqsave for spinlock */ |
| 497 | u32 num_sxg_cards; |
| 498 | u32 num_sxg_ports; |
| 499 | u32 num_sxg_ports_active; |
| 500 | u32 dynamic_intagg; |
| 501 | p_physcard_t phys_card; |
| 502 | } sxgbase_driver_t; |
| 503 | |
| 504 | |
| 505 | typedef struct _adapter_t |
| 506 | { |
| 507 | void * ifp; |
| 508 | unsigned int port; |
| 509 | p_physcard_t physcard; |
| 510 | unsigned int physport; |
| 511 | unsigned int cardindex; |
| 512 | unsigned int card_size; |
| 513 | unsigned int chipid; |
| 514 | unsigned int busnumber; |
| 515 | unsigned int slotnumber; |
| 516 | unsigned int functionnumber; |
| 517 | ushort vendid; |
| 518 | ushort devid; |
| 519 | ushort subsysid; |
| 520 | u32 irq; |
| 521 | |
| 522 | void * sxg_adapter; |
| 523 | u32 nBusySend; |
| 524 | |
| 525 | void __iomem * base_addr; |
| 526 | u32 memorylength; |
| 527 | u32 drambase; |
| 528 | u32 dramlength; |
| 529 | unsigned int queues_initialized; |
| 530 | unsigned int allocated; |
| 531 | unsigned int activated; |
| 532 | u32 intrregistered; |
| 533 | unsigned int isp_initialized; |
| 534 | unsigned int gennumber; |
| 535 | u32 curaddrupper; |
| 536 | u32 isrcopy; |
| 537 | unsigned char state; |
| 538 | unsigned char linkstate; |
| 539 | unsigned char linkspeed; |
| 540 | unsigned char linkduplex; |
| 541 | unsigned int flags; |
| 542 | unsigned char macaddr[6]; |
| 543 | unsigned char currmacaddr[6]; |
| 544 | u32 macopts; |
| 545 | ushort devflags_prev; |
| 546 | u64 mcastmask; |
| 547 | p_mcast_address_t mcastaddrs; |
| 548 | struct timer_list pingtimer; |
| 549 | u32 pingtimerset; |
| 550 | struct timer_list statstimer; |
| 551 | u32 statstimerset; |
| 552 | struct timer_list vpci_timer; |
| 553 | u32 vpci_timerset; |
| 554 | struct timer_list loadtimer; |
| 555 | u32 loadtimerset; |
| 556 | |
| 557 | u32 xmitq_full; |
| 558 | u32 all_reg_writes; |
| 559 | u32 icr_reg_writes; |
| 560 | u32 isr_reg_writes; |
| 561 | u32 error_interrupts; |
| 562 | u32 error_rmiss_interrupts; |
| 563 | u32 rx_errors; |
| 564 | u32 rcv_drops; |
| 565 | u32 rcv_interrupts; |
| 566 | u32 xmit_interrupts; |
| 567 | u32 linkevent_interrupts; |
| 568 | u32 upr_interrupts; |
| 569 | u32 num_isrs; |
| 570 | u32 false_interrupts; |
| 571 | u32 tx_packets; |
| 572 | u32 xmit_completes; |
| 573 | u32 tx_drops; |
| 574 | u32 rcv_broadcasts; |
| 575 | u32 rcv_multicasts; |
| 576 | u32 rcv_unicasts; |
| 577 | u32 max_isr_rcvs; |
| 578 | u32 max_isr_xmits; |
| 579 | u32 rcv_interrupt_yields; |
| 580 | u32 intagg_period; |
| 581 | struct net_device_stats stats; |
| 582 | u32 * MiniportHandle; // Our miniport handle |
| 583 | SXG_STATE State; // Adapter state |
| 584 | SXG_LINK_STATE LinkState; // Link state |
| 585 | u64 LinkSpeed; // Link Speed |
| 586 | u32 PowerState; // NDIS power state |
| 587 | struct _adapter_t *Next; // Linked list |
| 588 | ushort AdapterID; // 1..n |
| 589 | unsigned char MacAddr[6]; // Our permanent HW mac address |
| 590 | unsigned char CurrMacAddr[6]; // Our Current mac address |
| 591 | p_net_device netdev; |
| 592 | p_net_device next_netdevice; |
| 593 | struct pci_dev * pcidev; |
| 594 | |
| 595 | PSXG_MULTICAST_ADDRESS MulticastAddrs; // Multicast list |
| 596 | u64 MulticastMask; // Multicast mask |
| 597 | u32 * InterruptHandle; // Register Interrupt handle |
| 598 | u32 InterruptLevel; // From Resource list |
| 599 | u32 InterruptVector; // From Resource list |
| 600 | spinlock_t AdapterLock; /* Serialize access adapter routines */ |
| 601 | spinlock_t Bit64RegLock; /* For writing 64-bit addresses */ |
| 602 | PSXG_HW_REGS HwRegs; // Sahara HW Register Memory (BAR0/1) |
| 603 | PSXG_UCODE_REGS UcodeRegs; // Microcode Register Memory (BAR2/3) |
| 604 | PSXG_TCB_REGS TcbRegs; // Same as Ucode regs - See sxghw.h |
| 605 | ushort ResetDpcCount; // For timeout |
| 606 | ushort RssDpcCount; // For timeout |
| 607 | ushort VendorID; // Vendor ID |
| 608 | ushort DeviceID; // Device ID |
| 609 | ushort SubSystemID; // Sub-System ID |
| 610 | ushort FrameSize; // Maximum frame size |
| 611 | u32 * DmaHandle; // NDIS DMA handle |
| 612 | u32 * PacketPoolHandle; // Used with NDIS 5.2 only. Don't ifdef out |
| 613 | u32 * BufferPoolHandle; // Used with NDIS 5.2 only. Don't ifdef out |
| 614 | u32 MacFilter; // NDIS MAC Filter |
| 615 | ushort IpId; // For slowpath |
| 616 | PSXG_EVENT_RING EventRings; // Host event rings. 1/CPU to 16 max |
| 617 | dma_addr_t PEventRings; // Physical address |
| 618 | u32 NextEvent[SXG_MAX_RSS]; // Current location in ring |
| 619 | dma_addr_t PTcbBuffers; // TCB Buffers - physical address |
| 620 | dma_addr_t PTcbCompBuffers; // TCB Composite Buffers - phys addr |
| 621 | PSXG_XMT_RING XmtRings; // Transmit rings |
| 622 | dma_addr_t PXmtRings; // Transmit rings - physical address |
| 623 | SXG_RING_INFO XmtRingZeroInfo; // Transmit ring 0 info |
| 624 | spinlock_t XmtZeroLock; /* Transmit ring 0 lock */ |
| 625 | u32 * XmtRingZeroIndex; // Shared XMT ring 0 index |
| 626 | dma_addr_t PXmtRingZeroIndex; // Shared XMT ring 0 index - physical |
| 627 | LIST_ENTRY FreeProtocolHeaders;// Free protocol headers |
| 628 | u32 FreeProtoHdrCount; // Count |
| 629 | void * ProtocolHeaders; // Block of protocol header |
| 630 | dma_addr_t PProtocolHeaders; // Block of protocol headers - phys |
| 631 | |
| 632 | PSXG_RCV_RING RcvRings; // Receive rings |
| 633 | dma_addr_t PRcvRings; // Receive rings - physical address |
| 634 | SXG_RING_INFO RcvRingZeroInfo; // Receive ring 0 info |
| 635 | |
| 636 | u32 * Isr; // Interrupt status register |
| 637 | dma_addr_t PIsr; // ISR - physical address |
| 638 | u32 IsrCopy[SXG_MAX_RSS]; // Copy of ISR |
| 639 | ushort InterruptsEnabled; // Bitmask of enabled vectors |
| 640 | unsigned char * IndirectionTable; // RSS indirection table |
| 641 | dma_addr_t PIndirectionTable; // Physical address |
| 642 | ushort RssTableSize; // From NDIS_RECEIVE_SCALE_PARAMETERS |
| 643 | ushort HashKeySize; // From NDIS_RECEIVE_SCALE_PARAMETERS |
| 644 | unsigned char HashSecretKey[40]; // rss key |
| 645 | u32 HashInformation; |
| 646 | // Receive buffer queues |
| 647 | spinlock_t RcvQLock; /* Receive Queue Lock */ |
| 648 | LIST_ENTRY FreeRcvBuffers; // Free SXG_DATA_BUFFER queue |
| 649 | LIST_ENTRY FreeRcvBlocks; // Free SXG_RCV_DESCRIPTOR_BLOCK Q |
| 650 | LIST_ENTRY AllRcvBlocks; // All SXG_RCV_BLOCKs |
| 651 | ushort FreeRcvBufferCount; // Number of free rcv data buffers |
| 652 | ushort FreeRcvBlockCount; // # of free rcv descriptor blocks |
| 653 | ushort AllRcvBlockCount; // Number of total receive blocks |
| 654 | ushort ReceiveBufferSize; // SXG_RCV_DATA/JUMBO_BUFFER_SIZE only |
| 655 | u32 AllocationsPending; // Receive allocation pending |
| 656 | u32 RcvBuffersOnCard; // SXG_DATA_BUFFERS owned by card |
| 657 | // SGL buffers |
| 658 | spinlock_t SglQLock; /* SGL Queue Lock */ |
| 659 | LIST_ENTRY FreeSglBuffers; // Free SXG_SCATTER_GATHER |
| 660 | LIST_ENTRY AllSglBuffers; // All SXG_SCATTER_GATHER |
| 661 | ushort FreeSglBufferCount; // Number of free SGL buffers |
| 662 | ushort AllSglBufferCount; // Number of total SGL buffers |
| 663 | u32 CurrentTime; // Tick count |
| 664 | u32 FastpathConnections;// # of fastpath connections |
| 665 | // Various single-bit flags: |
| 666 | u32 BasicAllocations:1; // Locks and listheads |
| 667 | u32 IntRegistered:1; // Interrupt registered |
| 668 | u32 PingOutstanding:1; // Ping outstanding to card |
| 669 | u32 Dead:1; // Card dead |
| 670 | u32 DumpDriver:1; // OID_SLIC_DRIVER_DUMP request |
| 671 | u32 DumpCard:1; // OID_SLIC_CARD_DUMP request |
| 672 | u32 DumpCmdRunning:1; // Dump command in progress |
| 673 | u32 DebugRunning:1; // AGDB debug in progress |
| 674 | u32 JumboEnabled:1; // Jumbo frames enabled |
| 675 | u32 MsiEnabled:1; // MSI interrupt enabled |
| 676 | u32 RssEnabled:1; // RSS Enabled |
| 677 | u32 FailOnBadEeprom:1; // Fail on Bad Eeprom |
| 678 | u32 DiagStart:1; // Init adapter for diagnostic start |
| 679 | // Stats |
| 680 | u32 PendingRcvCount; // Outstanding rcv indications |
| 681 | u32 PendingXmtCount; // Outstanding send requests |
| 682 | SXG_STATS Stats; // Statistics |
| 683 | u32 ReassBufs; // Number of reassembly buffers |
| 684 | // Card Crash Info |
| 685 | ushort CrashLocation; // Microcode crash location |
| 686 | unsigned char CrashCpu; // Sahara CPU ID |
| 687 | // Diagnostics |
| 688 | // PDIAG_CMD DiagCmds; // List of free diagnostic commands |
| 689 | // PDIAG_BUFFER DiagBuffers; // List of free diagnostic buffers |
| 690 | // PDIAG_REQ DiagReqQ; // List of outstanding (asynchronous) diag requests |
| 691 | // u32 DiagCmdTimeout; // Time out for diag cmds (seconds) XXXTODO - replace with SXG_PARAM var? |
| 692 | // unsigned char DiagDmaDesc[DMA_CPU_CTXS]; // Free DMA descriptors bit field (32 CPU ctx * 8 DMA ctx) |
| 693 | |
| 694 | ///////////////////////////////////////////////////////////////////// |
| 695 | // Put preprocessor-conditional fields at the end so we don't |
| 696 | // have to recompile sxgdbg everytime we reconfigure the driver |
| 697 | ///////////////////////////////////////////////////////////////////// |
| 698 | void * PendingSetRss; // Pending RSS parameter change |
| 699 | u32 IPv4HdrSize; // Shared 5.2/6.0 encap param |
| 700 | unsigned char * InterruptInfo; // Allocated by us during AddDevice |
| 701 | #if defined(CONFIG_X86) |
| 702 | u32 AddrUpper; // Upper 32 bits of 64-bit register |
| 703 | #endif |
| 704 | //#if SXG_FAILURE_DUMP |
| 705 | // NDIS_EVENT DumpThreadEvent; // syncronize dump thread |
| 706 | // BOOLEAN DumpThreadRunning; // termination flag |
| 707 | // PSXG_DUMP_CMD DumpBuffer; // 68k - Cmd and Buffer |
| 708 | // dma_addr_t PDumpBuffer; // Physical address |
| 709 | //#endif // SXG_FAILURE_DUMP |
| 710 | |
| 711 | } adapter_t, *p_adapter_t; |
| 712 | |
| 713 | #if SLIC_DUMP_ENABLED |
| 714 | #define SLIC_DUMP_REQUESTED 1 |
| 715 | #define SLIC_DUMP_IN_PROGRESS 2 |
| 716 | #define SLIC_DUMP_DONE 3 |
| 717 | |
| 718 | /**************************************************************************** |
| 719 | * |
| 720 | * Microcode crash information structure. This |
| 721 | * structure is written out to the card's SRAM when the microcode panic's. |
| 722 | * |
| 723 | ****************************************************************************/ |
| 724 | typedef struct _slic_crash_info { |
| 725 | ushort cpu_id; |
| 726 | ushort crash_pc; |
| 727 | } slic_crash_info, *p_slic_crash_info; |
| 728 | |
| 729 | #define CRASH_INFO_OFFSET 0x155C |
| 730 | |
| 731 | #endif |
| 732 | |
| 733 | #define UPDATE_STATS(largestat, newstat, oldstat) \ |
| 734 | { \ |
| 735 | if ((newstat) < (oldstat)) \ |
| 736 | (largestat) += ((newstat) + (0xFFFFFFFF - oldstat + 1)); \ |
| 737 | else \ |
| 738 | (largestat) += ((newstat) - (oldstat)); \ |
| 739 | } |
| 740 | |
| 741 | #define UPDATE_STATS_GB(largestat, newstat, oldstat) \ |
| 742 | { \ |
| 743 | (largestat) += ((newstat) - (oldstat)); \ |
| 744 | } |
| 745 | |
| 746 | #define ETHER_EQ_ADDR(_AddrA, _AddrB, _Result) \ |
| 747 | { \ |
| 748 | _Result = TRUE; \ |
| 749 | if (*(u32 *)(_AddrA) != *(u32 *)(_AddrB)) \ |
| 750 | _Result = FALSE; \ |
| 751 | if (*(u16 *)(&((_AddrA)[4])) != *(u16 *)(&((_AddrB)[4]))) \ |
| 752 | _Result = FALSE; \ |
| 753 | } |
| 754 | |
| 755 | #define ETHERMAXFRAME 1514 |
| 756 | #define JUMBOMAXFRAME 9014 |
| 757 | |
| 758 | #if defined(CONFIG_X86_64) || defined(CONFIG_IA64) |
| 759 | #define SXG_GET_ADDR_LOW(_addr) (u32)((u64)(_addr) & 0x00000000FFFFFFFF) |
| 760 | #define SXG_GET_ADDR_HIGH(_addr) (u32)(((u64)(_addr) >> 32) & 0x00000000FFFFFFFF) |
| 761 | #else |
| 762 | #define SXG_GET_ADDR_LOW(_addr) (u32)_addr |
| 763 | #define SXG_GET_ADDR_HIGH(_addr) (u32)0 |
| 764 | #endif |
| 765 | |
| 766 | #define FLUSH TRUE |
| 767 | #define DONT_FLUSH FALSE |
| 768 | |
| 769 | #define SIOCSLICDUMPCARD SIOCDEVPRIVATE+9 |
| 770 | #define SIOCSLICSETINTAGG SIOCDEVPRIVATE+10 |
| 771 | #define SIOCSLICTRACEDUMP SIOCDEVPRIVATE+11 |
| 772 | |
| 773 | #endif /* __SXG_DRIVER_H__ */ |