Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1 | #ifndef __ASM_ARM_SYSTEM_H |
| 2 | #define __ASM_ARM_SYSTEM_H |
| 3 | |
| 4 | #ifdef __KERNEL__ |
| 5 | |
| 6 | #include <linux/config.h> |
| 7 | |
| 8 | /* |
| 9 | * This is used to ensure the compiler did actually allocate the register we |
| 10 | * asked it for some inline assembly sequences. Apparently we can't trust |
| 11 | * the compiler from one version to another so a bit of paranoia won't hurt. |
| 12 | * This string is meant to be concatenated with the inline asm string and |
| 13 | * will cause compilation to stop on mismatch. (From ARM32 - may come in handy) |
| 14 | */ |
| 15 | #define __asmeq(x, y) ".ifnc " x "," y " ; .err ; .endif\n\t" |
| 16 | |
| 17 | #ifndef __ASSEMBLY__ |
| 18 | |
| 19 | #include <linux/linkage.h> |
| 20 | |
| 21 | struct thread_info; |
| 22 | struct task_struct; |
| 23 | |
| 24 | #if 0 |
| 25 | /* information about the system we're running on */ |
| 26 | extern unsigned int system_rev; |
| 27 | extern unsigned int system_serial_low; |
| 28 | extern unsigned int system_serial_high; |
| 29 | extern unsigned int mem_fclk_21285; |
| 30 | |
| 31 | FIXME - sort this |
| 32 | /* |
| 33 | * We need to turn the caches off before calling the reset vector - RiscOS |
| 34 | * messes up if we don't |
| 35 | */ |
| 36 | #define proc_hard_reset() cpu_proc_fin() |
| 37 | |
| 38 | #endif |
| 39 | |
| 40 | struct pt_regs; |
| 41 | |
| 42 | void die(const char *msg, struct pt_regs *regs, int err) |
| 43 | __attribute__((noreturn)); |
| 44 | |
| 45 | void die_if_kernel(const char *str, struct pt_regs *regs, int err); |
| 46 | |
| 47 | void hook_fault_code(int nr, int (*fn)(unsigned long, unsigned int, |
| 48 | struct pt_regs *), |
| 49 | int sig, const char *name); |
| 50 | |
| 51 | #include <asm/proc-fns.h> |
| 52 | |
| 53 | #define xchg(ptr,x) \ |
| 54 | ((__typeof__(*(ptr)))__xchg((unsigned long)(x),(ptr),sizeof(*(ptr)))) |
| 55 | |
| 56 | #define tas(ptr) (xchg((ptr),1)) |
| 57 | |
| 58 | extern asmlinkage void __backtrace(void); |
| 59 | |
| 60 | #define set_cr(x) \ |
| 61 | __asm__ __volatile__( \ |
| 62 | "mcr p15, 0, %0, c1, c0, 0 @ set CR" \ |
| 63 | : : "r" (x) : "cc") |
| 64 | |
| 65 | #define get_cr() \ |
| 66 | ({ \ |
| 67 | unsigned int __val; \ |
| 68 | __asm__ __volatile__( \ |
| 69 | "mrc p15, 0, %0, c1, c0, 0 @ get CR" \ |
| 70 | : "=r" (__val) : : "cc"); \ |
| 71 | __val; \ |
| 72 | }) |
| 73 | |
| 74 | extern unsigned long cr_no_alignment; /* defined in entry-armv.S */ |
| 75 | extern unsigned long cr_alignment; /* defined in entry-armv.S */ |
| 76 | |
| 77 | #define UDBG_UNDEFINED (1 << 0) |
| 78 | #define UDBG_SYSCALL (1 << 1) |
| 79 | #define UDBG_BADABORT (1 << 2) |
| 80 | #define UDBG_SEGV (1 << 3) |
| 81 | #define UDBG_BUS (1 << 4) |
| 82 | |
| 83 | extern unsigned int user_debug; |
| 84 | |
| 85 | #define vectors_base() (0) |
| 86 | |
| 87 | #define mb() __asm__ __volatile__ ("" : : : "memory") |
| 88 | #define rmb() mb() |
| 89 | #define wmb() mb() |
| 90 | #define nop() __asm__ __volatile__("mov\tr0,r0\t@ nop\n\t"); |
| 91 | |
| 92 | #define read_barrier_depends() do { } while(0) |
| 93 | #define set_mb(var, value) do { var = value; mb(); } while (0) |
| 94 | #define set_wmb(var, value) do { var = value; wmb(); } while (0) |
| 95 | |
| 96 | /* |
| 97 | * We assume knowledge of how |
| 98 | * spin_unlock_irq() and friends are implemented. This avoids |
| 99 | * us needlessly decrementing and incrementing the preempt count. |
| 100 | */ |
| 101 | #define prepare_arch_switch(rq,next) local_irq_enable() |
| 102 | #define finish_arch_switch(rq,prev) spin_unlock(&(rq)->lock) |
| 103 | #define task_running(rq,p) ((rq)->curr == (p)) |
| 104 | |
| 105 | /* |
| 106 | * switch_to(prev, next) should switch from task `prev' to `next' |
| 107 | * `prev' will never be the same as `next'. schedule() itself |
| 108 | * contains the memory barrier to tell GCC not to cache `current'. |
| 109 | */ |
| 110 | extern struct task_struct *__switch_to(struct task_struct *, struct thread_info *, struct thread_info *); |
| 111 | |
| 112 | #define switch_to(prev,next,last) \ |
| 113 | do { \ |
Al Viro | 697102c | 2006-01-12 01:05:59 -0800 | [diff] [blame] | 114 | last = __switch_to(prev,task_thread_info(prev),task_thread_info(next)); \ |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 115 | } while (0) |
| 116 | |
| 117 | /* |
Ingo Molnar | 4dc7a0b | 2006-01-12 01:05:27 -0800 | [diff] [blame] | 118 | * On SMP systems, when the scheduler does migration-cost autodetection, |
| 119 | * it needs a way to flush as much of the CPU's caches as possible. |
| 120 | * |
| 121 | * TODO: fill this in! |
| 122 | */ |
| 123 | static inline void sched_cacheflush(void) |
| 124 | { |
| 125 | } |
| 126 | |
| 127 | /* |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 128 | * Save the current interrupt enable state & disable IRQs |
| 129 | */ |
| 130 | #define local_irq_save(x) \ |
| 131 | do { \ |
| 132 | unsigned long temp; \ |
| 133 | __asm__ __volatile__( \ |
| 134 | " mov %0, pc @ save_flags_cli\n" \ |
| 135 | " orr %1, %0, #0x08000000\n" \ |
| 136 | " and %0, %0, #0x0c000000\n" \ |
| 137 | " teqp %1, #0\n" \ |
| 138 | : "=r" (x), "=r" (temp) \ |
| 139 | : \ |
| 140 | : "memory"); \ |
| 141 | } while (0) |
| 142 | |
| 143 | /* |
| 144 | * Enable IRQs (sti) |
| 145 | */ |
| 146 | #define local_irq_enable() \ |
| 147 | do { \ |
| 148 | unsigned long temp; \ |
| 149 | __asm__ __volatile__( \ |
| 150 | " mov %0, pc @ sti\n" \ |
| 151 | " bic %0, %0, #0x08000000\n" \ |
| 152 | " teqp %0, #0\n" \ |
| 153 | : "=r" (temp) \ |
| 154 | : \ |
| 155 | : "memory"); \ |
| 156 | } while(0) |
| 157 | |
| 158 | /* |
| 159 | * Disable IRQs (cli) |
| 160 | */ |
| 161 | #define local_irq_disable() \ |
| 162 | do { \ |
| 163 | unsigned long temp; \ |
| 164 | __asm__ __volatile__( \ |
| 165 | " mov %0, pc @ cli\n" \ |
| 166 | " orr %0, %0, #0x08000000\n" \ |
| 167 | " teqp %0, #0\n" \ |
| 168 | : "=r" (temp) \ |
| 169 | : \ |
| 170 | : "memory"); \ |
| 171 | } while(0) |
| 172 | |
| 173 | /* Enable FIQs (stf) */ |
| 174 | |
| 175 | #define __stf() do { \ |
| 176 | unsigned long temp; \ |
| 177 | __asm__ __volatile__( \ |
| 178 | " mov %0, pc @ stf\n" \ |
| 179 | " bic %0, %0, #0x04000000\n" \ |
| 180 | " teqp %0, #0\n" \ |
| 181 | : "=r" (temp)); \ |
| 182 | } while(0) |
| 183 | |
| 184 | /* Disable FIQs (clf) */ |
| 185 | |
| 186 | #define __clf() do { \ |
| 187 | unsigned long temp; \ |
| 188 | __asm__ __volatile__( \ |
| 189 | " mov %0, pc @ clf\n" \ |
| 190 | " orr %0, %0, #0x04000000\n" \ |
| 191 | " teqp %0, #0\n" \ |
| 192 | : "=r" (temp)); \ |
| 193 | } while(0) |
| 194 | |
| 195 | |
| 196 | /* |
| 197 | * Save the current interrupt enable state. |
| 198 | */ |
| 199 | #define local_save_flags(x) \ |
| 200 | do { \ |
| 201 | __asm__ __volatile__( \ |
| 202 | " mov %0, pc @ save_flags\n" \ |
| 203 | " and %0, %0, #0x0c000000\n" \ |
| 204 | : "=r" (x)); \ |
| 205 | } while (0) |
| 206 | |
| 207 | |
| 208 | /* |
| 209 | * restore saved IRQ & FIQ state |
| 210 | */ |
| 211 | #define local_irq_restore(x) \ |
| 212 | do { \ |
| 213 | unsigned long temp; \ |
| 214 | __asm__ __volatile__( \ |
| 215 | " mov %0, pc @ restore_flags\n" \ |
| 216 | " bic %0, %0, #0x0c000000\n" \ |
| 217 | " orr %0, %0, %1\n" \ |
| 218 | " teqp %0, #0\n" \ |
| 219 | : "=&r" (temp) \ |
| 220 | : "r" (x) \ |
| 221 | : "memory"); \ |
| 222 | } while (0) |
| 223 | |
| 224 | |
| 225 | #ifdef CONFIG_SMP |
| 226 | #error SMP not supported |
| 227 | #endif |
| 228 | |
| 229 | #define smp_mb() barrier() |
| 230 | #define smp_rmb() barrier() |
| 231 | #define smp_wmb() barrier() |
| 232 | #define smp_read_barrier_depends() do { } while(0) |
| 233 | |
| 234 | #define clf() __clf() |
| 235 | #define stf() __stf() |
| 236 | |
| 237 | #define irqs_disabled() \ |
| 238 | ({ \ |
| 239 | unsigned long flags; \ |
| 240 | local_save_flags(flags); \ |
| 241 | flags & PSR_I_BIT; \ |
| 242 | }) |
| 243 | |
| 244 | static inline unsigned long __xchg(unsigned long x, volatile void *ptr, int size) |
| 245 | { |
| 246 | extern void __bad_xchg(volatile void *, int); |
| 247 | |
| 248 | switch (size) { |
| 249 | case 1: return cpu_xchg_1(x, ptr); |
| 250 | case 4: return cpu_xchg_4(x, ptr); |
| 251 | default: __bad_xchg(ptr, size); |
| 252 | } |
| 253 | return 0; |
| 254 | } |
| 255 | |
| 256 | #endif /* __ASSEMBLY__ */ |
| 257 | |
| 258 | #define arch_align_stack(x) (x) |
| 259 | |
| 260 | #endif /* __KERNEL__ */ |
| 261 | |
| 262 | #endif |