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Kevin Hilman8bd22942009-05-28 10:56:16 -07001/*
2 * OMAP3 Power Management Routines
3 *
4 * Copyright (C) 2006-2008 Nokia Corporation
5 * Tony Lindgren <tony@atomide.com>
6 * Jouni Hogander
7 *
Rajendra Nayak2f5939c2008-09-26 17:50:07 +05308 * Copyright (C) 2007 Texas Instruments, Inc.
9 * Rajendra Nayak <rnayak@ti.com>
10 *
Kevin Hilman8bd22942009-05-28 10:56:16 -070011 * Copyright (C) 2005 Texas Instruments, Inc.
12 * Richard Woodruff <r-woodruff2@ti.com>
13 *
14 * Based on pm.c for omap1
15 *
16 * This program is free software; you can redistribute it and/or modify
17 * it under the terms of the GNU General Public License version 2 as
18 * published by the Free Software Foundation.
19 */
20
21#include <linux/pm.h>
22#include <linux/suspend.h>
23#include <linux/interrupt.h>
24#include <linux/module.h>
25#include <linux/list.h>
26#include <linux/err.h>
27#include <linux/gpio.h>
Kevin Hilmanc40552b2009-10-06 14:25:09 -070028#include <linux/clk.h>
Tero Kristodccaad82009-11-17 18:34:53 +020029#include <linux/delay.h>
Tejun Heo5a0e3ad2010-03-24 17:04:11 +090030#include <linux/slab.h>
Jean Pihet5e7c58d2011-03-03 11:25:43 +010031#include <trace/events/power.h>
Kevin Hilman8bd22942009-05-28 10:56:16 -070032
Russell King2c74a0c2011-06-22 17:41:48 +010033#include <asm/suspend.h>
David Howells9f97da72012-03-28 18:30:01 +010034#include <asm/system_misc.h>
Russell King2c74a0c2011-06-22 17:41:48 +010035
Tony Lindgrence491cf2009-10-20 09:40:47 -070036#include <plat/sram.h>
Paul Walmsley1540f2142010-12-21 21:05:15 -070037#include "clockdomain.h"
Paul Walmsley72e06d02010-12-21 21:05:16 -070038#include "powerdomain.h"
Rajendra Nayak61255ab2008-09-26 17:49:56 +053039#include <plat/sdrc.h>
Rajendra Nayak2f5939c2008-09-26 17:50:07 +053040#include <plat/prcm.h>
41#include <plat/gpmc.h>
Tero Kristof2d11852008-08-28 13:13:31 +000042#include <plat/dma.h>
Kevin Hilman8bd22942009-05-28 10:56:16 -070043
Tony Lindgren4e653312011-11-10 22:45:17 +010044#include "common.h"
Paul Walmsley59fb6592010-12-21 15:30:55 -070045#include "cm2xxx_3xxx.h"
Kevin Hilman8bd22942009-05-28 10:56:16 -070046#include "cm-regbits-34xx.h"
47#include "prm-regbits-34xx.h"
48
Paul Walmsley59fb6592010-12-21 15:30:55 -070049#include "prm2xxx_3xxx.h"
Kevin Hilman8bd22942009-05-28 10:56:16 -070050#include "pm.h"
Tero Kristo13a6fe02008-10-13 13:17:06 +030051#include "sdrc.h"
Paul Walmsley4814ced2010-10-08 11:40:20 -060052#include "control.h"
Tero Kristo13a6fe02008-10-13 13:17:06 +030053
Nishanth Menon8cdfd832010-12-20 14:05:05 -060054/* pm34xx errata defined in pm.h */
55u16 pm34xx_errata;
56
Kevin Hilman8bd22942009-05-28 10:56:16 -070057struct power_state {
58 struct powerdomain *pwrdm;
59 u32 next_state;
Kevin Hilman10f90ed2009-06-24 11:39:18 -070060#ifdef CONFIG_SUSPEND
Kevin Hilman8bd22942009-05-28 10:56:16 -070061 u32 saved_state;
Kevin Hilman10f90ed2009-06-24 11:39:18 -070062#endif
Kevin Hilman8bd22942009-05-28 10:56:16 -070063 struct list_head node;
64};
65
66static LIST_HEAD(pwrst_list);
67
Tero Kristo27d59a42008-10-13 13:15:00 +030068static int (*_omap_save_secure_sram)(u32 *addr);
Jean Pihet46e130d2011-06-29 18:40:23 +020069void (*omap3_do_wfi_sram)(void);
Tero Kristo27d59a42008-10-13 13:15:00 +030070
Rajendra Nayakfa3c2a42008-09-26 17:49:22 +053071static struct powerdomain *mpu_pwrdm, *neon_pwrdm;
72static struct powerdomain *core_pwrdm, *per_pwrdm;
Tero Kristoc16c3f62008-12-11 16:46:57 +020073static struct powerdomain *cam_pwrdm;
Rajendra Nayakfa3c2a42008-09-26 17:49:22 +053074
Kalle Jokiniemi3a7ec262009-03-26 15:59:01 +020075static void omap3_enable_io_chain(void)
76{
77 int timeout = 0;
78
Paul Walmsleyb02b9172011-10-06 17:18:45 -060079 omap2_prm_set_mod_reg_bits(OMAP3430_EN_IO_CHAIN_MASK, WKUP_MOD,
80 PM_WKEN);
81 /* Do a readback to assure write has been done */
82 omap2_prm_read_mod_reg(WKUP_MOD, PM_WKEN);
Kalle Jokiniemi3a7ec262009-03-26 15:59:01 +020083
Paul Walmsleyb02b9172011-10-06 17:18:45 -060084 while (!(omap2_prm_read_mod_reg(WKUP_MOD, PM_WKEN) &
85 OMAP3430_ST_IO_CHAIN_MASK)) {
86 timeout++;
87 if (timeout > 1000) {
88 pr_err("Wake up daisy chain activation failed.\n");
89 return;
Kalle Jokiniemi3a7ec262009-03-26 15:59:01 +020090 }
Paul Walmsleyb02b9172011-10-06 17:18:45 -060091 omap2_prm_set_mod_reg_bits(OMAP3430_ST_IO_CHAIN_MASK,
92 WKUP_MOD, PM_WKEN);
Kalle Jokiniemi3a7ec262009-03-26 15:59:01 +020093 }
94}
95
96static void omap3_disable_io_chain(void)
97{
Paul Walmsleyb02b9172011-10-06 17:18:45 -060098 omap2_prm_clear_mod_reg_bits(OMAP3430_EN_IO_CHAIN_MASK, WKUP_MOD,
99 PM_WKEN);
Kalle Jokiniemi3a7ec262009-03-26 15:59:01 +0200100}
101
Rajendra Nayak2f5939c2008-09-26 17:50:07 +0530102static void omap3_core_save_context(void)
103{
Paul Walmsley596efe42010-12-21 21:05:16 -0700104 omap3_ctrl_save_padconf();
Tero Kristodccaad82009-11-17 18:34:53 +0200105
106 /*
107 * Force write last pad into memory, as this can fail in some
Jean Pihet83521292010-12-18 16:44:46 +0100108 * cases according to errata 1.157, 1.185
Tero Kristodccaad82009-11-17 18:34:53 +0200109 */
110 omap_ctrl_writel(omap_ctrl_readl(OMAP343X_PADCONF_ETK_D14),
111 OMAP343X_CONTROL_MEM_WKUP + 0x2a0);
112
Rajendra Nayak2f5939c2008-09-26 17:50:07 +0530113 /* Save the Interrupt controller context */
114 omap_intc_save_context();
115 /* Save the GPMC context */
116 omap3_gpmc_save_context();
117 /* Save the system control module context, padconf already save above*/
118 omap3_control_save_context();
Tero Kristof2d11852008-08-28 13:13:31 +0000119 omap_dma_global_context_save();
Rajendra Nayak2f5939c2008-09-26 17:50:07 +0530120}
121
122static void omap3_core_restore_context(void)
123{
124 /* Restore the control module context, padconf restored by h/w */
125 omap3_control_restore_context();
126 /* Restore the GPMC context */
127 omap3_gpmc_restore_context();
128 /* Restore the interrupt controller context */
129 omap_intc_restore_context();
Tero Kristof2d11852008-08-28 13:13:31 +0000130 omap_dma_global_context_restore();
Rajendra Nayak2f5939c2008-09-26 17:50:07 +0530131}
132
Tero Kristo9d971402008-12-12 11:20:05 +0200133/*
134 * FIXME: This function should be called before entering off-mode after
135 * OMAP3 secure services have been accessed. Currently it is only called
136 * once during boot sequence, but this works as we are not using secure
137 * services.
138 */
Kevin Hilman617fcc92011-01-25 16:40:01 -0800139static void omap3_save_secure_ram_context(void)
Tero Kristo27d59a42008-10-13 13:15:00 +0300140{
141 u32 ret;
Kevin Hilman617fcc92011-01-25 16:40:01 -0800142 int mpu_next_state = pwrdm_read_next_pwrst(mpu_pwrdm);
Tero Kristo27d59a42008-10-13 13:15:00 +0300143
144 if (omap_type() != OMAP2_DEVICE_TYPE_GP) {
Tero Kristo27d59a42008-10-13 13:15:00 +0300145 /*
146 * MPU next state must be set to POWER_ON temporarily,
147 * otherwise the WFI executed inside the ROM code
148 * will hang the system.
149 */
150 pwrdm_set_next_pwrst(mpu_pwrdm, PWRDM_POWER_ON);
151 ret = _omap_save_secure_sram((u32 *)
152 __pa(omap3_secure_ram_storage));
Kevin Hilman617fcc92011-01-25 16:40:01 -0800153 pwrdm_set_next_pwrst(mpu_pwrdm, mpu_next_state);
Tero Kristo27d59a42008-10-13 13:15:00 +0300154 /* Following is for error tracking, it should not happen */
155 if (ret) {
Mark A. Greer98179852012-03-17 18:22:48 -0700156 pr_err("save_secure_sram() returns %08x\n", ret);
Tero Kristo27d59a42008-10-13 13:15:00 +0300157 while (1)
158 ;
159 }
160 }
161}
162
Jon Hunter77da2d92009-06-27 00:07:25 -0500163/*
164 * PRCM Interrupt Handler Helper Function
165 *
166 * The purpose of this function is to clear any wake-up events latched
167 * in the PRCM PM_WKST_x registers. It is possible that a wake-up event
168 * may occur whilst attempting to clear a PM_WKST_x register and thus
169 * set another bit in this register. A while loop is used to ensure
170 * that any peripheral wake-up events occurring while attempting to
171 * clear the PM_WKST_x are detected and cleared.
172 */
Tero Kristo22f51372011-12-16 14:36:59 -0700173static int prcm_clear_mod_irqs(s16 module, u8 regs, u32 ignore_bits)
Jon Hunter77da2d92009-06-27 00:07:25 -0500174{
Vikram Pandita71a80772009-07-17 19:33:09 -0500175 u32 wkst, fclk, iclk, clken;
Jon Hunter77da2d92009-06-27 00:07:25 -0500176 u16 wkst_off = (regs == 3) ? OMAP3430ES2_PM_WKST3 : PM_WKST1;
177 u16 fclk_off = (regs == 3) ? OMAP3430ES2_CM_FCLKEN3 : CM_FCLKEN1;
178 u16 iclk_off = (regs == 3) ? CM_ICLKEN3 : CM_ICLKEN1;
Paul Walmsley5d805972009-07-22 10:18:07 -0700179 u16 grpsel_off = (regs == 3) ?
180 OMAP3430ES2_PM_MPUGRPSEL3 : OMAP3430_PM_MPUGRPSEL;
Paul Walmsley8cb0ac92009-07-22 10:29:02 -0700181 int c = 0;
Jon Hunter77da2d92009-06-27 00:07:25 -0500182
Paul Walmsleyc4d7e582010-12-21 21:05:14 -0700183 wkst = omap2_prm_read_mod_reg(module, wkst_off);
184 wkst &= omap2_prm_read_mod_reg(module, grpsel_off);
Tero Kristo22f51372011-12-16 14:36:59 -0700185 wkst &= ~ignore_bits;
Jon Hunter77da2d92009-06-27 00:07:25 -0500186 if (wkst) {
Paul Walmsleyc4d7e582010-12-21 21:05:14 -0700187 iclk = omap2_cm_read_mod_reg(module, iclk_off);
188 fclk = omap2_cm_read_mod_reg(module, fclk_off);
Jon Hunter77da2d92009-06-27 00:07:25 -0500189 while (wkst) {
Vikram Pandita71a80772009-07-17 19:33:09 -0500190 clken = wkst;
Paul Walmsleyc4d7e582010-12-21 21:05:14 -0700191 omap2_cm_set_mod_reg_bits(clken, module, iclk_off);
Vikram Pandita71a80772009-07-17 19:33:09 -0500192 /*
193 * For USBHOST, we don't know whether HOST1 or
194 * HOST2 woke us up, so enable both f-clocks
195 */
196 if (module == OMAP3430ES2_USBHOST_MOD)
197 clken |= 1 << OMAP3430ES2_EN_USBHOST2_SHIFT;
Paul Walmsleyc4d7e582010-12-21 21:05:14 -0700198 omap2_cm_set_mod_reg_bits(clken, module, fclk_off);
199 omap2_prm_write_mod_reg(wkst, module, wkst_off);
200 wkst = omap2_prm_read_mod_reg(module, wkst_off);
Tero Kristo22f51372011-12-16 14:36:59 -0700201 wkst &= ~ignore_bits;
Paul Walmsley8cb0ac92009-07-22 10:29:02 -0700202 c++;
Jon Hunter77da2d92009-06-27 00:07:25 -0500203 }
Paul Walmsleyc4d7e582010-12-21 21:05:14 -0700204 omap2_cm_write_mod_reg(iclk, module, iclk_off);
205 omap2_cm_write_mod_reg(fclk, module, fclk_off);
Jon Hunter77da2d92009-06-27 00:07:25 -0500206 }
Paul Walmsley8cb0ac92009-07-22 10:29:02 -0700207
208 return c;
209}
210
Tero Kristo22f51372011-12-16 14:36:59 -0700211static irqreturn_t _prcm_int_handle_io(int irq, void *unused)
Paul Walmsley8cb0ac92009-07-22 10:29:02 -0700212{
213 int c;
214
Tero Kristo22f51372011-12-16 14:36:59 -0700215 c = prcm_clear_mod_irqs(WKUP_MOD, 1,
216 ~(OMAP3430_ST_IO_MASK | OMAP3430_ST_IO_CHAIN_MASK));
Paul Walmsley8cb0ac92009-07-22 10:29:02 -0700217
Tero Kristo22f51372011-12-16 14:36:59 -0700218 return c ? IRQ_HANDLED : IRQ_NONE;
Jon Hunter77da2d92009-06-27 00:07:25 -0500219}
220
Tero Kristo22f51372011-12-16 14:36:59 -0700221static irqreturn_t _prcm_int_handle_wakeup(int irq, void *unused)
Kevin Hilman8bd22942009-05-28 10:56:16 -0700222{
Tero Kristo22f51372011-12-16 14:36:59 -0700223 int c;
Kevin Hilman8bd22942009-05-28 10:56:16 -0700224
Tero Kristo22f51372011-12-16 14:36:59 -0700225 /*
226 * Clear all except ST_IO and ST_IO_CHAIN for wkup module,
227 * these are handled in a separate handler to avoid acking
228 * IO events before parsing in mux code
229 */
230 c = prcm_clear_mod_irqs(WKUP_MOD, 1,
231 OMAP3430_ST_IO_MASK | OMAP3430_ST_IO_CHAIN_MASK);
232 c += prcm_clear_mod_irqs(CORE_MOD, 1, 0);
233 c += prcm_clear_mod_irqs(OMAP3430_PER_MOD, 1, 0);
234 if (omap_rev() > OMAP3430_REV_ES1_0) {
235 c += prcm_clear_mod_irqs(CORE_MOD, 3, 0);
236 c += prcm_clear_mod_irqs(OMAP3430ES2_USBHOST_MOD, 1, 0);
237 }
Paul Walmsley8cb0ac92009-07-22 10:29:02 -0700238
Tero Kristo22f51372011-12-16 14:36:59 -0700239 return c ? IRQ_HANDLED : IRQ_NONE;
Kevin Hilman8bd22942009-05-28 10:56:16 -0700240}
241
Russell Kingcbe26342011-06-30 08:45:49 +0100242static void omap34xx_save_context(u32 *save)
243{
244 u32 val;
245
246 /* Read Auxiliary Control Register */
247 asm("mrc p15, 0, %0, c1, c0, 1" : "=r" (val));
248 *save++ = 1;
249 *save++ = val;
250
251 /* Read L2 AUX ctrl register */
252 asm("mrc p15, 1, %0, c9, c0, 2" : "=r" (val));
253 *save++ = 1;
254 *save++ = val;
255}
256
Russell King29cb3cd2011-07-02 09:54:01 +0100257static int omap34xx_do_sram_idle(unsigned long save_state)
Rajendra Nayak57f277b2008-09-26 17:49:34 +0530258{
Russell Kingcbe26342011-06-30 08:45:49 +0100259 omap34xx_cpu_suspend(save_state);
Russell King29cb3cd2011-07-02 09:54:01 +0100260 return 0;
Rajendra Nayak57f277b2008-09-26 17:49:34 +0530261}
262
Rajendra Nayak99e6a4d2008-10-08 17:30:58 +0530263void omap_sram_idle(void)
Kevin Hilman8bd22942009-05-28 10:56:16 -0700264{
265 /* Variable to tell what needs to be saved and restored
266 * in omap_sram_idle*/
267 /* save_state = 0 => Nothing to save and restored */
268 /* save_state = 1 => Only L1 and logic lost */
269 /* save_state = 2 => Only L2 lost */
270 /* save_state = 3 => L1, L2 and logic lost */
Rajendra Nayakfa3c2a42008-09-26 17:49:22 +0530271 int save_state = 0;
272 int mpu_next_state = PWRDM_POWER_ON;
273 int per_next_state = PWRDM_POWER_ON;
274 int core_next_state = PWRDM_POWER_ON;
Paul Walmsley72e06d02010-12-21 21:05:16 -0700275 int per_going_off;
Rajendra Nayak2f5939c2008-09-26 17:50:07 +0530276 int core_prev_state, per_prev_state;
Tero Kristo13a6fe02008-10-13 13:17:06 +0300277 u32 sdrc_pwr = 0;
Kevin Hilman8bd22942009-05-28 10:56:16 -0700278
Kevin Hilman8bd22942009-05-28 10:56:16 -0700279 mpu_next_state = pwrdm_read_next_pwrst(mpu_pwrdm);
280 switch (mpu_next_state) {
Rajendra Nayakfa3c2a42008-09-26 17:49:22 +0530281 case PWRDM_POWER_ON:
Kevin Hilman8bd22942009-05-28 10:56:16 -0700282 case PWRDM_POWER_RET:
283 /* No need to save context */
284 save_state = 0;
285 break;
Rajendra Nayak61255ab2008-09-26 17:49:56 +0530286 case PWRDM_POWER_OFF:
287 save_state = 3;
288 break;
Kevin Hilman8bd22942009-05-28 10:56:16 -0700289 default:
290 /* Invalid state */
Mark A. Greer98179852012-03-17 18:22:48 -0700291 pr_err("Invalid mpu state in sram_idle\n");
Kevin Hilman8bd22942009-05-28 10:56:16 -0700292 return;
293 }
Peter 'p2' De Schrijverfe617af2008-10-15 17:48:44 +0300294
Rajendra Nayakfa3c2a42008-09-26 17:49:22 +0530295 /* NEON control */
296 if (pwrdm_read_pwrst(neon_pwrdm) == PWRDM_POWER_ON)
Jouni Hogander71391782008-10-28 10:59:05 +0200297 pwrdm_set_next_pwrst(neon_pwrdm, mpu_next_state);
Rajendra Nayakfa3c2a42008-09-26 17:49:22 +0530298
Mike Chan40742fa2010-05-03 16:04:06 -0700299 /* Enable IO-PAD and IO-CHAIN wakeups */
Kevin Hilman658ce972008-11-04 20:50:52 -0800300 per_next_state = pwrdm_read_next_pwrst(per_pwrdm);
Tero Kristoecf157d2008-12-01 13:17:29 +0200301 core_next_state = pwrdm_read_next_pwrst(core_pwrdm);
Kevin Hilmand5c47d72010-08-10 16:04:35 -0700302 if (omap3_has_io_wakeup() &&
303 (per_next_state < PWRDM_POWER_ON ||
304 core_next_state < PWRDM_POWER_ON)) {
Paul Walmsleyc4d7e582010-12-21 21:05:14 -0700305 omap2_prm_set_mod_reg_bits(OMAP3430_EN_IO_MASK, WKUP_MOD, PM_WKEN);
Paul Walmsleyb02b9172011-10-06 17:18:45 -0600306 if (omap3_has_io_chain_ctrl())
307 omap3_enable_io_chain();
Mike Chan40742fa2010-05-03 16:04:06 -0700308 }
309
Charulatha Vff2f8e52011-09-13 18:32:37 +0530310 pwrdm_pre_transition();
311
Mike Chan40742fa2010-05-03 16:04:06 -0700312 /* PER */
Kevin Hilman658ce972008-11-04 20:50:52 -0800313 if (per_next_state < PWRDM_POWER_ON) {
Paul Walmsley72e06d02010-12-21 21:05:16 -0700314 per_going_off = (per_next_state == PWRDM_POWER_OFF) ? 1 : 0;
Paul Walmsley72e06d02010-12-21 21:05:16 -0700315 omap2_gpio_prepare_for_idle(per_going_off);
Kevin Hilman658ce972008-11-04 20:50:52 -0800316 }
317
318 /* CORE */
Rajendra Nayakfa3c2a42008-09-26 17:49:22 +0530319 if (core_next_state < PWRDM_POWER_ON) {
Rajendra Nayak2f5939c2008-09-26 17:50:07 +0530320 if (core_next_state == PWRDM_POWER_OFF) {
321 omap3_core_save_context();
Paul Walmsleyf0611a52010-12-21 15:30:56 -0700322 omap3_cm_save_context();
Rajendra Nayak2f5939c2008-09-26 17:50:07 +0530323 }
Rajendra Nayakfa3c2a42008-09-26 17:49:22 +0530324 }
Mike Chan40742fa2010-05-03 16:04:06 -0700325
Tero Kristof18cc2f2009-10-23 19:03:50 +0300326 omap3_intc_prepare_idle();
Kevin Hilman8bd22942009-05-28 10:56:16 -0700327
Rajendra Nayak61255ab2008-09-26 17:49:56 +0530328 /*
Paul Walmsley30474542011-10-06 13:43:23 -0600329 * On EMU/HS devices ROM code restores a SRDC value
330 * from scratchpad which has automatic self refresh on timeout
331 * of AUTO_CNT = 1 enabled. This takes care of erratum ID i443.
332 * Hence store/restore the SDRC_POWER register here.
333 */
334 if (cpu_is_omap3430() && omap_rev() >= OMAP3430_REV_ES3_0 &&
335 (omap_type() == OMAP2_DEVICE_TYPE_EMU ||
336 omap_type() == OMAP2_DEVICE_TYPE_SEC) &&
Rajendra Nayakf265dc42009-06-09 22:30:41 +0530337 core_next_state == PWRDM_POWER_OFF)
Tero Kristo13a6fe02008-10-13 13:17:06 +0300338 sdrc_pwr = sdrc_read_reg(SDRC_POWER);
Tero Kristo13a6fe02008-10-13 13:17:06 +0300339
340 /*
Russell King076f2cc2011-06-22 15:42:54 +0100341 * omap3_arm_context is the location where some ARM context
342 * get saved. The rest is placed on the stack, and restored
343 * from there before resuming.
Rajendra Nayak61255ab2008-09-26 17:49:56 +0530344 */
Russell Kingcbe26342011-06-30 08:45:49 +0100345 if (save_state)
346 omap34xx_save_context(omap3_arm_context);
Russell King076f2cc2011-06-22 15:42:54 +0100347 if (save_state == 1 || save_state == 3)
Russell King2c74a0c2011-06-22 17:41:48 +0100348 cpu_suspend(save_state, omap34xx_do_sram_idle);
Russell King076f2cc2011-06-22 15:42:54 +0100349 else
350 omap34xx_do_sram_idle(save_state);
Kevin Hilman8bd22942009-05-28 10:56:16 -0700351
Rajendra Nayakf265dc42009-06-09 22:30:41 +0530352 /* Restore normal SDRC POWER settings */
Paul Walmsley30474542011-10-06 13:43:23 -0600353 if (cpu_is_omap3430() && omap_rev() >= OMAP3430_REV_ES3_0 &&
354 (omap_type() == OMAP2_DEVICE_TYPE_EMU ||
355 omap_type() == OMAP2_DEVICE_TYPE_SEC) &&
Tero Kristo13a6fe02008-10-13 13:17:06 +0300356 core_next_state == PWRDM_POWER_OFF)
357 sdrc_write_reg(sdrc_pwr, SDRC_POWER);
358
Kevin Hilman658ce972008-11-04 20:50:52 -0800359 /* CORE */
Rajendra Nayakfa3c2a42008-09-26 17:49:22 +0530360 if (core_next_state < PWRDM_POWER_ON) {
Rajendra Nayak2f5939c2008-09-26 17:50:07 +0530361 core_prev_state = pwrdm_read_prev_pwrst(core_pwrdm);
362 if (core_prev_state == PWRDM_POWER_OFF) {
363 omap3_core_restore_context();
Paul Walmsleyf0611a52010-12-21 15:30:56 -0700364 omap3_cm_restore_context();
Rajendra Nayak2f5939c2008-09-26 17:50:07 +0530365 omap3_sram_restore_context();
Kalle Jokiniemi8a917d22009-05-13 13:32:11 +0300366 omap2_sms_restore_context();
Rajendra Nayak2f5939c2008-09-26 17:50:07 +0530367 }
Kevin Hilman658ce972008-11-04 20:50:52 -0800368 if (core_next_state == PWRDM_POWER_OFF)
Paul Walmsleyc4d7e582010-12-21 21:05:14 -0700369 omap2_prm_clear_mod_reg_bits(OMAP3430_AUTO_OFF_MASK,
Kevin Hilman658ce972008-11-04 20:50:52 -0800370 OMAP3430_GR_MOD,
371 OMAP3_PRM_VOLTCTRL_OFFSET);
372 }
Tero Kristof18cc2f2009-10-23 19:03:50 +0300373 omap3_intc_resume_idle();
Kevin Hilman658ce972008-11-04 20:50:52 -0800374
Charulatha Vff2f8e52011-09-13 18:32:37 +0530375 pwrdm_post_transition();
376
Kevin Hilman658ce972008-11-04 20:50:52 -0800377 /* PER */
378 if (per_next_state < PWRDM_POWER_ON) {
379 per_prev_state = pwrdm_read_prev_pwrst(per_pwrdm);
Kevin Hilman43ffcd92009-01-27 11:09:24 -0800380 omap2_gpio_resume_after_idle();
Rajendra Nayakfa3c2a42008-09-26 17:49:22 +0530381 }
Peter 'p2' De Schrijverfe617af2008-10-15 17:48:44 +0300382
Kalle Jokiniemi3a7ec262009-03-26 15:59:01 +0200383 /* Disable IO-PAD and IO-CHAIN wakeup */
Kevin Hilman58a55592010-08-16 09:21:19 +0300384 if (omap3_has_io_wakeup() &&
385 (per_next_state < PWRDM_POWER_ON ||
386 core_next_state < PWRDM_POWER_ON)) {
Paul Walmsleyc4d7e582010-12-21 21:05:14 -0700387 omap2_prm_clear_mod_reg_bits(OMAP3430_EN_IO_MASK, WKUP_MOD,
388 PM_WKEN);
Paul Walmsleyb02b9172011-10-06 17:18:45 -0600389 if (omap3_has_io_chain_ctrl())
390 omap3_disable_io_chain();
Kalle Jokiniemi3a7ec262009-03-26 15:59:01 +0200391 }
Kevin Hilman658ce972008-11-04 20:50:52 -0800392
Rajendra Nayak5cd19372011-02-25 16:06:48 -0700393 clkdm_allow_idle(mpu_pwrdm->pwrdm_clkdms[0]);
Kevin Hilman8bd22942009-05-28 10:56:16 -0700394}
395
Kevin Hilman8bd22942009-05-28 10:56:16 -0700396static void omap3_pm_idle(void)
397{
Kevin Hilman8bd22942009-05-28 10:56:16 -0700398 local_fiq_disable();
399
Nicolas Pitre0bcd24b2012-01-04 16:27:48 -0500400 if (omap_irq_pending())
Kevin Hilman8bd22942009-05-28 10:56:16 -0700401 goto out;
402
Jean Pihet5e7c58d2011-03-03 11:25:43 +0100403 trace_power_start(POWER_CSTATE, 1, smp_processor_id());
404 trace_cpu_idle(1, smp_processor_id());
405
Kevin Hilman8bd22942009-05-28 10:56:16 -0700406 omap_sram_idle();
407
Jean Pihet5e7c58d2011-03-03 11:25:43 +0100408 trace_power_end(smp_processor_id());
409 trace_cpu_idle(PWR_EVENT_EXIT, smp_processor_id());
410
Kevin Hilman8bd22942009-05-28 10:56:16 -0700411out:
412 local_fiq_enable();
Kevin Hilman8bd22942009-05-28 10:56:16 -0700413}
414
Kevin Hilman10f90ed2009-06-24 11:39:18 -0700415#ifdef CONFIG_SUSPEND
Kevin Hilman8bd22942009-05-28 10:56:16 -0700416static int omap3_pm_suspend(void)
417{
418 struct power_state *pwrst;
419 int state, ret = 0;
420
421 /* Read current next_pwrsts */
422 list_for_each_entry(pwrst, &pwrst_list, node)
423 pwrst->saved_state = pwrdm_read_next_pwrst(pwrst->pwrdm);
424 /* Set ones wanted by suspend */
425 list_for_each_entry(pwrst, &pwrst_list, node) {
Santosh Shilimkareb6a2c72010-09-15 01:04:01 +0530426 if (omap_set_pwrdm_state(pwrst->pwrdm, pwrst->next_state))
Kevin Hilman8bd22942009-05-28 10:56:16 -0700427 goto restore;
428 if (pwrdm_clear_all_prev_pwrst(pwrst->pwrdm))
429 goto restore;
430 }
431
Tero Kristo2bbe3af2009-10-23 19:03:48 +0300432 omap3_intc_suspend();
433
Kevin Hilman8bd22942009-05-28 10:56:16 -0700434 omap_sram_idle();
435
436restore:
437 /* Restore next_pwrsts */
438 list_for_each_entry(pwrst, &pwrst_list, node) {
Kevin Hilman8bd22942009-05-28 10:56:16 -0700439 state = pwrdm_read_prev_pwrst(pwrst->pwrdm);
440 if (state > pwrst->next_state) {
Mark A. Greer98179852012-03-17 18:22:48 -0700441 pr_info("Powerdomain (%s) didn't enter "
442 "target state %d\n",
Kevin Hilman8bd22942009-05-28 10:56:16 -0700443 pwrst->pwrdm->name, pwrst->next_state);
444 ret = -1;
445 }
Santosh Shilimkareb6a2c72010-09-15 01:04:01 +0530446 omap_set_pwrdm_state(pwrst->pwrdm, pwrst->saved_state);
Kevin Hilman8bd22942009-05-28 10:56:16 -0700447 }
448 if (ret)
Mark A. Greer98179852012-03-17 18:22:48 -0700449 pr_err("Could not enter target state in pm_suspend\n");
Kevin Hilman8bd22942009-05-28 10:56:16 -0700450 else
Mark A. Greer98179852012-03-17 18:22:48 -0700451 pr_info("Successfully put all powerdomains to target state\n");
Kevin Hilman8bd22942009-05-28 10:56:16 -0700452
453 return ret;
454}
455
Kevin Hilman10f90ed2009-06-24 11:39:18 -0700456#endif /* CONFIG_SUSPEND */
Kevin Hilman8bd22942009-05-28 10:56:16 -0700457
Kevin Hilman1155e422008-11-25 11:48:24 -0800458
459/**
460 * omap3_iva_idle(): ensure IVA is in idle so it can be put into
461 * retention
462 *
463 * In cases where IVA2 is activated by bootcode, it may prevent
464 * full-chip retention or off-mode because it is not idle. This
465 * function forces the IVA2 into idle state so it can go
466 * into retention/off and thus allow full-chip retention/off.
467 *
468 **/
469static void __init omap3_iva_idle(void)
470{
471 /* ensure IVA2 clock is disabled */
Paul Walmsleyc4d7e582010-12-21 21:05:14 -0700472 omap2_cm_write_mod_reg(0, OMAP3430_IVA2_MOD, CM_FCLKEN);
Kevin Hilman1155e422008-11-25 11:48:24 -0800473
474 /* if no clock activity, nothing else to do */
Paul Walmsleyc4d7e582010-12-21 21:05:14 -0700475 if (!(omap2_cm_read_mod_reg(OMAP3430_IVA2_MOD, OMAP3430_CM_CLKSTST) &
Kevin Hilman1155e422008-11-25 11:48:24 -0800476 OMAP3430_CLKACTIVITY_IVA2_MASK))
477 return;
478
479 /* Reset IVA2 */
Paul Walmsleyc4d7e582010-12-21 21:05:14 -0700480 omap2_prm_write_mod_reg(OMAP3430_RST1_IVA2_MASK |
Paul Walmsley2bc4ef72010-05-18 18:47:24 -0600481 OMAP3430_RST2_IVA2_MASK |
482 OMAP3430_RST3_IVA2_MASK,
Abhijit Pagare37903002010-01-26 20:12:51 -0700483 OMAP3430_IVA2_MOD, OMAP2_RM_RSTCTRL);
Kevin Hilman1155e422008-11-25 11:48:24 -0800484
485 /* Enable IVA2 clock */
Paul Walmsleyc4d7e582010-12-21 21:05:14 -0700486 omap2_cm_write_mod_reg(OMAP3430_CM_FCLKEN_IVA2_EN_IVA2_MASK,
Kevin Hilman1155e422008-11-25 11:48:24 -0800487 OMAP3430_IVA2_MOD, CM_FCLKEN);
488
489 /* Set IVA2 boot mode to 'idle' */
490 omap_ctrl_writel(OMAP3_IVA2_BOOTMOD_IDLE,
491 OMAP343X_CONTROL_IVA2_BOOTMOD);
492
493 /* Un-reset IVA2 */
Paul Walmsleyc4d7e582010-12-21 21:05:14 -0700494 omap2_prm_write_mod_reg(0, OMAP3430_IVA2_MOD, OMAP2_RM_RSTCTRL);
Kevin Hilman1155e422008-11-25 11:48:24 -0800495
496 /* Disable IVA2 clock */
Paul Walmsleyc4d7e582010-12-21 21:05:14 -0700497 omap2_cm_write_mod_reg(0, OMAP3430_IVA2_MOD, CM_FCLKEN);
Kevin Hilman1155e422008-11-25 11:48:24 -0800498
499 /* Reset IVA2 */
Paul Walmsleyc4d7e582010-12-21 21:05:14 -0700500 omap2_prm_write_mod_reg(OMAP3430_RST1_IVA2_MASK |
Paul Walmsley2bc4ef72010-05-18 18:47:24 -0600501 OMAP3430_RST2_IVA2_MASK |
502 OMAP3430_RST3_IVA2_MASK,
Abhijit Pagare37903002010-01-26 20:12:51 -0700503 OMAP3430_IVA2_MOD, OMAP2_RM_RSTCTRL);
Kevin Hilman1155e422008-11-25 11:48:24 -0800504}
505
Kevin Hilman8111b222009-04-28 15:27:44 -0700506static void __init omap3_d2d_idle(void)
Kevin Hilman8bd22942009-05-28 10:56:16 -0700507{
Kevin Hilman8111b222009-04-28 15:27:44 -0700508 u16 mask, padconf;
509
510 /* In a stand alone OMAP3430 where there is not a stacked
511 * modem for the D2D Idle Ack and D2D MStandby must be pulled
512 * high. S CONTROL_PADCONF_SAD2D_IDLEACK and
513 * CONTROL_PADCONF_SAD2D_MSTDBY to have a pull up. */
514 mask = (1 << 4) | (1 << 3); /* pull-up, enabled */
515 padconf = omap_ctrl_readw(OMAP3_PADCONF_SAD2D_MSTANDBY);
516 padconf |= mask;
517 omap_ctrl_writew(padconf, OMAP3_PADCONF_SAD2D_MSTANDBY);
518
519 padconf = omap_ctrl_readw(OMAP3_PADCONF_SAD2D_IDLEACK);
520 padconf |= mask;
521 omap_ctrl_writew(padconf, OMAP3_PADCONF_SAD2D_IDLEACK);
522
Kevin Hilman8bd22942009-05-28 10:56:16 -0700523 /* reset modem */
Paul Walmsleyc4d7e582010-12-21 21:05:14 -0700524 omap2_prm_write_mod_reg(OMAP3430_RM_RSTCTRL_CORE_MODEM_SW_RSTPWRON_MASK |
Paul Walmsley2bc4ef72010-05-18 18:47:24 -0600525 OMAP3430_RM_RSTCTRL_CORE_MODEM_SW_RST_MASK,
Abhijit Pagare37903002010-01-26 20:12:51 -0700526 CORE_MOD, OMAP2_RM_RSTCTRL);
Paul Walmsleyc4d7e582010-12-21 21:05:14 -0700527 omap2_prm_write_mod_reg(0, CORE_MOD, OMAP2_RM_RSTCTRL);
Kevin Hilman8111b222009-04-28 15:27:44 -0700528}
Kevin Hilman8bd22942009-05-28 10:56:16 -0700529
Kevin Hilman8111b222009-04-28 15:27:44 -0700530static void __init prcm_setup_regs(void)
531{
Govindraj.Re5863682010-09-27 20:20:25 +0530532 u32 omap3630_en_uart4_mask = cpu_is_omap3630() ?
533 OMAP3630_EN_UART4_MASK : 0;
534 u32 omap3630_grpsel_uart4_mask = cpu_is_omap3630() ?
535 OMAP3630_GRPSEL_UART4_MASK : 0;
536
Paul Walmsley4ef70c02011-02-25 15:39:30 -0700537 /* XXX This should be handled by hwmod code or SCM init code */
Paul Walmsley2fd0f752010-05-18 18:40:23 -0600538 omap_ctrl_writel(OMAP3430_AUTOIDLE_MASK, OMAP2_CONTROL_SYSCONFIG);
Tero Kristob296c812009-10-23 19:03:49 +0300539
Kevin Hilman8bd22942009-05-28 10:56:16 -0700540 /*
Kevin Hilman8bd22942009-05-28 10:56:16 -0700541 * Enable control of expternal oscillator through
542 * sys_clkreq. In the long run clock framework should
543 * take care of this.
544 */
Paul Walmsleyc4d7e582010-12-21 21:05:14 -0700545 omap2_prm_rmw_mod_reg_bits(OMAP_AUTOEXTCLKMODE_MASK,
Kevin Hilman8bd22942009-05-28 10:56:16 -0700546 1 << OMAP_AUTOEXTCLKMODE_SHIFT,
547 OMAP3430_GR_MOD,
548 OMAP3_PRM_CLKSRC_CTRL_OFFSET);
549
550 /* setup wakup source */
Paul Walmsleyc4d7e582010-12-21 21:05:14 -0700551 omap2_prm_write_mod_reg(OMAP3430_EN_IO_MASK | OMAP3430_EN_GPIO1_MASK |
Paul Walmsley2fd0f752010-05-18 18:40:23 -0600552 OMAP3430_EN_GPT1_MASK | OMAP3430_EN_GPT12_MASK,
Kevin Hilman8bd22942009-05-28 10:56:16 -0700553 WKUP_MOD, PM_WKEN);
554 /* No need to write EN_IO, that is always enabled */
Paul Walmsleyc4d7e582010-12-21 21:05:14 -0700555 omap2_prm_write_mod_reg(OMAP3430_GRPSEL_GPIO1_MASK |
Paul Walmsley275f6752010-05-18 18:40:23 -0600556 OMAP3430_GRPSEL_GPT1_MASK |
557 OMAP3430_GRPSEL_GPT12_MASK,
Kevin Hilman8bd22942009-05-28 10:56:16 -0700558 WKUP_MOD, OMAP3430_PM_MPUGRPSEL);
Kevin Hilman1155e422008-11-25 11:48:24 -0800559
Subramani Venkateshb92c5722009-12-22 15:07:50 +0530560 /* Enable PM_WKEN to support DSS LPR */
Paul Walmsleyc4d7e582010-12-21 21:05:14 -0700561 omap2_prm_write_mod_reg(OMAP3430_PM_WKEN_DSS_EN_DSS_MASK,
Subramani Venkateshb92c5722009-12-22 15:07:50 +0530562 OMAP3430_DSS_MOD, PM_WKEN);
563
Kevin Hilmanb427f922009-10-22 14:48:13 -0700564 /* Enable wakeups in PER */
Paul Walmsleyc4d7e582010-12-21 21:05:14 -0700565 omap2_prm_write_mod_reg(omap3630_en_uart4_mask |
Govindraj.Re5863682010-09-27 20:20:25 +0530566 OMAP3430_EN_GPIO2_MASK | OMAP3430_EN_GPIO3_MASK |
Paul Walmsley2fd0f752010-05-18 18:40:23 -0600567 OMAP3430_EN_GPIO4_MASK | OMAP3430_EN_GPIO5_MASK |
568 OMAP3430_EN_GPIO6_MASK | OMAP3430_EN_UART3_MASK |
569 OMAP3430_EN_MCBSP2_MASK | OMAP3430_EN_MCBSP3_MASK |
570 OMAP3430_EN_MCBSP4_MASK,
Kevin Hilmanb427f922009-10-22 14:48:13 -0700571 OMAP3430_PER_MOD, PM_WKEN);
Kevin Hilmaneb350f72009-09-10 15:53:08 +0000572 /* and allow them to wake up MPU */
Paul Walmsleyc4d7e582010-12-21 21:05:14 -0700573 omap2_prm_write_mod_reg(omap3630_grpsel_uart4_mask |
Govindraj.Re5863682010-09-27 20:20:25 +0530574 OMAP3430_GRPSEL_GPIO2_MASK |
Paul Walmsley275f6752010-05-18 18:40:23 -0600575 OMAP3430_GRPSEL_GPIO3_MASK |
576 OMAP3430_GRPSEL_GPIO4_MASK |
577 OMAP3430_GRPSEL_GPIO5_MASK |
578 OMAP3430_GRPSEL_GPIO6_MASK |
579 OMAP3430_GRPSEL_UART3_MASK |
580 OMAP3430_GRPSEL_MCBSP2_MASK |
581 OMAP3430_GRPSEL_MCBSP3_MASK |
582 OMAP3430_GRPSEL_MCBSP4_MASK,
Kevin Hilmaneb350f72009-09-10 15:53:08 +0000583 OMAP3430_PER_MOD, OMAP3430_PM_MPUGRPSEL);
584
Kevin Hilmand3fd3292009-05-05 16:34:25 -0700585 /* Don't attach IVA interrupts */
Paul Walmsleyc4d7e582010-12-21 21:05:14 -0700586 omap2_prm_write_mod_reg(0, WKUP_MOD, OMAP3430_PM_IVAGRPSEL);
587 omap2_prm_write_mod_reg(0, CORE_MOD, OMAP3430_PM_IVAGRPSEL1);
588 omap2_prm_write_mod_reg(0, CORE_MOD, OMAP3430ES2_PM_IVAGRPSEL3);
589 omap2_prm_write_mod_reg(0, OMAP3430_PER_MOD, OMAP3430_PM_IVAGRPSEL);
Kevin Hilmand3fd3292009-05-05 16:34:25 -0700590
Kevin Hilmanb1340d12009-04-27 16:14:54 -0700591 /* Clear any pending 'reset' flags */
Paul Walmsleyc4d7e582010-12-21 21:05:14 -0700592 omap2_prm_write_mod_reg(0xffffffff, MPU_MOD, OMAP2_RM_RSTST);
593 omap2_prm_write_mod_reg(0xffffffff, CORE_MOD, OMAP2_RM_RSTST);
594 omap2_prm_write_mod_reg(0xffffffff, OMAP3430_PER_MOD, OMAP2_RM_RSTST);
595 omap2_prm_write_mod_reg(0xffffffff, OMAP3430_EMU_MOD, OMAP2_RM_RSTST);
596 omap2_prm_write_mod_reg(0xffffffff, OMAP3430_NEON_MOD, OMAP2_RM_RSTST);
597 omap2_prm_write_mod_reg(0xffffffff, OMAP3430_DSS_MOD, OMAP2_RM_RSTST);
598 omap2_prm_write_mod_reg(0xffffffff, OMAP3430ES2_USBHOST_MOD, OMAP2_RM_RSTST);
Kevin Hilmanb1340d12009-04-27 16:14:54 -0700599
Kevin Hilman014c46d2009-04-27 07:50:23 -0700600 /* Clear any pending PRCM interrupts */
Paul Walmsleyc4d7e582010-12-21 21:05:14 -0700601 omap2_prm_write_mod_reg(0, OCP_MOD, OMAP3_PRM_IRQSTATUS_MPU_OFFSET);
Kevin Hilman014c46d2009-04-27 07:50:23 -0700602
Kevin Hilman1155e422008-11-25 11:48:24 -0800603 omap3_iva_idle();
Kevin Hilman8111b222009-04-28 15:27:44 -0700604 omap3_d2d_idle();
Kevin Hilman8bd22942009-05-28 10:56:16 -0700605}
606
Kevin Hilmanc40552b2009-10-06 14:25:09 -0700607void omap3_pm_off_mode_enable(int enable)
608{
609 struct power_state *pwrst;
610 u32 state;
611
612 if (enable)
613 state = PWRDM_POWER_OFF;
614 else
615 state = PWRDM_POWER_RET;
616
617 list_for_each_entry(pwrst, &pwrst_list, node) {
Eduardo Valentincc1b6022010-12-20 14:05:09 -0600618 if (IS_PM34XX_ERRATUM(PM_SDRC_WAKEUP_ERRATUM_i583) &&
619 pwrst->pwrdm == core_pwrdm &&
620 state == PWRDM_POWER_OFF) {
621 pwrst->next_state = PWRDM_POWER_RET;
Ricardo Salveti de Araujoe16b41b2011-01-31 11:35:25 -0200622 pr_warn("%s: Core OFF disabled due to errata i583\n",
Eduardo Valentincc1b6022010-12-20 14:05:09 -0600623 __func__);
624 } else {
625 pwrst->next_state = state;
626 }
627 omap_set_pwrdm_state(pwrst->pwrdm, pwrst->next_state);
Kevin Hilmanc40552b2009-10-06 14:25:09 -0700628 }
629}
630
Tero Kristo68d47782008-11-26 12:26:24 +0200631int omap3_pm_get_suspend_state(struct powerdomain *pwrdm)
632{
633 struct power_state *pwrst;
634
635 list_for_each_entry(pwrst, &pwrst_list, node) {
636 if (pwrst->pwrdm == pwrdm)
637 return pwrst->next_state;
638 }
639 return -EINVAL;
640}
641
642int omap3_pm_set_suspend_state(struct powerdomain *pwrdm, int state)
643{
644 struct power_state *pwrst;
645
646 list_for_each_entry(pwrst, &pwrst_list, node) {
647 if (pwrst->pwrdm == pwrdm) {
648 pwrst->next_state = state;
649 return 0;
650 }
651 }
652 return -EINVAL;
653}
654
Peter 'p2' De Schrijvera23456e2008-10-15 18:13:47 +0300655static int __init pwrdms_setup(struct powerdomain *pwrdm, void *unused)
Kevin Hilman8bd22942009-05-28 10:56:16 -0700656{
657 struct power_state *pwrst;
658
659 if (!pwrdm->pwrsts)
660 return 0;
661
Ming Leid3d381c2009-08-22 21:20:26 +0800662 pwrst = kmalloc(sizeof(struct power_state), GFP_ATOMIC);
Kevin Hilman8bd22942009-05-28 10:56:16 -0700663 if (!pwrst)
664 return -ENOMEM;
665 pwrst->pwrdm = pwrdm;
666 pwrst->next_state = PWRDM_POWER_RET;
667 list_add(&pwrst->node, &pwrst_list);
668
669 if (pwrdm_has_hdwr_sar(pwrdm))
670 pwrdm_enable_hdwr_sar(pwrdm);
671
Santosh Shilimkareb6a2c72010-09-15 01:04:01 +0530672 return omap_set_pwrdm_state(pwrst->pwrdm, pwrst->next_state);
Kevin Hilman8bd22942009-05-28 10:56:16 -0700673}
674
675/*
Jean Pihet46e130d2011-06-29 18:40:23 +0200676 * Push functions to SRAM
677 *
678 * The minimum set of functions is pushed to SRAM for execution:
679 * - omap3_do_wfi for erratum i581 WA,
680 * - save_secure_ram_context for security extensions.
681 */
Rajendra Nayak3231fc82008-09-26 17:49:14 +0530682void omap_push_sram_idle(void)
683{
Jean Pihet46e130d2011-06-29 18:40:23 +0200684 omap3_do_wfi_sram = omap_sram_push(omap3_do_wfi, omap3_do_wfi_sz);
685
Tero Kristo27d59a42008-10-13 13:15:00 +0300686 if (omap_type() != OMAP2_DEVICE_TYPE_GP)
687 _omap_save_secure_sram = omap_sram_push(save_secure_ram_context,
688 save_secure_ram_context_sz);
Rajendra Nayak3231fc82008-09-26 17:49:14 +0530689}
690
Nishanth Menon8cdfd832010-12-20 14:05:05 -0600691static void __init pm_errata_configure(void)
692{
Peter 'p2' De Schrijverc4236d22010-12-20 14:05:07 -0600693 if (cpu_is_omap3630()) {
Nishanth Menon458e9992010-12-20 14:05:06 -0600694 pm34xx_errata |= PM_RTA_ERRATUM_i608;
Peter 'p2' De Schrijverc4236d22010-12-20 14:05:07 -0600695 /* Enable the l2 cache toggling in sleep logic */
696 enable_omap3630_toggle_l2_on_restore();
Eduardo Valentincc1b6022010-12-20 14:05:09 -0600697 if (omap_rev() < OMAP3630_REV_ES1_2)
698 pm34xx_errata |= PM_SDRC_WAKEUP_ERRATUM_i583;
Peter 'p2' De Schrijverc4236d22010-12-20 14:05:07 -0600699 }
Nishanth Menon8cdfd832010-12-20 14:05:05 -0600700}
701
Kevin Hilman7cc515f2009-06-10 09:02:25 -0700702static int __init omap3_pm_init(void)
Kevin Hilman8bd22942009-05-28 10:56:16 -0700703{
704 struct power_state *pwrst, *tmp;
Paul Walmsley55ed9692010-01-26 20:12:59 -0700705 struct clockdomain *neon_clkdm, *per_clkdm, *mpu_clkdm, *core_clkdm;
Kevin Hilman8bd22942009-05-28 10:56:16 -0700706 int ret;
707
708 if (!cpu_is_omap34xx())
709 return -ENODEV;
710
Paul Walmsleyb02b9172011-10-06 17:18:45 -0600711 if (!omap3_has_io_chain_ctrl())
712 pr_warning("PM: no software I/O chain control; some wakeups may be lost\n");
713
Nishanth Menon8cdfd832010-12-20 14:05:05 -0600714 pm_errata_configure();
715
Kevin Hilman8bd22942009-05-28 10:56:16 -0700716 /* XXX prcm_setup_regs needs to be before enabling hw
717 * supervised mode for powerdomains */
718 prcm_setup_regs();
719
Tero Kristo22f51372011-12-16 14:36:59 -0700720 ret = request_irq(omap_prcm_event_to_irq("wkup"),
721 _prcm_int_handle_wakeup, IRQF_NO_SUSPEND, "pm_wkup", NULL);
722
Kevin Hilman8bd22942009-05-28 10:56:16 -0700723 if (ret) {
Tero Kristo22f51372011-12-16 14:36:59 -0700724 pr_err("pm: Failed to request pm_wkup irq\n");
725 goto err1;
726 }
727
728 /* IO interrupt is shared with mux code */
729 ret = request_irq(omap_prcm_event_to_irq("io"),
730 _prcm_int_handle_io, IRQF_SHARED | IRQF_NO_SUSPEND, "pm_io",
731 omap3_pm_init);
732
733 if (ret) {
734 pr_err("pm: Failed to request pm_io irq\n");
Mark A. Greerce229c52012-03-17 18:22:47 -0700735 goto err2;
Kevin Hilman8bd22942009-05-28 10:56:16 -0700736 }
737
Peter 'p2' De Schrijvera23456e2008-10-15 18:13:47 +0300738 ret = pwrdm_for_each(pwrdms_setup, NULL);
Kevin Hilman8bd22942009-05-28 10:56:16 -0700739 if (ret) {
Mark A. Greer98179852012-03-17 18:22:48 -0700740 pr_err("Failed to setup powerdomains\n");
Mark A. Greerce229c52012-03-17 18:22:47 -0700741 goto err3;
Kevin Hilman8bd22942009-05-28 10:56:16 -0700742 }
743
Paul Walmsley92206fd2012-02-02 02:38:50 -0700744 (void) clkdm_for_each(omap_pm_clkdms_setup, NULL);
Kevin Hilman8bd22942009-05-28 10:56:16 -0700745
746 mpu_pwrdm = pwrdm_lookup("mpu_pwrdm");
747 if (mpu_pwrdm == NULL) {
Mark A. Greer98179852012-03-17 18:22:48 -0700748 pr_err("Failed to get mpu_pwrdm\n");
Mark A. Greerce229c52012-03-17 18:22:47 -0700749 ret = -EINVAL;
750 goto err3;
Kevin Hilman8bd22942009-05-28 10:56:16 -0700751 }
752
Rajendra Nayakfa3c2a42008-09-26 17:49:22 +0530753 neon_pwrdm = pwrdm_lookup("neon_pwrdm");
754 per_pwrdm = pwrdm_lookup("per_pwrdm");
755 core_pwrdm = pwrdm_lookup("core_pwrdm");
Tero Kristoc16c3f62008-12-11 16:46:57 +0200756 cam_pwrdm = pwrdm_lookup("cam_pwrdm");
Rajendra Nayakfa3c2a42008-09-26 17:49:22 +0530757
Paul Walmsley55ed9692010-01-26 20:12:59 -0700758 neon_clkdm = clkdm_lookup("neon_clkdm");
759 mpu_clkdm = clkdm_lookup("mpu_clkdm");
760 per_clkdm = clkdm_lookup("per_clkdm");
761 core_clkdm = clkdm_lookup("core_clkdm");
762
Kevin Hilman10f90ed2009-06-24 11:39:18 -0700763#ifdef CONFIG_SUSPEND
Paul Walmsley14164082012-02-02 02:30:50 -0700764 omap_pm_suspend = omap3_pm_suspend;
765#endif
Kevin Hilman8bd22942009-05-28 10:56:16 -0700766
Nicolas Pitre0bcd24b2012-01-04 16:27:48 -0500767 arm_pm_idle = omap3_pm_idle;
Kalle Jokiniemi03433712008-09-26 11:04:20 +0300768 omap3_idle_init();
Kevin Hilman8bd22942009-05-28 10:56:16 -0700769
Nishanth Menon458e9992010-12-20 14:05:06 -0600770 /*
771 * RTA is disabled during initialization as per erratum i608
772 * it is safer to disable RTA by the bootloader, but we would like
773 * to be doubly sure here and prevent any mishaps.
774 */
775 if (IS_PM34XX_ERRATUM(PM_RTA_ERRATUM_i608))
776 omap3630_ctrl_disable_rta();
777
Paul Walmsley55ed9692010-01-26 20:12:59 -0700778 clkdm_add_wkdep(neon_clkdm, mpu_clkdm);
Tero Kristo27d59a42008-10-13 13:15:00 +0300779 if (omap_type() != OMAP2_DEVICE_TYPE_GP) {
780 omap3_secure_ram_storage =
781 kmalloc(0x803F, GFP_KERNEL);
782 if (!omap3_secure_ram_storage)
Mark A. Greer98179852012-03-17 18:22:48 -0700783 pr_err("Memory allocation failed when "
784 "allocating for secure sram context\n");
Tero Kristo27d59a42008-10-13 13:15:00 +0300785
Tero Kristo9d971402008-12-12 11:20:05 +0200786 local_irq_disable();
787 local_fiq_disable();
788
789 omap_dma_global_context_save();
Kevin Hilman617fcc92011-01-25 16:40:01 -0800790 omap3_save_secure_ram_context();
Tero Kristo9d971402008-12-12 11:20:05 +0200791 omap_dma_global_context_restore();
792
793 local_irq_enable();
794 local_fiq_enable();
795 }
796
797 omap3_save_scratchpad_contents();
Kevin Hilman8bd22942009-05-28 10:56:16 -0700798 return ret;
Mark A. Greerce229c52012-03-17 18:22:47 -0700799
800err3:
Kevin Hilman8bd22942009-05-28 10:56:16 -0700801 list_for_each_entry_safe(pwrst, tmp, &pwrst_list, node) {
802 list_del(&pwrst->node);
803 kfree(pwrst);
804 }
Mark A. Greerce229c52012-03-17 18:22:47 -0700805 free_irq(omap_prcm_event_to_irq("io"), omap3_pm_init);
806err2:
807 free_irq(omap_prcm_event_to_irq("wkup"), NULL);
808err1:
Kevin Hilman8bd22942009-05-28 10:56:16 -0700809 return ret;
810}
811
812late_initcall(omap3_pm_init);