| Russell King | a09e64f | 2008-08-05 16:14:15 +0100 | [diff] [blame] | 1 | /* arch/arm/mach-s3c2410/include/mach/regs-s3c2412-mem.h |
| 2 | * |
| 3 | * Copyright (c) 2008 Simtec Electronics |
| 4 | * Ben Dooks <ben@simtec.co.uk> |
| 5 | * http://armlinux.simtec.co.uk/ |
| 6 | * |
| 7 | * This program is free software; you can redistribute it and/or modify |
| 8 | * it under the terms of the GNU General Public License version 2 as |
| 9 | * published by the Free Software Foundation. |
| 10 | * |
| 11 | * S3C2412 memory register definitions |
| 12 | */ |
| 13 | |
| 14 | #ifndef __ASM_ARM_REGS_S3C2412_MEM |
| 15 | #define __ASM_ARM_REGS_S3C2412_MEM |
| 16 | |
| Russell King | a09e64f | 2008-08-05 16:14:15 +0100 | [diff] [blame] | 17 | #define S3C2412_MEMREG(x) (S3C24XX_VA_MEMCTRL + (x)) |
| Ben Dooks | 2540003 | 2009-07-30 23:23:36 +0100 | [diff] [blame] | 18 | #define S3C2412_EBIREG(x) (S3C2412_VA_EBI + (x)) |
| 19 | |
| 20 | #define S3C2412_SSMCREG(x) (S3C2412_VA_SSMC + (x)) |
| 21 | #define S3C2412_SSMC(x, o) (S3C2412_SSMCREG((x * 0x20) + (o))) |
| Russell King | a09e64f | 2008-08-05 16:14:15 +0100 | [diff] [blame] | 22 | |
| 23 | #define S3C2412_BANKCFG S3C2412_MEMREG(0x00) |
| 24 | #define S3C2412_BANKCON1 S3C2412_MEMREG(0x04) |
| 25 | #define S3C2412_BANKCON2 S3C2412_MEMREG(0x08) |
| 26 | #define S3C2412_BANKCON3 S3C2412_MEMREG(0x0C) |
| 27 | |
| 28 | #define S3C2412_REFRESH S3C2412_MEMREG(0x10) |
| 29 | #define S3C2412_TIMEOUT S3C2412_MEMREG(0x14) |
| 30 | |
| Ben Dooks | 2540003 | 2009-07-30 23:23:36 +0100 | [diff] [blame] | 31 | /* EBI control registers */ |
| 32 | |
| 33 | #define S3C2412_EBI_PR S3C2412_EBIREG(0x00) |
| 34 | #define S3C2412_EBI_BANKCFG S3C2412_EBIREG(0x04) |
| 35 | |
| 36 | /* SSMC control registers */ |
| 37 | |
| 38 | #define S3C2412_SSMC_BANK(x) S3C2412_SSMC(x, 0x00) |
| 39 | #define S3C2412_SMIDCYR(x) S3C2412_SSMC(x, 0x00) |
| 40 | #define S3C2412_SMBWSTRD(x) S3C2412_SSMC(x, 0x04) |
| 41 | #define S3C2412_SMBWSTWRR(x) S3C2412_SSMC(x, 0x08) |
| 42 | #define S3C2412_SMBWSTOENR(x) S3C2412_SSMC(x, 0x0C) |
| 43 | #define S3C2412_SMBWSTWENR(x) S3C2412_SSMC(x, 0x10) |
| 44 | #define S3C2412_SMBCR(x) S3C2412_SSMC(x, 0x14) |
| 45 | #define S3C2412_SMBSR(x) S3C2412_SSMC(x, 0x18) |
| 46 | #define S3C2412_SMBWSTBRDR(x) S3C2412_SSMC(x, 0x1C) |
| 47 | |
| Russell King | a09e64f | 2008-08-05 16:14:15 +0100 | [diff] [blame] | 48 | #endif /* __ASM_ARM_REGS_S3C2412_MEM */ |