| H. Peter Anvin | 5e1b007 | 2008-10-23 00:20:33 -0700 | [diff] [blame] | 1 | #ifndef _ASM_X86_IRQ_REMAPPING_H |
| 2 | #define _ASM_X86_IRQ_REMAPPING_H |
| Suresh Siddha | 89027d3 | 2008-07-10 11:16:56 -0700 | [diff] [blame] | 3 | |
| Suresh Siddha | fc1edaf | 2009-04-20 13:02:27 -0700 | [diff] [blame] | 4 | #define IRTE_DEST(dest) ((x2apic_mode) ? dest : dest << 8) |
| Suresh Siddha | 89027d3 | 2008-07-10 11:16:56 -0700 | [diff] [blame] | 5 | |
| Suresh Siddha | 62a92f4 | 2010-08-27 11:09:49 -0700 | [diff] [blame^] | 6 | #ifdef CONFIG_INTR_REMAP |
| 7 | static inline void prepare_irte(struct irte *irte, int vector, |
| 8 | unsigned int dest) |
| 9 | { |
| 10 | memset(irte, 0, sizeof(*irte)); |
| 11 | |
| 12 | irte->present = 1; |
| 13 | irte->dst_mode = apic->irq_dest_mode; |
| 14 | /* |
| 15 | * Trigger mode in the IRTE will always be edge, and for IO-APIC, the |
| 16 | * actual level or edge trigger will be setup in the IO-APIC |
| 17 | * RTE. This will help simplify level triggered irq migration. |
| 18 | * For more details, see the comments (in io_apic.c) explainig IO-APIC |
| 19 | * irq migration in the presence of interrupt-remapping. |
| 20 | */ |
| 21 | irte->trigger_mode = 0; |
| 22 | irte->dlvry_mode = apic->irq_delivery_mode; |
| 23 | irte->vector = vector; |
| 24 | irte->dest_id = IRTE_DEST(dest); |
| 25 | irte->redir_hint = 1; |
| 26 | } |
| 27 | #else |
| 28 | static void prepare_irte(struct irte *irte, int vector, unsigned int dest) |
| 29 | { |
| 30 | } |
| 31 | #endif |
| 32 | |
| H. Peter Anvin | 5e1b007 | 2008-10-23 00:20:33 -0700 | [diff] [blame] | 33 | #endif /* _ASM_X86_IRQ_REMAPPING_H */ |