| Peter De Schrijver | c3e00a0 | 2011-12-14 17:03:13 +0200 | [diff] [blame] | 1 | /include/ "skeleton.dtsi" |
| 2 | |
| 3 | / { |
| 4 | compatible = "nvidia,tegra30"; |
| 5 | interrupt-parent = <&intc>; |
| 6 | |
| 7 | intc: interrupt-controller@50041000 { |
| 8 | compatible = "arm,cortex-a9-gic"; |
| 9 | interrupt-controller; |
| 10 | #interrupt-cells = <3>; |
| 11 | reg = < 0x50041000 0x1000 >, |
| 12 | < 0x50040100 0x0100 >; |
| 13 | }; |
| 14 | |
| 15 | i2c@7000c000 { |
| 16 | #address-cells = <1>; |
| 17 | #size-cells = <0>; |
| 18 | compatible = "nvidia,tegra30-i2c", "nvidia,tegra20-i2c"; |
| 19 | reg = <0x7000C000 0x100>; |
| 20 | interrupts = < 0 38 0x04 >; |
| 21 | }; |
| 22 | |
| 23 | i2c@7000c400 { |
| 24 | #address-cells = <1>; |
| 25 | #size-cells = <0>; |
| 26 | compatible = "nvidia,tegra30-i2c", "nvidia,tegra20-i2c"; |
| 27 | reg = <0x7000C400 0x100>; |
| 28 | interrupts = < 0 84 0x04 >; |
| 29 | }; |
| 30 | |
| 31 | i2c@7000c500 { |
| 32 | #address-cells = <1>; |
| 33 | #size-cells = <0>; |
| 34 | compatible = "nvidia,tegra30-i2c", "nvidia,tegra20-i2c"; |
| 35 | reg = <0x7000C500 0x100>; |
| 36 | interrupts = < 0 92 0x04 >; |
| 37 | }; |
| 38 | |
| 39 | i2c@7000c700 { |
| 40 | #address-cells = <1>; |
| 41 | #size-cells = <0>; |
| 42 | compatible = "nvidia,tegra30-i2c", "nvidia,tegra20-i2c"; |
| 43 | reg = <0x7000c700 0x100>; |
| 44 | interrupts = < 0 120 0x04 >; |
| 45 | }; |
| 46 | |
| 47 | i2c@7000d000 { |
| 48 | #address-cells = <1>; |
| 49 | #size-cells = <0>; |
| 50 | compatible = "nvidia,tegra30-i2c", "nvidia,tegra20-i2c"; |
| 51 | reg = <0x7000D000 0x100>; |
| 52 | interrupts = < 0 53 0x04 >; |
| 53 | }; |
| 54 | |
| 55 | gpio: gpio@6000d000 { |
| 56 | compatible = "nvidia,tegra30-gpio", "nvidia,tegra20-gpio"; |
| 57 | reg = < 0x6000d000 0x1000 >; |
| Stephen Warren | 636e50a | 2012-01-04 08:39:35 +0000 | [diff] [blame^] | 58 | interrupts = < 0 32 0x04 |
| 59 | 0 33 0x04 |
| 60 | 0 34 0x04 |
| 61 | 0 35 0x04 |
| 62 | 0 55 0x04 |
| 63 | 0 87 0x04 |
| 64 | 0 89 0x04 >; |
| Peter De Schrijver | c3e00a0 | 2011-12-14 17:03:13 +0200 | [diff] [blame] | 65 | #gpio-cells = <2>; |
| 66 | gpio-controller; |
| 67 | }; |
| 68 | |
| 69 | serial@70006000 { |
| 70 | compatible = "nvidia,tegra30-uart", "nvidia,tegra20-uart"; |
| 71 | reg = <0x70006000 0x40>; |
| 72 | reg-shift = <2>; |
| 73 | interrupts = < 0 36 0x04 >; |
| 74 | }; |
| 75 | |
| 76 | serial@70006040 { |
| 77 | compatible = "nvidia,tegra30-uart", "nvidia,tegra20-uart"; |
| 78 | reg = <0x70006040 0x40>; |
| 79 | reg-shift = <2>; |
| 80 | interrupts = < 0 37 0x04 >; |
| 81 | }; |
| 82 | |
| 83 | serial@70006200 { |
| 84 | compatible = "nvidia,tegra30-uart", "nvidia,tegra20-uart"; |
| 85 | reg = <0x70006200 0x100>; |
| 86 | reg-shift = <2>; |
| 87 | interrupts = < 0 46 0x04 >; |
| 88 | }; |
| 89 | |
| 90 | serial@70006300 { |
| 91 | compatible = "nvidia,tegra30-uart", "nvidia,tegra20-uart"; |
| 92 | reg = <0x70006300 0x100>; |
| 93 | reg-shift = <2>; |
| 94 | interrupts = < 0 90 0x04 >; |
| 95 | }; |
| 96 | |
| 97 | serial@70006400 { |
| 98 | compatible = "nvidia,tegra30-uart", "nvidia,tegra20-uart"; |
| 99 | reg = <0x70006400 0x100>; |
| 100 | reg-shift = <2>; |
| 101 | interrupts = < 0 91 0x04 >; |
| 102 | }; |
| 103 | |
| 104 | sdhci@78000000 { |
| 105 | compatible = "nvidia,tegra30-sdhci", "nvidia,tegra20-sdhci"; |
| 106 | reg = <0x78000000 0x200>; |
| 107 | interrupts = < 0 14 0x04 >; |
| 108 | }; |
| 109 | |
| 110 | sdhci@78000200 { |
| 111 | compatible = "nvidia,tegra30-sdhci", "nvidia,tegra20-sdhci"; |
| 112 | reg = <0x78000200 0x200>; |
| 113 | interrupts = < 0 15 0x04 >; |
| 114 | }; |
| 115 | |
| 116 | sdhci@78000400 { |
| 117 | compatible = "nvidia,tegra30-sdhci", "nvidia,tegra20-sdhci"; |
| 118 | reg = <0x78000400 0x200>; |
| 119 | interrupts = < 0 19 0x04 >; |
| 120 | }; |
| 121 | |
| 122 | sdhci@78000600 { |
| 123 | compatible = "nvidia,tegra30-sdhci", "nvidia,tegra20-sdhci"; |
| 124 | reg = <0x78000600 0x200>; |
| 125 | interrupts = < 0 31 0x04 >; |
| 126 | }; |
| 127 | |
| 128 | pinmux: pinmux@70000000 { |
| 129 | compatible = "nvidia,tegra30-pinmux"; |
| 130 | reg = < 0x70000868 0xd0 /* Pad control registers */ |
| 131 | 0x70003000 0x3e0 >; /* Mux registers */ |
| 132 | }; |
| 133 | }; |