| Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1 | /* |
| 2 | * include/asm-ppc/platforms/mvme5100.h |
| 3 | * |
| 4 | * Definitions for Motorola MVME5100. |
| 5 | * |
| 6 | * Author: Matt Porter <mporter@mvista.com> |
| 7 | * |
| 8 | * 2001 (c) MontaVista, Software, Inc. This file is licensed under |
| 9 | * the terms of the GNU General Public License version 2. This program |
| 10 | * is licensed "as is" without any warranty of any kind, whether express |
| 11 | * or implied. |
| 12 | */ |
| 13 | |
| 14 | #ifdef __KERNEL__ |
| 15 | #ifndef __ASM_MVME5100_H__ |
| 16 | #define __ASM_MVME5100_H__ |
| 17 | |
| 18 | #define MVME5100_HAWK_SMC_BASE 0xfef80000 |
| 19 | |
| 20 | #define MVME5100_PCI_CONFIG_ADDR 0xfe000cf8 |
| 21 | #define MVME5100_PCI_CONFIG_DATA 0xfe000cfc |
| 22 | |
| 23 | #define MVME5100_PCI_IO_BASE 0xfe000000 |
| 24 | #define MVME5100_PCI_MEM_BASE 0x80000000 |
| 25 | |
| 26 | #define MVME5100_PCI_MEM_OFFSET 0x00000000 |
| 27 | |
| 28 | #define MVME5100_PCI_DRAM_OFFSET 0x00000000 |
| 29 | #define MVME5100_ISA_MEM_BASE 0x00000000 |
| 30 | #define MVME5100_ISA_IO_BASE MVME5100_PCI_IO_BASE |
| 31 | |
| 32 | #define MVME5100_PCI_LOWER_MEM 0x80000000 |
| 33 | #define MVME5100_PCI_UPPER_MEM 0xf3f7ffff |
| 34 | #define MVME5100_PCI_LOWER_IO 0x00000000 |
| 35 | #define MVME5100_PCI_UPPER_IO 0x0077ffff |
| 36 | |
| 37 | /* MVME5100 board register addresses. */ |
| 38 | #define MVME5100_BOARD_STATUS_REG 0xfef88080 |
| 39 | #define MVME5100_BOARD_MODFAIL_REG 0xfef88090 |
| 40 | #define MVME5100_BOARD_MODRST_REG 0xfef880a0 |
| 41 | #define MVME5100_BOARD_TBEN_REG 0xfef880c0 |
| 42 | #define MVME5100_BOARD_SW_READ_REG 0xfef880e0 |
| 43 | #define MVME5100_BOARD_GEO_ADDR_REG 0xfef880e8 |
| 44 | #define MVME5100_BOARD_EXT_FEATURE1_REG 0xfef880f0 |
| 45 | #define MVME5100_BOARD_EXT_FEATURE2_REG 0xfef88100 |
| 46 | |
| 47 | /* Define the NVRAM/RTC address strobe & data registers */ |
| 48 | #define MVME5100_PHYS_NVRAM_AS0 0xfef880c8 |
| 49 | #define MVME5100_PHYS_NVRAM_AS1 0xfef880d0 |
| 50 | #define MVME5100_PHYS_NVRAM_DATA 0xfef880d8 |
| 51 | |
| 52 | #define MVME5100_NVRAM_AS0 (MVME5100_PHYS_NVRAM_AS0 - MVME5100_ISA_IO_BASE) |
| 53 | #define MVME5100_NVRAM_AS1 (MVME5100_PHYS_NVRAM_AS1 - MVME5100_ISA_IO_BASE) |
| 54 | #define MVME5100_NVRAM_DATA (MVME5100_PHYS_NVRAM_DATA - MVME5100_ISA_IO_BASE) |
| 55 | |
| 56 | /* UART clock, addresses, and irq */ |
| 57 | #define MVME5100_BASE_BAUD 1843200 |
| 58 | #define MVME5100_SERIAL_1 0xfef88000 |
| 59 | #define MVME5100_SERIAL_2 0xfef88200 |
| 60 | #ifdef CONFIG_MVME5100_IPMC761_PRESENT |
| 61 | #define MVME5100_SERIAL_IRQ 17 |
| 62 | #else |
| 63 | #define MVME5100_SERIAL_IRQ 1 |
| 64 | #endif |
| 65 | |
| 66 | #define RS_TABLE_SIZE 4 |
| 67 | |
| 68 | #define BASE_BAUD ( MVME5100_BASE_BAUD / 16 ) |
| 69 | |
| 70 | #define STD_COM_FLAGS ASYNC_BOOT_AUTOCONF |
| 71 | |
| 72 | /* All UART IRQ's are wire-OR'd to one MPIC IRQ */ |
| 73 | #define STD_SERIAL_PORT_DFNS \ |
| 74 | { 0, BASE_BAUD, MVME5100_SERIAL_1, \ |
| 75 | MVME5100_SERIAL_IRQ, \ |
| 76 | STD_COM_FLAGS, /* ttyS0 */ \ |
| 77 | iomem_base: (unsigned char *)MVME5100_SERIAL_1, \ |
| 78 | iomem_reg_shift: 4, \ |
| 79 | io_type: SERIAL_IO_MEM }, \ |
| 80 | { 0, BASE_BAUD, MVME5100_SERIAL_2, \ |
| 81 | MVME5100_SERIAL_IRQ, \ |
| 82 | STD_COM_FLAGS, /* ttyS1 */ \ |
| 83 | iomem_base: (unsigned char *)MVME5100_SERIAL_2, \ |
| 84 | iomem_reg_shift: 4, \ |
| 85 | io_type: SERIAL_IO_MEM }, |
| 86 | |
| 87 | #define SERIAL_PORT_DFNS \ |
| 88 | STD_SERIAL_PORT_DFNS |
| 89 | |
| 90 | #endif /* __ASM_MVME5100_H__ */ |
| 91 | #endif /* __KERNEL__ */ |