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gerrit-public.fairphone.software / kernel / msm / 66266f4ab8a049680cacf72ce792d967c12cd99a / . / arch / arm / mach-ep93xx / dma.c
blob: 5a2570881255ef7851ee73c8c9c06ce60b4090b7 [file] [log] [blame]
Mika Westerberge791e342011-05-29 13:10:03 +0300[diff] [blame]1/*
2 * arch/arm/mach-ep93xx/dma.c
3 *
4 * Platform support code for the EP93xx dmaengine driver.
5 *
6 * Copyright (C) 2011 Mika Westerberg
7 *
8 * This work is based on the original dma-m2p implementation with
9 * following copyrights:
10 *
11 * Copyright (C) 2006 Lennert Buytenhek <buytenh@wantstofly.org>
12 * Copyright (C) 2006 Applied Data Systems
13 * Copyright (C) 2009 Ryan Mallon <rmallon@gmail.com>
14 *
15 * This program is free software; you can redistribute it and/or modify
16 * it under the terms of the GNU General Public License as published by
17 * the Free Software Foundation; either version 2 of the License, or (at
18 * your option) any later version.
19 */
20
21#include <linux/dmaengine.h>
22#include <linux/dma-mapping.h>
23#include <linux/init.h>
24#include <linux/interrupt.h>
25#include <linux/kernel.h>
26#include <linux/platform_device.h>
27
28#include <mach/dma.h>
29#include <mach/hardware.h>
30
31#define DMA_CHANNEL(_name, _base, _irq) \
32 { .name = (_name), .base = (_base), .irq = (_irq) }
33
34/*
35 * DMA M2P channels.
36 *
37 * On the EP93xx chip the following peripherals my be allocated to the 10
38 * Memory to Internal Peripheral (M2P) channels (5 transmit + 5 receive).
39 *
40 * I2S contains 3 Tx and 3 Rx DMA Channels
41 * AAC contains 3 Tx and 3 Rx DMA Channels
42 * UART1 contains 1 Tx and 1 Rx DMA Channels
43 * UART2 contains 1 Tx and 1 Rx DMA Channels
44 * UART3 contains 1 Tx and 1 Rx DMA Channels
45 * IrDA contains 1 Tx and 1 Rx DMA Channels
46 *
47 * Registers are mapped statically in ep93xx_map_io().
48 */
49static struct ep93xx_dma_chan_data ep93xx_dma_m2p_channels[] = {
50 DMA_CHANNEL("m2p0", EP93XX_DMA_BASE + 0x0000, IRQ_EP93XX_DMAM2P0),
51 DMA_CHANNEL("m2p1", EP93XX_DMA_BASE + 0x0040, IRQ_EP93XX_DMAM2P1),
52 DMA_CHANNEL("m2p2", EP93XX_DMA_BASE + 0x0080, IRQ_EP93XX_DMAM2P2),
53 DMA_CHANNEL("m2p3", EP93XX_DMA_BASE + 0x00c0, IRQ_EP93XX_DMAM2P3),
54 DMA_CHANNEL("m2p4", EP93XX_DMA_BASE + 0x0240, IRQ_EP93XX_DMAM2P4),
55 DMA_CHANNEL("m2p5", EP93XX_DMA_BASE + 0x0200, IRQ_EP93XX_DMAM2P5),
56 DMA_CHANNEL("m2p6", EP93XX_DMA_BASE + 0x02c0, IRQ_EP93XX_DMAM2P6),
57 DMA_CHANNEL("m2p7", EP93XX_DMA_BASE + 0x0280, IRQ_EP93XX_DMAM2P7),
58 DMA_CHANNEL("m2p8", EP93XX_DMA_BASE + 0x0340, IRQ_EP93XX_DMAM2P8),
59 DMA_CHANNEL("m2p9", EP93XX_DMA_BASE + 0x0300, IRQ_EP93XX_DMAM2P9),
60};
61
62static struct ep93xx_dma_platform_data ep93xx_dma_m2p_data = {
63 .channels = ep93xx_dma_m2p_channels,
64 .num_channels = ARRAY_SIZE(ep93xx_dma_m2p_channels),
65};
66
67static struct platform_device ep93xx_dma_m2p_device = {
68 .name = "ep93xx-dma-m2p",
69 .id = -1,
70 .dev = {
71 .platform_data = &ep93xx_dma_m2p_data,
72 },
73};
74
75/*
76 * DMA M2M channels.
77 *
78 * There are 2 M2M channels which support memcpy/memset and in addition simple
79 * hardware requests from/to SSP and IDE. We do not implement an external
80 * hardware requests.
81 *
82 * Registers are mapped statically in ep93xx_map_io().
83 */
84static struct ep93xx_dma_chan_data ep93xx_dma_m2m_channels[] = {
85 DMA_CHANNEL("m2m0", EP93XX_DMA_BASE + 0x0100, IRQ_EP93XX_DMAM2M0),
86 DMA_CHANNEL("m2m1", EP93XX_DMA_BASE + 0x0140, IRQ_EP93XX_DMAM2M1),
87};
88
89static struct ep93xx_dma_platform_data ep93xx_dma_m2m_data = {
90 .channels = ep93xx_dma_m2m_channels,
91 .num_channels = ARRAY_SIZE(ep93xx_dma_m2m_channels),
92};
93
94static struct platform_device ep93xx_dma_m2m_device = {
95 .name = "ep93xx-dma-m2m",
96 .id = -1,
97 .dev = {
98 .platform_data = &ep93xx_dma_m2m_data,
99 },
100};
101
102static int __init ep93xx_dma_init(void)
103{
104 platform_device_register(&ep93xx_dma_m2p_device);
105 platform_device_register(&ep93xx_dma_m2m_device);
106 return 0;
107}
108arch_initcall(ep93xx_dma_init);