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gerrit-public.fairphone.software / kernel / msm / 66c72838c6abaf8a37ecd77c68a621e1fe06b47b / . / sound / soc / codecs / msm8x10-wcd.h
blob: d250e0ac9e1f2ac665b50048b2b1b191e915c88b [file] [log] [blame]
Kuirong Wang265f3592012-12-05 16:17:41 -0800[diff] [blame]1/* Copyright (c) 2013, The Linux Foundation. All rights reserved.
2 *
3 * This program is free software; you can redistribute it and/or modify
4 * it under the terms of the GNU General Public License version 2 and
5 * only version 2 as published by the Free Software Foundation.
6 *
7 * This program is distributed in the hope that it will be useful,
8 * but WITHOUT ANY WARRANTY; without even the implied warranty of
9 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
10 * GNU General Public License for more details.
11 */
12#ifndef MSM8X10_WCD_H
13#define MSM8X10_WCD_H
14
15#include <sound/soc.h>
16#include <sound/jack.h>
17#include "wcd9xxx-mbhc.h"
18#include "wcd9xxx-resmgr.h"
19
20#define MSM8X10_WCD_NUM_REGISTERS 0x600
21#define MSM8X10_WCD_MAX_REGISTER (MSM8X10_WCD_NUM_REGISTERS-1)
22#define MSM8X10_WCD_CACHE_SIZE MSM8X10_WCD_NUM_REGISTERS
23#define MSM8X10_WCD_NUM_IRQ_REGS 3
24#define MAX_REGULATOR 7
25#define MSM8X10_WCD_REG_VAL(reg, val) {reg, 0, val}
26
27#define MSM8X10_WCD_IS_DINO_REG(reg) \
28 (((reg >= 0x400) && (reg <= 0x5FF)) ? 1 : 0)
29#define MSM8X10_WCD_IS_HELICON_REG(reg) \
30 (((reg >= 0x000) && (reg <= 0x1FF)) ? 1 : 0)
31extern const u8 msm8x10_wcd_reg_readable[MSM8X10_WCD_CACHE_SIZE];
32extern const u8 msm8x10_wcd_reset_reg_defaults[MSM8X10_WCD_CACHE_SIZE];
33struct msm8x10_wcd_codec_dai_data {
34 u32 rate;
35 u32 *ch_num;
36 u32 ch_act;
37 u32 ch_tot;
38};
39
40enum msm8x10_wcd_pid_current {
41 MSM8X10_WCD_PID_MIC_2P5_UA,
42 MSM8X10_WCD_PID_MIC_5_UA,
43 MSM8X10_WCD_PID_MIC_10_UA,
44 MSM8X10_WCD_PID_MIC_20_UA,
45};
46
47struct msm8x10_wcd_reg_mask_val {
48 u16 reg;
49 u8 mask;
50 u8 val;
51};
52
53enum msm8x10_wcd_mbhc_analog_pwr_cfg {
54 MSM8X10_WCD_ANALOG_PWR_COLLAPSED = 0,
55 MSM8X10_WCD_ANALOG_PWR_ON,
56 MSM8X10_WCD_NUM_ANALOG_PWR_CONFIGS,
57};
58
59/* Number of input and output Slimbus port */
60enum {
61 MSM8X10_WCD_RX1 = 0,
62 MSM8X10_WCD_RX2,
63 MSM8X10_WCD_RX3,
64 MSM8X10_WCD_RX_MAX,
65};
66
67enum {
68 MSM8X10_WCD_TX1 = 0,
69 MSM8X10_WCD_TX2,
70 MSM8X10_WCD_TX3,
71 MSM8X10_WCD_TX4,
72 MSM8X10_WCD_TX_MAX,
73};
74
75enum {
76 /* INTR_REG 0 */
77 MSM8X10_WCD_IRQ_RESERVED_0 = 0,
78 MSM8X10_WCD_IRQ_MBHC_REMOVAL,
79 MSM8X10_WCD_IRQ_MBHC_SHORT_TERM,
80 MSM8X10_WCD_IRQ_MBHC_PRESS,
81 MSM8X10_WCD_IRQ_MBHC_RELEASE,
82 MSM8X10_WCD_IRQ_MBHC_POTENTIAL,
83 MSM8X10_WCD_IRQ_MBHC_INSERTION,
84 MSM8X10_WCD_IRQ_MBHC_HS_DET,
85 /* INTR_REG 1 */
86 MSM8X10_WCD_IRQ_PA_STARTUP,
87 MSM8X10_WCD_IRQ_BG_PRECHARGE,
88 MSM8X10_WCD_IRQ_RESERVED_1,
89 MSM8X10_WCD_IRQ_EAR_PA_OCPL_FAULT,
90 MSM8X10_WCD_IRQ_EAR_PA_STARTUP,
91 MSM8X10_WCD_IRQ_SPKR_PA_OCPL_FAULT,
92 MSM8X10_WCD_IRQ_SPKR_CLIP_FAULT,
93 MSM8X10_WCD_IRQ_RESERVED_2,
94 /* INTR_REG 2 */
95 MSM8X10_WCD_IRQ_HPH_L_PA_STARTUP,
96 MSM8X10_WCD_IRQ_HPH_R_PA_STARTUP,
97 MSM8X10_WCD_IRQ_HPH_PA_OCPL_FAULT,
98 MSM8X10_WCD_IRQ_HPH_PA_OCPR_FAULT,
99 MSM8X10_WCD_IRQ_RESERVED_3,
100 MSM8X10_WCD_IRQ_RESERVED_4,
101 MSM8X10_WCD_IRQ_RESERVED_5,
102 MSM8X10_WCD_IRQ_RESERVED_6,
103 MSM8X10_WCD_NUM_IRQS,
104};
105
106/*
107 * Each micbias can be assigned to one of three cfilters
108 * Vbatt_min >= .15V + ldoh_v
109 * ldoh_v >= .15v + cfiltx_mv
110 * If ldoh_v = 1.95 160 mv < cfiltx_mv < 1800 mv
111 * If ldoh_v = 2.35 200 mv < cfiltx_mv < 2200 mv
112 * If ldoh_v = 2.75 240 mv < cfiltx_mv < 2600 mv
113 * If ldoh_v = 2.85 250 mv < cfiltx_mv < 2700 mv
114 */
115struct msm8x10_wcd_micbias_setting {
116 u8 ldoh_v;
117 u32 cfilt1_mv; /* in mv */
118 /*
119 * Different WCD9xxx series codecs may not
120 * have 4 mic biases. If a codec has fewer
121 * mic biases, some of these properties will
122 * not be used.
123 */
124 u8 bias1_cfilt_sel;
125 u8 bias1_cap_mode;
126};
127
128struct msm8x10_wcd_ocp_setting {
129 unsigned int use_pdata:1; /* 0 - use sys default as recommended */
130 unsigned int num_attempts:4; /* up to 15 attempts */
131 unsigned int run_time:4; /* in duty cycle */
132 unsigned int wait_time:4; /* in duty cycle */
133 unsigned int hph_ocp_limit:3; /* Headphone OCP current limit */
134};
135
136struct msm8x10_wcd_regulator {
137 const char *name;
138 int min_uV;
139 int max_uV;
140 int optimum_uA;
141 struct regulator *regulator;
142};
143
144struct msm8x10_wcd_pdata {
145 int irq;
146 int irq_base;
147 int num_irqs;
148 int reset_gpio;
149 void *msm8x10_wcd_ahb_base_vaddr;
150 struct msm8x10_wcd_micbias_setting micbias;
151 struct msm8x10_wcd_ocp_setting ocp;
152 struct msm8x10_wcd_regulator regulator[MAX_REGULATOR];
153 u32 mclk_rate;
154};
155
156enum msm8x10_wcd_micbias_num {
157 MSM8X10_WCD_MICBIAS1 = 0,
158};
159
160struct msm8x10_wcd_mbhc_config {
161 struct snd_soc_jack *headset_jack;
162 struct snd_soc_jack *button_jack;
163 bool read_fw_bin;
164 /*
165 * void* calibration contains:
166 * struct msm8x10_wcd_mbhc_general_cfg generic;
167 * struct msm8x10_wcd_mbhc_plug_detect_cfg plug_det;
168 * struct msm8x10_wcd_mbhc_plug_type_cfg plug_type;
169 * struct msm8x10_wcd_mbhc_btn_detect_cfg btn_det;
170 * struct msm8x10_wcd_mbhc_imped_detect_cfg imped_det;
171 * Note: various size depends on btn_det->num_btn
172 */
173 void *calibration;
174 enum msm8x10_wcd_micbias_num micbias;
175 int (*mclk_cb_fn) (struct snd_soc_codec*, int, bool);
176 unsigned int mclk_rate;
177 unsigned int gpio;
178 unsigned int gpio_irq;
179 int gpio_level_insert;
180 bool detect_extn_cable;
181 /* swap_gnd_mic returns true if extern GND/MIC swap switch toggled */
182 bool (*swap_gnd_mic) (struct snd_soc_codec *);
183};
184
185enum msm8x10_wcd_pm_state {
186 MSM8X10_WCD_PM_SLEEPABLE,
187 MSM8X10_WCD_PM_AWAKE,
188 MSM8X10_WCD_PM_ASLEEP,
189};
190
191struct msm8x10_wcd {
192 struct device *dev;
193 struct mutex io_lock;
194 struct mutex xfer_lock;
195 struct mutex irq_lock;
196 u8 version;
197
198 int reset_gpio;
Kuirong Wang3a6408d2013-02-20 17:46:46 -0800[diff] [blame]199 int (*read_dev)(struct msm8x10_wcd *msm8x10,
200 unsigned short reg, unsigned int *val);
201 int (*write_dev)(struct msm8x10_wcd *msm8x10,
Kuirong Wang91e52532013-03-31 14:24:22 -0700[diff] [blame]202 unsigned short reg, u8 val);
Kuirong Wang265f3592012-12-05 16:17:41 -0800[diff] [blame]203
204 u32 num_of_supplies;
205 struct regulator_bulk_data *supplies;
206
207 enum msm8x10_wcd_pm_state pm_state;
208 struct mutex pm_lock;
209 /* pm_wq notifies change of pm_state */
210 wait_queue_head_t pm_wq;
211 struct pm_qos_request pm_qos_req;
212 int wlock_holders;
213
214 u8 idbyte[4];
215
216 unsigned int irq_base;
217 unsigned int irq;
218 u8 irq_masks_cur[MSM8X10_WCD_NUM_IRQ_REGS];
219 u8 irq_masks_cache[MSM8X10_WCD_NUM_IRQ_REGS];
220 bool irq_level_high[MSM8X10_WCD_NUM_IRQS];
221 int num_irqs;
222 u32 mclk_rate;
223};
224
225extern int msm8x10_wcd_mclk_enable(struct snd_soc_codec *codec, int mclk_enable,
226 bool dapm);
227extern int msm8x10_wcd_hs_detect(struct snd_soc_codec *codec,
228 struct msm8x10_wcd_mbhc_config *mbhc_cfg);
229
230#endif