Magnus Damm | b2623a6 | 2010-03-19 04:47:10 +0000 | [diff] [blame] | 1 | /* |
| 2 | * Header for the new SH dmaengine driver |
| 3 | * |
| 4 | * Copyright (C) 2010 Guennadi Liakhovetski <g.liakhovetski@gmx.de> |
| 5 | * |
| 6 | * This program is free software; you can redistribute it and/or modify |
| 7 | * it under the terms of the GNU General Public License version 2 as |
| 8 | * published by the Free Software Foundation. |
| 9 | */ |
| 10 | #ifndef SH_DMA_H |
| 11 | #define SH_DMA_H |
| 12 | |
| 13 | #include <linux/list.h> |
| 14 | #include <linux/dmaengine.h> |
| 15 | |
| 16 | /* Used by slave DMA clients to request DMA to/from a specific peripheral */ |
| 17 | struct sh_dmae_slave { |
| 18 | unsigned int slave_id; /* Set by the platform */ |
| 19 | struct device *dma_dev; /* Set by the platform */ |
Guennadi Liakhovetski | 5bac942 | 2010-04-21 15:36:49 +0000 | [diff] [blame] | 20 | const struct sh_dmae_slave_config *config; /* Set by the driver */ |
Magnus Damm | b2623a6 | 2010-03-19 04:47:10 +0000 | [diff] [blame] | 21 | }; |
| 22 | |
| 23 | struct sh_dmae_regs { |
| 24 | u32 sar; /* SAR / source address */ |
| 25 | u32 dar; /* DAR / destination address */ |
| 26 | u32 tcr; /* TCR / transfer count */ |
| 27 | }; |
| 28 | |
| 29 | struct sh_desc { |
| 30 | struct sh_dmae_regs hw; |
| 31 | struct list_head node; |
| 32 | struct dma_async_tx_descriptor async_tx; |
| 33 | enum dma_data_direction direction; |
| 34 | dma_cookie_t cookie; |
| 35 | size_t partial; |
| 36 | int chunks; |
| 37 | int mark; |
| 38 | }; |
Guennadi Liakhovetski | 5bac942 | 2010-04-21 15:36:49 +0000 | [diff] [blame] | 39 | |
Magnus Damm | b2623a6 | 2010-03-19 04:47:10 +0000 | [diff] [blame] | 40 | struct sh_dmae_slave_config { |
| 41 | unsigned int slave_id; |
| 42 | dma_addr_t addr; |
| 43 | u32 chcr; |
| 44 | char mid_rid; |
| 45 | }; |
| 46 | |
| 47 | struct sh_dmae_channel { |
| 48 | unsigned int offset; |
| 49 | unsigned int dmars; |
| 50 | unsigned int dmars_bit; |
| 51 | }; |
| 52 | |
| 53 | struct sh_dmae_pdata { |
Guennadi Liakhovetski | 5bac942 | 2010-04-21 15:36:49 +0000 | [diff] [blame] | 54 | const struct sh_dmae_slave_config *slave; |
Magnus Damm | b2623a6 | 2010-03-19 04:47:10 +0000 | [diff] [blame] | 55 | int slave_num; |
Guennadi Liakhovetski | 5bac942 | 2010-04-21 15:36:49 +0000 | [diff] [blame] | 56 | const struct sh_dmae_channel *channel; |
Magnus Damm | b2623a6 | 2010-03-19 04:47:10 +0000 | [diff] [blame] | 57 | int channel_num; |
| 58 | unsigned int ts_low_shift; |
| 59 | unsigned int ts_low_mask; |
| 60 | unsigned int ts_high_shift; |
| 61 | unsigned int ts_high_mask; |
Guennadi Liakhovetski | 5bac942 | 2010-04-21 15:36:49 +0000 | [diff] [blame] | 62 | const unsigned int *ts_shift; |
Magnus Damm | b2623a6 | 2010-03-19 04:47:10 +0000 | [diff] [blame] | 63 | int ts_shift_num; |
| 64 | u16 dmaor_init; |
Kuninori Morimoto | 5899a72 | 2011-06-17 08:20:40 +0000 | [diff] [blame] | 65 | unsigned int chcr_offset; |
Kuninori Morimoto | 67c6269 | 2011-06-17 08:20:51 +0000 | [diff] [blame^] | 66 | u32 chcr_ie_bit; |
Magnus Damm | b2623a6 | 2010-03-19 04:47:10 +0000 | [diff] [blame] | 67 | }; |
| 68 | |
| 69 | /* DMA register */ |
| 70 | #define SAR 0x00 |
| 71 | #define DAR 0x04 |
| 72 | #define TCR 0x08 |
| 73 | #define CHCR 0x0C |
| 74 | #define DMAOR 0x40 |
| 75 | |
| 76 | /* DMAOR definitions */ |
| 77 | #define DMAOR_AE 0x00000004 |
| 78 | #define DMAOR_NMIF 0x00000002 |
| 79 | #define DMAOR_DME 0x00000001 |
| 80 | |
| 81 | /* Definitions for the SuperH DMAC */ |
| 82 | #define REQ_L 0x00000000 |
| 83 | #define REQ_E 0x00080000 |
| 84 | #define RACK_H 0x00000000 |
| 85 | #define RACK_L 0x00040000 |
| 86 | #define ACK_R 0x00000000 |
| 87 | #define ACK_W 0x00020000 |
| 88 | #define ACK_H 0x00000000 |
| 89 | #define ACK_L 0x00010000 |
| 90 | #define DM_INC 0x00004000 |
| 91 | #define DM_DEC 0x00008000 |
| 92 | #define DM_FIX 0x0000c000 |
| 93 | #define SM_INC 0x00001000 |
| 94 | #define SM_DEC 0x00002000 |
| 95 | #define SM_FIX 0x00003000 |
| 96 | #define RS_IN 0x00000200 |
| 97 | #define RS_OUT 0x00000300 |
| 98 | #define TS_BLK 0x00000040 |
| 99 | #define TM_BUR 0x00000020 |
| 100 | #define CHCR_DE 0x00000001 |
| 101 | #define CHCR_TE 0x00000002 |
| 102 | #define CHCR_IE 0x00000004 |
| 103 | |
| 104 | #endif |