Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1 | #ifndef __ASM_ARM_SYSTEM_H |
| 2 | #define __ASM_ARM_SYSTEM_H |
| 3 | |
| 4 | #ifdef __KERNEL__ |
| 5 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 6 | |
| 7 | #define CPU_ARCH_UNKNOWN 0 |
| 8 | #define CPU_ARCH_ARMv3 1 |
| 9 | #define CPU_ARCH_ARMv4 2 |
| 10 | #define CPU_ARCH_ARMv4T 3 |
| 11 | #define CPU_ARCH_ARMv5 4 |
| 12 | #define CPU_ARCH_ARMv5T 5 |
| 13 | #define CPU_ARCH_ARMv5TE 6 |
| 14 | #define CPU_ARCH_ARMv5TEJ 7 |
| 15 | #define CPU_ARCH_ARMv6 8 |
| 16 | |
| 17 | /* |
| 18 | * CR1 bits (CP#15 CR1) |
| 19 | */ |
| 20 | #define CR_M (1 << 0) /* MMU enable */ |
| 21 | #define CR_A (1 << 1) /* Alignment abort enable */ |
| 22 | #define CR_C (1 << 2) /* Dcache enable */ |
| 23 | #define CR_W (1 << 3) /* Write buffer enable */ |
| 24 | #define CR_P (1 << 4) /* 32-bit exception handler */ |
| 25 | #define CR_D (1 << 5) /* 32-bit data address range */ |
| 26 | #define CR_L (1 << 6) /* Implementation defined */ |
| 27 | #define CR_B (1 << 7) /* Big endian */ |
| 28 | #define CR_S (1 << 8) /* System MMU protection */ |
| 29 | #define CR_R (1 << 9) /* ROM MMU protection */ |
| 30 | #define CR_F (1 << 10) /* Implementation defined */ |
| 31 | #define CR_Z (1 << 11) /* Implementation defined */ |
| 32 | #define CR_I (1 << 12) /* Icache enable */ |
| 33 | #define CR_V (1 << 13) /* Vectors relocated to 0xffff0000 */ |
| 34 | #define CR_RR (1 << 14) /* Round Robin cache replacement */ |
| 35 | #define CR_L4 (1 << 15) /* LDR pc can set T bit */ |
| 36 | #define CR_DT (1 << 16) |
| 37 | #define CR_IT (1 << 18) |
| 38 | #define CR_ST (1 << 19) |
| 39 | #define CR_FI (1 << 21) /* Fast interrupt (lower latency mode) */ |
| 40 | #define CR_U (1 << 22) /* Unaligned access operation */ |
| 41 | #define CR_XP (1 << 23) /* Extended page tables */ |
| 42 | #define CR_VE (1 << 24) /* Vectored interrupts */ |
| 43 | |
| 44 | #define CPUID_ID 0 |
| 45 | #define CPUID_CACHETYPE 1 |
| 46 | #define CPUID_TCM 2 |
| 47 | #define CPUID_TLBTYPE 3 |
| 48 | |
| 49 | #define read_cpuid(reg) \ |
| 50 | ({ \ |
| 51 | unsigned int __val; \ |
| 52 | asm("mrc p15, 0, %0, c0, c0, " __stringify(reg) \ |
| 53 | : "=r" (__val) \ |
| 54 | : \ |
| 55 | : "cc"); \ |
| 56 | __val; \ |
| 57 | }) |
| 58 | |
| 59 | /* |
| 60 | * This is used to ensure the compiler did actually allocate the register we |
| 61 | * asked it for some inline assembly sequences. Apparently we can't trust |
| 62 | * the compiler from one version to another so a bit of paranoia won't hurt. |
| 63 | * This string is meant to be concatenated with the inline asm string and |
| 64 | * will cause compilation to stop on mismatch. |
| 65 | * (for details, see gcc PR 15089) |
| 66 | */ |
| 67 | #define __asmeq(x, y) ".ifnc " x "," y " ; .err ; .endif\n\t" |
| 68 | |
| 69 | #ifndef __ASSEMBLY__ |
| 70 | |
| 71 | #include <linux/linkage.h> |
| 72 | |
| 73 | struct thread_info; |
| 74 | struct task_struct; |
| 75 | |
| 76 | /* information about the system we're running on */ |
| 77 | extern unsigned int system_rev; |
| 78 | extern unsigned int system_serial_low; |
| 79 | extern unsigned int system_serial_high; |
| 80 | extern unsigned int mem_fclk_21285; |
| 81 | |
| 82 | struct pt_regs; |
| 83 | |
| 84 | void die(const char *msg, struct pt_regs *regs, int err) |
| 85 | __attribute__((noreturn)); |
| 86 | |
Russell King | cfb0810 | 2005-06-30 11:06:49 +0100 | [diff] [blame] | 87 | struct siginfo; |
| 88 | void notify_die(const char *str, struct pt_regs *regs, struct siginfo *info, |
| 89 | unsigned long err, unsigned long trap); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 90 | |
| 91 | void hook_fault_code(int nr, int (*fn)(unsigned long, unsigned int, |
| 92 | struct pt_regs *), |
| 93 | int sig, const char *name); |
| 94 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 95 | #define xchg(ptr,x) \ |
| 96 | ((__typeof__(*(ptr)))__xchg((unsigned long)(x),(ptr),sizeof(*(ptr)))) |
| 97 | |
| 98 | #define tas(ptr) (xchg((ptr),1)) |
| 99 | |
| 100 | extern asmlinkage void __backtrace(void); |
Russell King | 652a12e | 2005-04-17 15:50:36 +0100 | [diff] [blame] | 101 | extern asmlinkage void c_backtrace(unsigned long fp, int pmode); |
Russell King | 5470dc6 | 2005-11-16 18:36:49 +0000 | [diff] [blame] | 102 | |
| 103 | struct mm_struct; |
Russell King | 652a12e | 2005-04-17 15:50:36 +0100 | [diff] [blame] | 104 | extern void show_pte(struct mm_struct *mm, unsigned long addr); |
| 105 | extern void __show_regs(struct pt_regs *); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 106 | |
| 107 | extern int cpu_architecture(void); |
Russell King | 36c5ed2 | 2005-06-19 18:39:33 +0100 | [diff] [blame] | 108 | extern void cpu_init(void); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 109 | |
Richard Purdie | 74617fb | 2006-06-19 19:57:12 +0100 | [diff] [blame] | 110 | void arm_machine_restart(char mode); |
| 111 | extern void (*arm_pm_restart)(char str); |
| 112 | |
Lennert Buytenhek | 23bdf86 | 2006-03-28 21:00:40 +0100 | [diff] [blame] | 113 | /* |
| 114 | * Intel's XScale3 core supports some v6 features (supersections, L2) |
| 115 | * but advertises itself as v5 as it does not support the v6 ISA. For |
| 116 | * this reason, we need a way to explicitly test for this type of CPU. |
| 117 | */ |
| 118 | #ifndef CONFIG_CPU_XSC3 |
| 119 | #define cpu_is_xsc3() 0 |
| 120 | #else |
| 121 | static inline int cpu_is_xsc3(void) |
| 122 | { |
| 123 | extern unsigned int processor_id; |
| 124 | |
| 125 | if ((processor_id & 0xffffe000) == 0x69056000) |
| 126 | return 1; |
| 127 | |
| 128 | return 0; |
| 129 | } |
| 130 | #endif |
| 131 | |
Deepak Saxena | 5cedae9 | 2006-05-31 16:14:05 -0700 | [diff] [blame] | 132 | #if !defined(CONFIG_CPU_XSCALE) && !defined(CONFIG_CPU_XSC3) |
| 133 | #define cpu_is_xscale() 0 |
| 134 | #else |
| 135 | #define cpu_is_xscale() 1 |
| 136 | #endif |
| 137 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 138 | #define set_cr(x) \ |
| 139 | __asm__ __volatile__( \ |
| 140 | "mcr p15, 0, %0, c1, c0, 0 @ set CR" \ |
| 141 | : : "r" (x) : "cc") |
| 142 | |
| 143 | #define get_cr() \ |
| 144 | ({ \ |
| 145 | unsigned int __val; \ |
| 146 | __asm__ __volatile__( \ |
| 147 | "mrc p15, 0, %0, c1, c0, 0 @ get CR" \ |
| 148 | : "=r" (__val) : : "cc"); \ |
| 149 | __val; \ |
| 150 | }) |
| 151 | |
| 152 | extern unsigned long cr_no_alignment; /* defined in entry-armv.S */ |
| 153 | extern unsigned long cr_alignment; /* defined in entry-armv.S */ |
| 154 | |
| 155 | #define UDBG_UNDEFINED (1 << 0) |
| 156 | #define UDBG_SYSCALL (1 << 1) |
| 157 | #define UDBG_BADABORT (1 << 2) |
| 158 | #define UDBG_SEGV (1 << 3) |
| 159 | #define UDBG_BUS (1 << 4) |
| 160 | |
| 161 | extern unsigned int user_debug; |
| 162 | |
| 163 | #if __LINUX_ARM_ARCH__ >= 4 |
| 164 | #define vectors_high() (cr_alignment & CR_V) |
| 165 | #else |
| 166 | #define vectors_high() (0) |
| 167 | #endif |
| 168 | |
Russell King | 6d9b37a | 2005-07-26 19:44:26 +0100 | [diff] [blame] | 169 | #if __LINUX_ARM_ARCH__ >= 6 |
| 170 | #define mb() __asm__ __volatile__ ("mcr p15, 0, %0, c7, c10, 5" \ |
| 171 | : : "r" (0) : "memory") |
| 172 | #else |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 173 | #define mb() __asm__ __volatile__ ("" : : : "memory") |
Russell King | 6d9b37a | 2005-07-26 19:44:26 +0100 | [diff] [blame] | 174 | #endif |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 175 | #define rmb() mb() |
| 176 | #define wmb() mb() |
| 177 | #define read_barrier_depends() do { } while(0) |
| 178 | #define set_mb(var, value) do { var = value; mb(); } while (0) |
| 179 | #define set_wmb(var, value) do { var = value; wmb(); } while (0) |
| 180 | #define nop() __asm__ __volatile__("mov\tr0,r0\t@ nop\n\t"); |
| 181 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 182 | /* |
Nick Piggin | 4866cde | 2005-06-25 14:57:23 -0700 | [diff] [blame] | 183 | * switch_mm() may do a full cache flush over the context switch, |
| 184 | * so enable interrupts over the context switch to avoid high |
| 185 | * latency. |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 186 | */ |
Nick Piggin | 4866cde | 2005-06-25 14:57:23 -0700 | [diff] [blame] | 187 | #define __ARCH_WANT_INTERRUPTS_ON_CTXSW |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 188 | |
| 189 | /* |
| 190 | * switch_to(prev, next) should switch from task `prev' to `next' |
| 191 | * `prev' will never be the same as `next'. schedule() itself |
| 192 | * contains the memory barrier to tell GCC not to cache `current'. |
| 193 | */ |
| 194 | extern struct task_struct *__switch_to(struct task_struct *, struct thread_info *, struct thread_info *); |
| 195 | |
| 196 | #define switch_to(prev,next,last) \ |
| 197 | do { \ |
Al Viro | e7c1b32 | 2006-01-12 01:05:56 -0800 | [diff] [blame] | 198 | last = __switch_to(prev,task_thread_info(prev), task_thread_info(next)); \ |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 199 | } while (0) |
| 200 | |
| 201 | /* |
Ingo Molnar | 4dc7a0b | 2006-01-12 01:05:27 -0800 | [diff] [blame] | 202 | * On SMP systems, when the scheduler does migration-cost autodetection, |
| 203 | * it needs a way to flush as much of the CPU's caches as possible. |
| 204 | * |
| 205 | * TODO: fill this in! |
| 206 | */ |
| 207 | static inline void sched_cacheflush(void) |
| 208 | { |
| 209 | } |
| 210 | |
| 211 | /* |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 212 | * CPU interrupt mask handling. |
| 213 | */ |
| 214 | #if __LINUX_ARM_ARCH__ >= 6 |
| 215 | |
| 216 | #define local_irq_save(x) \ |
| 217 | ({ \ |
| 218 | __asm__ __volatile__( \ |
| 219 | "mrs %0, cpsr @ local_irq_save\n" \ |
| 220 | "cpsid i" \ |
| 221 | : "=r" (x) : : "memory", "cc"); \ |
| 222 | }) |
| 223 | |
| 224 | #define local_irq_enable() __asm__("cpsie i @ __sti" : : : "memory", "cc") |
| 225 | #define local_irq_disable() __asm__("cpsid i @ __cli" : : : "memory", "cc") |
| 226 | #define local_fiq_enable() __asm__("cpsie f @ __stf" : : : "memory", "cc") |
| 227 | #define local_fiq_disable() __asm__("cpsid f @ __clf" : : : "memory", "cc") |
| 228 | |
| 229 | #else |
| 230 | |
| 231 | /* |
| 232 | * Save the current interrupt enable state & disable IRQs |
| 233 | */ |
| 234 | #define local_irq_save(x) \ |
| 235 | ({ \ |
| 236 | unsigned long temp; \ |
| 237 | (void) (&temp == &x); \ |
| 238 | __asm__ __volatile__( \ |
| 239 | "mrs %0, cpsr @ local_irq_save\n" \ |
| 240 | " orr %1, %0, #128\n" \ |
| 241 | " msr cpsr_c, %1" \ |
| 242 | : "=r" (x), "=r" (temp) \ |
| 243 | : \ |
| 244 | : "memory", "cc"); \ |
| 245 | }) |
| 246 | |
| 247 | /* |
| 248 | * Enable IRQs |
| 249 | */ |
| 250 | #define local_irq_enable() \ |
| 251 | ({ \ |
| 252 | unsigned long temp; \ |
| 253 | __asm__ __volatile__( \ |
| 254 | "mrs %0, cpsr @ local_irq_enable\n" \ |
| 255 | " bic %0, %0, #128\n" \ |
| 256 | " msr cpsr_c, %0" \ |
| 257 | : "=r" (temp) \ |
| 258 | : \ |
| 259 | : "memory", "cc"); \ |
| 260 | }) |
| 261 | |
| 262 | /* |
| 263 | * Disable IRQs |
| 264 | */ |
| 265 | #define local_irq_disable() \ |
| 266 | ({ \ |
| 267 | unsigned long temp; \ |
| 268 | __asm__ __volatile__( \ |
| 269 | "mrs %0, cpsr @ local_irq_disable\n" \ |
| 270 | " orr %0, %0, #128\n" \ |
| 271 | " msr cpsr_c, %0" \ |
| 272 | : "=r" (temp) \ |
| 273 | : \ |
| 274 | : "memory", "cc"); \ |
| 275 | }) |
| 276 | |
| 277 | /* |
| 278 | * Enable FIQs |
| 279 | */ |
| 280 | #define local_fiq_enable() \ |
| 281 | ({ \ |
| 282 | unsigned long temp; \ |
| 283 | __asm__ __volatile__( \ |
| 284 | "mrs %0, cpsr @ stf\n" \ |
| 285 | " bic %0, %0, #64\n" \ |
| 286 | " msr cpsr_c, %0" \ |
| 287 | : "=r" (temp) \ |
| 288 | : \ |
| 289 | : "memory", "cc"); \ |
| 290 | }) |
| 291 | |
| 292 | /* |
| 293 | * Disable FIQs |
| 294 | */ |
| 295 | #define local_fiq_disable() \ |
| 296 | ({ \ |
| 297 | unsigned long temp; \ |
| 298 | __asm__ __volatile__( \ |
| 299 | "mrs %0, cpsr @ clf\n" \ |
| 300 | " orr %0, %0, #64\n" \ |
| 301 | " msr cpsr_c, %0" \ |
| 302 | : "=r" (temp) \ |
| 303 | : \ |
| 304 | : "memory", "cc"); \ |
| 305 | }) |
| 306 | |
| 307 | #endif |
| 308 | |
| 309 | /* |
| 310 | * Save the current interrupt enable state. |
| 311 | */ |
| 312 | #define local_save_flags(x) \ |
| 313 | ({ \ |
| 314 | __asm__ __volatile__( \ |
| 315 | "mrs %0, cpsr @ local_save_flags" \ |
| 316 | : "=r" (x) : : "memory", "cc"); \ |
| 317 | }) |
| 318 | |
| 319 | /* |
| 320 | * restore saved IRQ & FIQ state |
| 321 | */ |
| 322 | #define local_irq_restore(x) \ |
| 323 | __asm__ __volatile__( \ |
| 324 | "msr cpsr_c, %0 @ local_irq_restore\n" \ |
| 325 | : \ |
| 326 | : "r" (x) \ |
| 327 | : "memory", "cc") |
| 328 | |
| 329 | #define irqs_disabled() \ |
| 330 | ({ \ |
| 331 | unsigned long flags; \ |
| 332 | local_save_flags(flags); \ |
Andrew Morton | 9a558cb | 2005-06-21 17:14:28 -0700 | [diff] [blame] | 333 | (int)(flags & PSR_I_BIT); \ |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 334 | }) |
| 335 | |
| 336 | #ifdef CONFIG_SMP |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 337 | |
| 338 | #define smp_mb() mb() |
| 339 | #define smp_rmb() rmb() |
| 340 | #define smp_wmb() wmb() |
| 341 | #define smp_read_barrier_depends() read_barrier_depends() |
| 342 | |
| 343 | #else |
| 344 | |
| 345 | #define smp_mb() barrier() |
| 346 | #define smp_rmb() barrier() |
| 347 | #define smp_wmb() barrier() |
| 348 | #define smp_read_barrier_depends() do { } while(0) |
| 349 | |
Russell King | 053a7b5 | 2005-06-28 19:22:25 +0100 | [diff] [blame] | 350 | #endif /* CONFIG_SMP */ |
| 351 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 352 | #if defined(CONFIG_CPU_SA1100) || defined(CONFIG_CPU_SA110) |
| 353 | /* |
| 354 | * On the StrongARM, "swp" is terminally broken since it bypasses the |
| 355 | * cache totally. This means that the cache becomes inconsistent, and, |
| 356 | * since we use normal loads/stores as well, this is really bad. |
| 357 | * Typically, this causes oopsen in filp_close, but could have other, |
| 358 | * more disasterous effects. There are two work-arounds: |
| 359 | * 1. Disable interrupts and emulate the atomic swap |
| 360 | * 2. Clean the cache, perform atomic swap, flush the cache |
| 361 | * |
| 362 | * We choose (1) since its the "easiest" to achieve here and is not |
| 363 | * dependent on the processor type. |
Russell King | 053a7b5 | 2005-06-28 19:22:25 +0100 | [diff] [blame] | 364 | * |
| 365 | * NOTE that this solution won't work on an SMP system, so explcitly |
| 366 | * forbid it here. |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 367 | */ |
| 368 | #define swp_is_buggy |
| 369 | #endif |
| 370 | |
| 371 | static inline unsigned long __xchg(unsigned long x, volatile void *ptr, int size) |
| 372 | { |
| 373 | extern void __bad_xchg(volatile void *, int); |
| 374 | unsigned long ret; |
| 375 | #ifdef swp_is_buggy |
| 376 | unsigned long flags; |
| 377 | #endif |
Russell King | 9560782 | 2005-07-26 19:39:31 +0100 | [diff] [blame] | 378 | #if __LINUX_ARM_ARCH__ >= 6 |
| 379 | unsigned int tmp; |
| 380 | #endif |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 381 | |
| 382 | switch (size) { |
Russell King | 9560782 | 2005-07-26 19:39:31 +0100 | [diff] [blame] | 383 | #if __LINUX_ARM_ARCH__ >= 6 |
| 384 | case 1: |
| 385 | asm volatile("@ __xchg1\n" |
| 386 | "1: ldrexb %0, [%3]\n" |
| 387 | " strexb %1, %2, [%3]\n" |
| 388 | " teq %1, #0\n" |
| 389 | " bne 1b" |
| 390 | : "=&r" (ret), "=&r" (tmp) |
| 391 | : "r" (x), "r" (ptr) |
| 392 | : "memory", "cc"); |
| 393 | break; |
| 394 | case 4: |
| 395 | asm volatile("@ __xchg4\n" |
| 396 | "1: ldrex %0, [%3]\n" |
| 397 | " strex %1, %2, [%3]\n" |
| 398 | " teq %1, #0\n" |
| 399 | " bne 1b" |
| 400 | : "=&r" (ret), "=&r" (tmp) |
| 401 | : "r" (x), "r" (ptr) |
| 402 | : "memory", "cc"); |
| 403 | break; |
| 404 | #elif defined(swp_is_buggy) |
| 405 | #ifdef CONFIG_SMP |
| 406 | #error SMP is not supported on this platform |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 407 | #endif |
Russell King | 9560782 | 2005-07-26 19:39:31 +0100 | [diff] [blame] | 408 | case 1: |
| 409 | local_irq_save(flags); |
| 410 | ret = *(volatile unsigned char *)ptr; |
| 411 | *(volatile unsigned char *)ptr = x; |
| 412 | local_irq_restore(flags); |
| 413 | break; |
| 414 | |
| 415 | case 4: |
| 416 | local_irq_save(flags); |
| 417 | ret = *(volatile unsigned long *)ptr; |
| 418 | *(volatile unsigned long *)ptr = x; |
| 419 | local_irq_restore(flags); |
| 420 | break; |
| 421 | #else |
| 422 | case 1: |
| 423 | asm volatile("@ __xchg1\n" |
| 424 | " swpb %0, %1, [%2]" |
| 425 | : "=&r" (ret) |
| 426 | : "r" (x), "r" (ptr) |
| 427 | : "memory", "cc"); |
| 428 | break; |
| 429 | case 4: |
| 430 | asm volatile("@ __xchg4\n" |
| 431 | " swp %0, %1, [%2]" |
| 432 | : "=&r" (ret) |
| 433 | : "r" (x), "r" (ptr) |
| 434 | : "memory", "cc"); |
| 435 | break; |
| 436 | #endif |
| 437 | default: |
| 438 | __bad_xchg(ptr, size), ret = 0; |
| 439 | break; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 440 | } |
| 441 | |
| 442 | return ret; |
| 443 | } |
| 444 | |
Ben Dooks | dabaeff | 2006-03-15 23:17:26 +0000 | [diff] [blame] | 445 | extern void disable_hlt(void); |
| 446 | extern void enable_hlt(void); |
| 447 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 448 | #endif /* __ASSEMBLY__ */ |
| 449 | |
| 450 | #define arch_align_stack(x) (x) |
| 451 | |
| 452 | #endif /* __KERNEL__ */ |
| 453 | |
| 454 | #endif |