Duy Truong | 790f06d | 2013-02-13 16:38:12 -0800 | [diff] [blame] | 1 | /* Copyright (c) 2010-2011, The Linux Foundation. All rights reserved. |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 2 | * |
| 3 | * This program is free software; you can redistribute it and/or modify |
| 4 | * it under the terms of the GNU General Public License version 2 and |
| 5 | * only version 2 as published by the Free Software Foundation. |
| 6 | * |
| 7 | * This program is distributed in the hope that it will be useful, |
| 8 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 9 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 10 | * GNU General Public License for more details. |
| 11 | */ |
| 12 | |
| 13 | #include <linux/err.h> |
| 14 | #include <linux/string.h> |
| 15 | #include <linux/kernel.h> |
| 16 | #include <linux/init.h> |
| 17 | #include <linux/mfd/pmic8901.h> |
| 18 | #include <linux/regulator/driver.h> |
Anirudh Ghayal | 9f77e96 | 2011-12-06 12:38:21 +0530 | [diff] [blame] | 19 | #include <linux/mfd/pm8xxx/core.h> |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 20 | #include <linux/regulator/pmic8901-regulator.h> |
Steve Muckle | f132c6c | 2012-06-06 18:30:57 -0700 | [diff] [blame] | 21 | #include <linux/module.h> |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 22 | |
| 23 | /* Regulator types */ |
| 24 | #define REGULATOR_TYPE_LDO 0 |
| 25 | #define REGULATOR_TYPE_SMPS 1 |
| 26 | #define REGULATOR_TYPE_VS 2 |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 27 | |
| 28 | /* Bank select/write macros */ |
| 29 | #define REGULATOR_BANK_SEL(n) ((n) << 4) |
| 30 | #define REGULATOR_BANK_WRITE 0x80 |
| 31 | #define LDO_TEST_BANKS 7 |
| 32 | #define REGULATOR_BANK_MASK 0xF0 |
| 33 | |
| 34 | /* Pin mask resource register programming */ |
| 35 | #define VREG_PMR_STATE_MASK 0x60 |
| 36 | #define VREG_PMR_STATE_HPM 0x60 |
| 37 | #define VREG_PMR_STATE_LPM 0x40 |
| 38 | #define VREG_PMR_STATE_OFF 0x20 |
| 39 | #define VREG_PMR_STATE_PIN_CTRL 0x20 |
| 40 | |
| 41 | #define VREG_PMR_MODE_ACTION_MASK 0x10 |
| 42 | #define VREG_PMR_MODE_ACTION_SLEEP 0x10 |
| 43 | #define VREG_PMR_MODE_ACTION_OFF 0x00 |
| 44 | |
| 45 | #define VREG_PMR_MODE_PIN_MASK 0x08 |
| 46 | #define VREG_PMR_MODE_PIN_MASKED 0x08 |
| 47 | |
| 48 | #define VREG_PMR_CTRL_PIN2_MASK 0x04 |
| 49 | #define VREG_PMR_CTRL_PIN2_MASKED 0x04 |
| 50 | |
| 51 | #define VREG_PMR_CTRL_PIN1_MASK 0x02 |
| 52 | #define VREG_PMR_CTRL_PIN1_MASKED 0x02 |
| 53 | |
| 54 | #define VREG_PMR_CTRL_PIN0_MASK 0x01 |
| 55 | #define VREG_PMR_CTRL_PIN0_MASKED 0x01 |
| 56 | |
| 57 | #define VREG_PMR_PIN_CTRL_ALL_MASK 0x1F |
| 58 | #define VREG_PMR_PIN_CTRL_ALL_MASKED 0x1F |
| 59 | |
| 60 | #define REGULATOR_IS_EN(pmr_reg) \ |
| 61 | ((pmr_reg & VREG_PMR_STATE_MASK) == VREG_PMR_STATE_HPM || \ |
| 62 | (pmr_reg & VREG_PMR_STATE_MASK) == VREG_PMR_STATE_LPM) |
| 63 | |
| 64 | /* FTSMPS programming */ |
| 65 | |
| 66 | /* CTRL register */ |
| 67 | #define SMPS_VCTRL_BAND_MASK 0xC0 |
| 68 | #define SMPS_VCTRL_BAND_OFF 0x00 |
| 69 | #define SMPS_VCTRL_BAND_1 0x40 |
| 70 | #define SMPS_VCTRL_BAND_2 0x80 |
| 71 | #define SMPS_VCTRL_BAND_3 0xC0 |
| 72 | #define SMPS_VCTRL_VPROG_MASK 0x3F |
| 73 | |
| 74 | #define SMPS_BAND_1_UV_MIN 350000 |
| 75 | #define SMPS_BAND_1_UV_MAX 650000 |
| 76 | #define SMPS_BAND_1_UV_STEP 6250 |
| 77 | |
| 78 | #define SMPS_BAND_2_UV_MIN 700000 |
| 79 | #define SMPS_BAND_2_UV_MAX 1400000 |
| 80 | #define SMPS_BAND_2_UV_STEP 12500 |
| 81 | |
| 82 | #define SMPS_BAND_3_UV_SETPOINT_MIN 1500000 |
| 83 | #define SMPS_BAND_3_UV_MIN 1400000 |
| 84 | #define SMPS_BAND_3_UV_MAX 3300000 |
| 85 | #define SMPS_BAND_3_UV_STEP 50000 |
| 86 | |
| 87 | #define SMPS_UV_MIN SMPS_BAND_1_UV_MIN |
| 88 | #define SMPS_UV_MAX SMPS_BAND_3_UV_MAX |
| 89 | |
| 90 | /* PWR_CNFG register */ |
| 91 | #define SMPS_PULL_DOWN_ENABLE_MASK 0x40 |
| 92 | #define SMPS_PULL_DOWN_ENABLE 0x40 |
| 93 | |
| 94 | /* LDO programming */ |
| 95 | |
| 96 | /* CTRL register */ |
| 97 | #define LDO_LOCAL_ENABLE_MASK 0x80 |
| 98 | #define LDO_LOCAL_ENABLE 0x80 |
| 99 | |
| 100 | #define LDO_PULL_DOWN_ENABLE_MASK 0x40 |
| 101 | #define LDO_PULL_DOWN_ENABLE 0x40 |
| 102 | |
| 103 | #define LDO_CTRL_VPROG_MASK 0x1F |
| 104 | |
| 105 | /* TEST register bank 2 */ |
| 106 | #define LDO_TEST_VPROG_UPDATE_MASK 0x08 |
| 107 | #define LDO_TEST_RANGE_SEL_MASK 0x04 |
| 108 | #define LDO_TEST_FINE_STEP_MASK 0x02 |
| 109 | #define LDO_TEST_FINE_STEP_SHIFT 1 |
| 110 | |
| 111 | /* TEST register bank 4 */ |
| 112 | #define LDO_TEST_RANGE_EXT_MASK 0x01 |
| 113 | |
| 114 | /* Allowable voltage ranges */ |
| 115 | #define PLDO_LOW_UV_MIN 750000 |
| 116 | #define PLDO_LOW_UV_MAX 1537500 |
| 117 | #define PLDO_LOW_FINE_STEP_UV 12500 |
| 118 | |
| 119 | #define PLDO_NORM_UV_MIN 1500000 |
| 120 | #define PLDO_NORM_UV_MAX 3075000 |
| 121 | #define PLDO_NORM_FINE_STEP_UV 25000 |
| 122 | |
| 123 | #define PLDO_HIGH_UV_MIN 1750000 |
| 124 | #define PLDO_HIGH_UV_MAX 4900000 |
| 125 | #define PLDO_HIGH_FINE_STEP_UV 50000 |
| 126 | |
| 127 | #define NLDO_UV_MIN 750000 |
| 128 | #define NLDO_UV_MAX 1537500 |
| 129 | #define NLDO_FINE_STEP_UV 12500 |
| 130 | |
| 131 | /* VS programming */ |
| 132 | |
| 133 | /* CTRL register */ |
| 134 | #define VS_CTRL_ENABLE_MASK 0xC0 |
| 135 | #define VS_CTRL_DISABLE 0x00 |
| 136 | #define VS_CTRL_ENABLE 0x40 |
| 137 | #define VS_CTRL_USE_PMR 0xC0 |
| 138 | |
| 139 | #define VS_PULL_DOWN_ENABLE_MASK 0x20 |
| 140 | #define VS_PULL_DOWN_ENABLE 0x20 |
| 141 | |
| 142 | struct pm8901_vreg { |
Anirudh Ghayal | 9f77e96 | 2011-12-06 12:38:21 +0530 | [diff] [blame] | 143 | struct device *dev; |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 144 | struct pm8901_vreg_pdata *pdata; |
| 145 | struct regulator_dev *rdev; |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 146 | int hpm_min_load; |
| 147 | unsigned pc_vote; |
| 148 | unsigned optimum; |
| 149 | unsigned mode_initialized; |
| 150 | u16 ctrl_addr; |
| 151 | u16 pmr_addr; |
| 152 | u16 test_addr; |
| 153 | u16 pfm_ctrl_addr; |
| 154 | u16 pwr_cnfg_addr; |
| 155 | u8 type; |
| 156 | u8 ctrl_reg; |
| 157 | u8 pmr_reg; |
| 158 | u8 test_reg[LDO_TEST_BANKS]; |
| 159 | u8 pfm_ctrl_reg; |
| 160 | u8 pwr_cnfg_reg; |
| 161 | u8 is_nmos; |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 162 | u8 state; |
| 163 | }; |
| 164 | |
| 165 | /* |
| 166 | * These are used to compensate for the PMIC 8901 v1 FTS regulators which |
| 167 | * output ~10% higher than the programmed set point. |
| 168 | */ |
Anirudh Ghayal | 9f77e96 | 2011-12-06 12:38:21 +0530 | [diff] [blame] | 169 | #define IS_PMIC_8901_V1(rev) ((rev) == PM8XXX_REVISION_8901_1p0 || \ |
| 170 | (rev) == PM8XXX_REVISION_8901_1p1) |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 171 | |
| 172 | #define PMIC_8901_V1_SCALE(uV) ((((uV) - 62100) * 23) / 25) |
| 173 | |
| 174 | #define PMIC_8901_V1_SCALE_INV(uV) (((uV) * 25) / 23 + 62100) |
| 175 | |
| 176 | /* |
| 177 | * Band 1 of PMIC 8901 SMPS regulators only supports set points with the 3 LSB's |
| 178 | * equal to 0. This is accomplished in the macro by truncating the bits. |
| 179 | */ |
| 180 | #define PM8901_SMPS_BAND_1_COMPENSATE(vprog) ((vprog) & 0xF8) |
| 181 | |
| 182 | #define LDO(_id, _ctrl_addr, _pmr_addr, _test_addr, _is_nmos) \ |
| 183 | [_id] = { \ |
| 184 | .ctrl_addr = _ctrl_addr, \ |
| 185 | .pmr_addr = _pmr_addr, \ |
| 186 | .test_addr = _test_addr, \ |
| 187 | .type = REGULATOR_TYPE_LDO, \ |
| 188 | .is_nmos = _is_nmos, \ |
| 189 | .hpm_min_load = PM8901_VREG_LDO_300_HPM_MIN_LOAD, \ |
| 190 | } |
| 191 | |
| 192 | #define SMPS(_id, _ctrl_addr, _pmr_addr, _pfm_ctrl_addr, _pwr_cnfg_addr) \ |
| 193 | [_id] = { \ |
| 194 | .ctrl_addr = _ctrl_addr, \ |
| 195 | .pmr_addr = _pmr_addr, \ |
| 196 | .pfm_ctrl_addr = _pfm_ctrl_addr, \ |
| 197 | .pwr_cnfg_addr = _pwr_cnfg_addr, \ |
| 198 | .type = REGULATOR_TYPE_SMPS, \ |
| 199 | .hpm_min_load = PM8901_VREG_FTSMPS_HPM_MIN_LOAD, \ |
| 200 | } |
| 201 | |
| 202 | #define VS(_id, _ctrl_addr, _pmr_addr) \ |
| 203 | [_id] = { \ |
| 204 | .ctrl_addr = _ctrl_addr, \ |
| 205 | .pmr_addr = _pmr_addr, \ |
| 206 | .type = REGULATOR_TYPE_VS, \ |
| 207 | } |
| 208 | |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 209 | static struct pm8901_vreg pm8901_vreg[] = { |
| 210 | /* id ctrl pmr tst n/p */ |
| 211 | LDO(PM8901_VREG_ID_L0, 0x02F, 0x0AB, 0x030, 1), |
| 212 | LDO(PM8901_VREG_ID_L1, 0x031, 0x0AC, 0x032, 0), |
| 213 | LDO(PM8901_VREG_ID_L2, 0x033, 0x0AD, 0x034, 0), |
| 214 | LDO(PM8901_VREG_ID_L3, 0x035, 0x0AE, 0x036, 0), |
| 215 | LDO(PM8901_VREG_ID_L4, 0x037, 0x0AF, 0x038, 0), |
| 216 | LDO(PM8901_VREG_ID_L5, 0x039, 0x0B0, 0x03A, 0), |
| 217 | LDO(PM8901_VREG_ID_L6, 0x03B, 0x0B1, 0x03C, 0), |
| 218 | |
| 219 | /* id ctrl pmr pfm pwr */ |
| 220 | SMPS(PM8901_VREG_ID_S0, 0x05B, 0x0A6, 0x05C, 0x0E3), |
| 221 | SMPS(PM8901_VREG_ID_S1, 0x06A, 0x0A7, 0x06B, 0x0EC), |
| 222 | SMPS(PM8901_VREG_ID_S2, 0x079, 0x0A8, 0x07A, 0x0F1), |
| 223 | SMPS(PM8901_VREG_ID_S3, 0x088, 0x0A9, 0x089, 0x0F6), |
| 224 | SMPS(PM8901_VREG_ID_S4, 0x097, 0x0AA, 0x098, 0x0FB), |
| 225 | |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 226 | /* id ctrl pmr */ |
| 227 | VS(PM8901_VREG_ID_LVS0, 0x046, 0x0B2), |
| 228 | VS(PM8901_VREG_ID_LVS1, 0x048, 0x0B3), |
| 229 | VS(PM8901_VREG_ID_LVS2, 0x04A, 0x0B4), |
| 230 | VS(PM8901_VREG_ID_LVS3, 0x04C, 0x0B5), |
| 231 | VS(PM8901_VREG_ID_MVS0, 0x052, 0x0B6), |
| 232 | VS(PM8901_VREG_ID_USB_OTG, 0x055, 0x0B7), |
| 233 | VS(PM8901_VREG_ID_HDMI_MVS, 0x058, 0x0B8), |
| 234 | }; |
| 235 | |
| 236 | static void print_write_error(struct pm8901_vreg *vreg, int rc, |
| 237 | const char *func); |
| 238 | |
Anirudh Ghayal | 9f77e96 | 2011-12-06 12:38:21 +0530 | [diff] [blame] | 239 | static int pm8901_vreg_write(struct pm8901_vreg *vreg, |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 240 | u16 addr, u8 val, u8 mask, u8 *reg_save) |
| 241 | { |
| 242 | int rc = 0; |
| 243 | u8 reg; |
| 244 | |
| 245 | reg = (*reg_save & ~mask) | (val & mask); |
| 246 | if (reg != *reg_save) |
Anirudh Ghayal | 9f77e96 | 2011-12-06 12:38:21 +0530 | [diff] [blame] | 247 | rc = pm8xxx_writeb(vreg->dev->parent, addr, reg); |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 248 | if (!rc) |
| 249 | *reg_save = reg; |
| 250 | return rc; |
| 251 | } |
| 252 | |
| 253 | /* Set pin control bits based on new mode. */ |
| 254 | static int pm8901_vreg_select_pin_ctrl(struct pm8901_vreg *vreg, u8 *pmr_reg) |
| 255 | { |
| 256 | *pmr_reg |= VREG_PMR_PIN_CTRL_ALL_MASKED; |
| 257 | |
| 258 | if ((*pmr_reg & VREG_PMR_STATE_MASK) == VREG_PMR_STATE_PIN_CTRL) { |
| 259 | if (vreg->pdata->pin_fn == PM8901_VREG_PIN_FN_MODE) |
| 260 | *pmr_reg = (*pmr_reg & ~VREG_PMR_STATE_MASK) |
| 261 | | VREG_PMR_STATE_LPM; |
| 262 | if (vreg->pdata->pin_ctrl & PM8901_VREG_PIN_CTRL_A0) |
| 263 | *pmr_reg &= ~VREG_PMR_CTRL_PIN0_MASKED; |
| 264 | if (vreg->pdata->pin_ctrl & PM8901_VREG_PIN_CTRL_A1) |
| 265 | *pmr_reg &= ~VREG_PMR_CTRL_PIN1_MASKED; |
| 266 | if (vreg->pdata->pin_ctrl & PM8901_VREG_PIN_CTRL_D0) |
| 267 | *pmr_reg &= ~VREG_PMR_CTRL_PIN2_MASKED; |
| 268 | } |
| 269 | |
| 270 | return 0; |
| 271 | } |
| 272 | |
| 273 | static int pm8901_vreg_enable(struct regulator_dev *dev) |
| 274 | { |
| 275 | struct pm8901_vreg *vreg = rdev_get_drvdata(dev); |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 276 | u8 val = VREG_PMR_STATE_HPM; |
| 277 | int rc; |
| 278 | |
| 279 | if (!vreg->mode_initialized && vreg->pc_vote) |
| 280 | val = VREG_PMR_STATE_PIN_CTRL; |
| 281 | else if (vreg->optimum == REGULATOR_MODE_FAST) |
| 282 | val = VREG_PMR_STATE_HPM; |
| 283 | else if (vreg->pc_vote) |
| 284 | val = VREG_PMR_STATE_PIN_CTRL; |
| 285 | else if (vreg->optimum == REGULATOR_MODE_STANDBY) |
| 286 | val = VREG_PMR_STATE_LPM; |
| 287 | |
| 288 | pm8901_vreg_select_pin_ctrl(vreg, &val); |
| 289 | |
Anirudh Ghayal | 9f77e96 | 2011-12-06 12:38:21 +0530 | [diff] [blame] | 290 | rc = pm8901_vreg_write(vreg, vreg->pmr_addr, |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 291 | val, |
| 292 | VREG_PMR_STATE_MASK | VREG_PMR_PIN_CTRL_ALL_MASK, |
| 293 | &vreg->pmr_reg); |
| 294 | if (rc) |
| 295 | print_write_error(vreg, rc, __func__); |
| 296 | |
| 297 | return rc; |
| 298 | } |
| 299 | |
| 300 | static int pm8901_vreg_disable(struct regulator_dev *dev) |
| 301 | { |
| 302 | struct pm8901_vreg *vreg = rdev_get_drvdata(dev); |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 303 | int rc; |
| 304 | |
Anirudh Ghayal | 9f77e96 | 2011-12-06 12:38:21 +0530 | [diff] [blame] | 305 | rc = pm8901_vreg_write(vreg, vreg->pmr_addr, |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 306 | VREG_PMR_STATE_OFF | VREG_PMR_PIN_CTRL_ALL_MASKED, |
| 307 | VREG_PMR_STATE_MASK | VREG_PMR_PIN_CTRL_ALL_MASK, |
| 308 | &vreg->pmr_reg); |
| 309 | if (rc) |
| 310 | print_write_error(vreg, rc, __func__); |
| 311 | |
| 312 | return rc; |
| 313 | } |
| 314 | |
| 315 | /* |
| 316 | * Cases that count as enabled: |
| 317 | * |
| 318 | * 1. PMR register has mode == HPM or LPM. |
| 319 | * 2. Any pin control bits are unmasked. |
| 320 | * 3. The regulator is an LDO and its local enable bit is set. |
| 321 | */ |
| 322 | static int _pm8901_vreg_is_enabled(struct pm8901_vreg *vreg) |
| 323 | { |
| 324 | if ((vreg->type == REGULATOR_TYPE_LDO) |
| 325 | && (vreg->ctrl_reg & LDO_LOCAL_ENABLE_MASK)) |
| 326 | return 1; |
| 327 | else if (vreg->type == REGULATOR_TYPE_VS) { |
| 328 | if ((vreg->ctrl_reg & VS_CTRL_ENABLE_MASK) == VS_CTRL_ENABLE) |
| 329 | return 1; |
| 330 | else if ((vreg->ctrl_reg & VS_CTRL_ENABLE_MASK) |
| 331 | == VS_CTRL_DISABLE) |
| 332 | return 0; |
| 333 | } |
| 334 | |
| 335 | return REGULATOR_IS_EN(vreg->pmr_reg) |
| 336 | || ((vreg->pmr_reg & VREG_PMR_PIN_CTRL_ALL_MASK) |
| 337 | != VREG_PMR_PIN_CTRL_ALL_MASKED); |
| 338 | } |
| 339 | |
| 340 | static int pm8901_vreg_is_enabled(struct regulator_dev *dev) |
| 341 | { |
| 342 | struct pm8901_vreg *vreg = rdev_get_drvdata(dev); |
| 343 | |
| 344 | return _pm8901_vreg_is_enabled(vreg); |
| 345 | } |
| 346 | |
| 347 | static int pm8901_ldo_disable(struct regulator_dev *dev) |
| 348 | { |
| 349 | struct pm8901_vreg *vreg = rdev_get_drvdata(dev); |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 350 | int rc; |
| 351 | |
| 352 | /* Disassert local enable bit in CTRL register. */ |
Anirudh Ghayal | 9f77e96 | 2011-12-06 12:38:21 +0530 | [diff] [blame] | 353 | rc = pm8901_vreg_write(vreg, vreg->ctrl_addr, 0, LDO_LOCAL_ENABLE_MASK, |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 354 | &vreg->ctrl_reg); |
| 355 | if (rc) |
| 356 | print_write_error(vreg, rc, __func__); |
| 357 | |
| 358 | /* Disassert enable bit in PMR register. */ |
| 359 | rc = pm8901_vreg_disable(dev); |
| 360 | |
| 361 | return rc; |
| 362 | } |
| 363 | |
Anirudh Ghayal | 9f77e96 | 2011-12-06 12:38:21 +0530 | [diff] [blame] | 364 | static int pm8901_pldo_set_voltage(struct pm8901_vreg *vreg, int uV) |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 365 | { |
| 366 | int vmin, rc = 0; |
| 367 | unsigned vprog, fine_step; |
| 368 | u8 range_ext, range_sel, fine_step_reg; |
| 369 | |
| 370 | if (uV < PLDO_LOW_UV_MIN || uV > PLDO_HIGH_UV_MAX) |
| 371 | return -EINVAL; |
| 372 | |
| 373 | if (uV < PLDO_LOW_UV_MAX + PLDO_LOW_FINE_STEP_UV) { |
| 374 | vmin = PLDO_LOW_UV_MIN; |
| 375 | fine_step = PLDO_LOW_FINE_STEP_UV; |
| 376 | range_ext = 0; |
| 377 | range_sel = LDO_TEST_RANGE_SEL_MASK; |
| 378 | } else if (uV < PLDO_NORM_UV_MAX + PLDO_NORM_FINE_STEP_UV) { |
| 379 | vmin = PLDO_NORM_UV_MIN; |
| 380 | fine_step = PLDO_NORM_FINE_STEP_UV; |
| 381 | range_ext = 0; |
| 382 | range_sel = 0; |
| 383 | } else { |
| 384 | vmin = PLDO_HIGH_UV_MIN; |
| 385 | fine_step = PLDO_HIGH_FINE_STEP_UV; |
| 386 | range_ext = LDO_TEST_RANGE_EXT_MASK; |
| 387 | range_sel = 0; |
| 388 | } |
| 389 | |
| 390 | vprog = (uV - vmin) / fine_step; |
| 391 | fine_step_reg = (vprog & 1) << LDO_TEST_FINE_STEP_SHIFT; |
| 392 | vprog >>= 1; |
| 393 | |
| 394 | /* |
| 395 | * Disable program voltage update if range extension, range select, |
| 396 | * or fine step have changed and the regulator is enabled. |
| 397 | */ |
| 398 | if (_pm8901_vreg_is_enabled(vreg) && |
| 399 | (((range_ext ^ vreg->test_reg[4]) & LDO_TEST_RANGE_EXT_MASK) |
| 400 | || ((range_sel ^ vreg->test_reg[2]) & LDO_TEST_RANGE_SEL_MASK) |
| 401 | || ((fine_step_reg ^ vreg->test_reg[2]) |
| 402 | & LDO_TEST_FINE_STEP_MASK))) { |
Anirudh Ghayal | 9f77e96 | 2011-12-06 12:38:21 +0530 | [diff] [blame] | 403 | rc = pm8901_vreg_write(vreg, vreg->test_addr, |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 404 | REGULATOR_BANK_SEL(2) | REGULATOR_BANK_WRITE, |
| 405 | REGULATOR_BANK_MASK | LDO_TEST_VPROG_UPDATE_MASK, |
| 406 | &vreg->test_reg[2]); |
| 407 | if (rc) |
| 408 | goto bail; |
| 409 | } |
| 410 | |
| 411 | /* Write new voltage. */ |
Anirudh Ghayal | 9f77e96 | 2011-12-06 12:38:21 +0530 | [diff] [blame] | 412 | rc = pm8901_vreg_write(vreg, vreg->ctrl_addr, vprog, |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 413 | LDO_CTRL_VPROG_MASK, &vreg->ctrl_reg); |
| 414 | if (rc) |
| 415 | goto bail; |
| 416 | |
| 417 | /* Write range extension. */ |
Anirudh Ghayal | 9f77e96 | 2011-12-06 12:38:21 +0530 | [diff] [blame] | 418 | rc = pm8901_vreg_write(vreg, vreg->test_addr, |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 419 | range_ext | REGULATOR_BANK_SEL(4) |
| 420 | | REGULATOR_BANK_WRITE, |
| 421 | LDO_TEST_RANGE_EXT_MASK | REGULATOR_BANK_MASK, |
| 422 | &vreg->test_reg[4]); |
| 423 | if (rc) |
| 424 | goto bail; |
| 425 | |
| 426 | /* Write fine step, range select and program voltage update. */ |
Anirudh Ghayal | 9f77e96 | 2011-12-06 12:38:21 +0530 | [diff] [blame] | 427 | rc = pm8901_vreg_write(vreg, vreg->test_addr, |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 428 | fine_step_reg | range_sel | REGULATOR_BANK_SEL(2) |
| 429 | | REGULATOR_BANK_WRITE | LDO_TEST_VPROG_UPDATE_MASK, |
| 430 | LDO_TEST_FINE_STEP_MASK | LDO_TEST_RANGE_SEL_MASK |
| 431 | | REGULATOR_BANK_MASK | LDO_TEST_VPROG_UPDATE_MASK, |
| 432 | &vreg->test_reg[2]); |
| 433 | bail: |
| 434 | if (rc) |
| 435 | print_write_error(vreg, rc, __func__); |
| 436 | |
| 437 | return rc; |
| 438 | } |
| 439 | |
Anirudh Ghayal | 9f77e96 | 2011-12-06 12:38:21 +0530 | [diff] [blame] | 440 | static int pm8901_nldo_set_voltage(struct pm8901_vreg *vreg, int uV) |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 441 | { |
| 442 | unsigned vprog, fine_step_reg; |
| 443 | int rc; |
| 444 | |
| 445 | if (uV < NLDO_UV_MIN || uV > NLDO_UV_MAX) |
| 446 | return -EINVAL; |
| 447 | |
| 448 | vprog = (uV - NLDO_UV_MIN) / NLDO_FINE_STEP_UV; |
| 449 | fine_step_reg = (vprog & 1) << LDO_TEST_FINE_STEP_SHIFT; |
| 450 | vprog >>= 1; |
| 451 | |
| 452 | /* Write new voltage. */ |
Anirudh Ghayal | 9f77e96 | 2011-12-06 12:38:21 +0530 | [diff] [blame] | 453 | rc = pm8901_vreg_write(vreg, vreg->ctrl_addr, vprog, |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 454 | LDO_CTRL_VPROG_MASK, &vreg->ctrl_reg); |
| 455 | if (rc) |
| 456 | print_write_error(vreg, rc, __func__); |
| 457 | |
| 458 | /* Write fine step. */ |
Anirudh Ghayal | 9f77e96 | 2011-12-06 12:38:21 +0530 | [diff] [blame] | 459 | rc = pm8901_vreg_write(vreg, vreg->test_addr, |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 460 | fine_step_reg | REGULATOR_BANK_SEL(2) |
| 461 | | REGULATOR_BANK_WRITE | LDO_TEST_VPROG_UPDATE_MASK, |
| 462 | LDO_TEST_FINE_STEP_MASK | REGULATOR_BANK_MASK |
| 463 | | LDO_TEST_VPROG_UPDATE_MASK, |
| 464 | &vreg->test_reg[2]); |
| 465 | if (rc) |
| 466 | print_write_error(vreg, rc, __func__); |
| 467 | |
| 468 | return rc; |
| 469 | } |
| 470 | |
| 471 | static int pm8901_ldo_set_voltage(struct regulator_dev *dev, |
| 472 | int min_uV, int max_uV, unsigned *selector) |
| 473 | { |
| 474 | struct pm8901_vreg *vreg = rdev_get_drvdata(dev); |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 475 | |
| 476 | if (vreg->is_nmos) |
Anirudh Ghayal | 9f77e96 | 2011-12-06 12:38:21 +0530 | [diff] [blame] | 477 | return pm8901_nldo_set_voltage(vreg, min_uV); |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 478 | else |
Anirudh Ghayal | 9f77e96 | 2011-12-06 12:38:21 +0530 | [diff] [blame] | 479 | return pm8901_pldo_set_voltage(vreg, min_uV); |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 480 | } |
| 481 | |
| 482 | static int pm8901_pldo_get_voltage(struct pm8901_vreg *vreg) |
| 483 | { |
| 484 | int vmin, fine_step; |
| 485 | u8 range_ext, range_sel, vprog, fine_step_reg; |
| 486 | |
| 487 | fine_step_reg = vreg->test_reg[2] & LDO_TEST_FINE_STEP_MASK; |
| 488 | range_sel = vreg->test_reg[2] & LDO_TEST_RANGE_SEL_MASK; |
| 489 | range_ext = vreg->test_reg[4] & LDO_TEST_RANGE_EXT_MASK; |
| 490 | vprog = vreg->ctrl_reg & LDO_CTRL_VPROG_MASK; |
| 491 | |
| 492 | vprog = (vprog << 1) | (fine_step_reg >> LDO_TEST_FINE_STEP_SHIFT); |
| 493 | |
| 494 | if (range_sel) { |
| 495 | /* low range mode */ |
| 496 | fine_step = PLDO_LOW_FINE_STEP_UV; |
| 497 | vmin = PLDO_LOW_UV_MIN; |
| 498 | } else if (!range_ext) { |
| 499 | /* normal mode */ |
| 500 | fine_step = PLDO_NORM_FINE_STEP_UV; |
| 501 | vmin = PLDO_NORM_UV_MIN; |
| 502 | } else { |
| 503 | /* high range mode */ |
| 504 | fine_step = PLDO_HIGH_FINE_STEP_UV; |
| 505 | vmin = PLDO_HIGH_UV_MIN; |
| 506 | } |
| 507 | |
| 508 | return fine_step * vprog + vmin; |
| 509 | } |
| 510 | |
| 511 | static int pm8901_nldo_get_voltage(struct pm8901_vreg *vreg) |
| 512 | { |
| 513 | u8 vprog, fine_step_reg; |
| 514 | |
| 515 | fine_step_reg = vreg->test_reg[2] & LDO_TEST_FINE_STEP_MASK; |
| 516 | vprog = vreg->ctrl_reg & LDO_CTRL_VPROG_MASK; |
| 517 | |
| 518 | vprog = (vprog << 1) | (fine_step_reg >> LDO_TEST_FINE_STEP_SHIFT); |
| 519 | |
| 520 | return NLDO_FINE_STEP_UV * vprog + NLDO_UV_MIN; |
| 521 | } |
| 522 | |
| 523 | static int pm8901_ldo_get_voltage(struct regulator_dev *dev) |
| 524 | { |
| 525 | struct pm8901_vreg *vreg = rdev_get_drvdata(dev); |
| 526 | |
| 527 | if (vreg->is_nmos) |
| 528 | return pm8901_nldo_get_voltage(vreg); |
| 529 | else |
| 530 | return pm8901_pldo_get_voltage(vreg); |
| 531 | } |
| 532 | |
| 533 | /* |
| 534 | * Optimum mode programming: |
| 535 | * REGULATOR_MODE_FAST: Go to HPM (highest priority) |
| 536 | * REGULATOR_MODE_STANDBY: Go to pin ctrl mode if there are any pin ctrl |
| 537 | * votes, else go to LPM |
| 538 | * |
| 539 | * Pin ctrl mode voting via regulator set_mode: |
| 540 | * REGULATOR_MODE_IDLE: Go to pin ctrl mode if the optimum mode is LPM, else |
| 541 | * go to HPM |
| 542 | * REGULATOR_MODE_NORMAL: Go to LPM if it is the optimum mode, else go to HPM |
| 543 | */ |
| 544 | static int pm8901_vreg_set_mode(struct regulator_dev *dev, unsigned int mode) |
| 545 | { |
| 546 | struct pm8901_vreg *vreg = rdev_get_drvdata(dev); |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 547 | unsigned optimum = vreg->optimum; |
| 548 | unsigned pc_vote = vreg->pc_vote; |
| 549 | unsigned mode_initialized = vreg->mode_initialized; |
| 550 | u8 val = 0; |
| 551 | int rc = 0; |
| 552 | |
| 553 | /* Determine new mode to go into. */ |
| 554 | switch (mode) { |
| 555 | case REGULATOR_MODE_FAST: |
| 556 | val = VREG_PMR_STATE_HPM; |
| 557 | optimum = mode; |
| 558 | mode_initialized = 1; |
| 559 | break; |
| 560 | |
| 561 | case REGULATOR_MODE_STANDBY: |
| 562 | if (pc_vote) |
| 563 | val = VREG_PMR_STATE_PIN_CTRL; |
| 564 | else |
| 565 | val = VREG_PMR_STATE_LPM; |
| 566 | optimum = mode; |
| 567 | mode_initialized = 1; |
| 568 | break; |
| 569 | |
| 570 | case REGULATOR_MODE_IDLE: |
| 571 | if (pc_vote++) |
| 572 | goto done; /* already taken care of */ |
| 573 | |
| 574 | if (mode_initialized && optimum == REGULATOR_MODE_FAST) |
| 575 | val = VREG_PMR_STATE_HPM; |
| 576 | else |
| 577 | val = VREG_PMR_STATE_PIN_CTRL; |
| 578 | break; |
| 579 | |
| 580 | case REGULATOR_MODE_NORMAL: |
| 581 | if (pc_vote && --pc_vote) |
| 582 | goto done; /* already taken care of */ |
| 583 | |
| 584 | if (optimum == REGULATOR_MODE_STANDBY) |
| 585 | val = VREG_PMR_STATE_LPM; |
| 586 | else |
| 587 | val = VREG_PMR_STATE_HPM; |
| 588 | break; |
| 589 | |
| 590 | default: |
| 591 | pr_err("%s: unknown mode, mode=%u\n", __func__, mode); |
| 592 | return -EINVAL; |
| 593 | } |
| 594 | |
| 595 | /* Set pin control bits based on new mode. */ |
| 596 | pm8901_vreg_select_pin_ctrl(vreg, &val); |
| 597 | |
| 598 | /* Only apply mode setting to hardware if currently enabled. */ |
| 599 | if (pm8901_vreg_is_enabled(dev)) |
Anirudh Ghayal | 9f77e96 | 2011-12-06 12:38:21 +0530 | [diff] [blame] | 600 | rc = pm8901_vreg_write(vreg, vreg->pmr_addr, val, |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 601 | VREG_PMR_STATE_MASK | VREG_PMR_PIN_CTRL_ALL_MASK, |
| 602 | &vreg->pmr_reg); |
| 603 | |
| 604 | if (rc) { |
| 605 | print_write_error(vreg, rc, __func__); |
| 606 | return rc; |
| 607 | } |
| 608 | |
| 609 | done: |
| 610 | vreg->mode_initialized = mode_initialized; |
| 611 | vreg->optimum = optimum; |
| 612 | vreg->pc_vote = pc_vote; |
| 613 | |
| 614 | return 0; |
| 615 | } |
| 616 | |
| 617 | static unsigned int pm8901_vreg_get_mode(struct regulator_dev *dev) |
| 618 | { |
| 619 | struct pm8901_vreg *vreg = rdev_get_drvdata(dev); |
| 620 | int pin_mask = VREG_PMR_CTRL_PIN0_MASK | VREG_PMR_CTRL_PIN1_MASK |
| 621 | | VREG_PMR_CTRL_PIN2_MASK; |
| 622 | |
| 623 | if (!vreg->mode_initialized && vreg->pc_vote) |
| 624 | return REGULATOR_MODE_IDLE; |
| 625 | else if (((vreg->pmr_reg & VREG_PMR_STATE_MASK) == VREG_PMR_STATE_OFF) |
| 626 | && ((vreg->pmr_reg & pin_mask) != pin_mask)) |
| 627 | return REGULATOR_MODE_IDLE; |
| 628 | else if (((vreg->pmr_reg & VREG_PMR_STATE_MASK) == VREG_PMR_STATE_LPM) |
| 629 | && ((vreg->pmr_reg & pin_mask) != pin_mask)) |
| 630 | return REGULATOR_MODE_IDLE; |
| 631 | else if (vreg->optimum == REGULATOR_MODE_FAST) |
| 632 | return REGULATOR_MODE_FAST; |
| 633 | else if (vreg->pc_vote) |
| 634 | return REGULATOR_MODE_IDLE; |
| 635 | else if (vreg->optimum == REGULATOR_MODE_STANDBY) |
| 636 | return REGULATOR_MODE_STANDBY; |
| 637 | return REGULATOR_MODE_FAST; |
| 638 | } |
| 639 | |
| 640 | unsigned int pm8901_vreg_get_optimum_mode(struct regulator_dev *dev, |
| 641 | int input_uV, int output_uV, int load_uA) |
| 642 | { |
| 643 | struct pm8901_vreg *vreg = rdev_get_drvdata(dev); |
| 644 | |
| 645 | if (load_uA <= 0) { |
| 646 | /* |
| 647 | * pm8901_vreg_get_optimum_mode is being called before consumers |
| 648 | * have specified their load currents via |
| 649 | * regulator_set_optimum_mode. Return whatever the existing mode |
| 650 | * is. |
| 651 | */ |
| 652 | return pm8901_vreg_get_mode(dev); |
| 653 | } |
| 654 | |
| 655 | if (load_uA >= vreg->hpm_min_load) |
| 656 | return REGULATOR_MODE_FAST; |
| 657 | return REGULATOR_MODE_STANDBY; |
| 658 | } |
| 659 | |
| 660 | static int pm8901_smps_set_voltage(struct regulator_dev *dev, |
| 661 | int min_uV, int max_uV, unsigned *selector) |
| 662 | { |
| 663 | struct pm8901_vreg *vreg = rdev_get_drvdata(dev); |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 664 | int rc; |
| 665 | u8 val, band; |
| 666 | |
Anirudh Ghayal | 9f77e96 | 2011-12-06 12:38:21 +0530 | [diff] [blame] | 667 | if (IS_PMIC_8901_V1(pm8xxx_get_revision(vreg->dev->parent))) |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 668 | min_uV = PMIC_8901_V1_SCALE(min_uV); |
| 669 | |
| 670 | if (min_uV < SMPS_BAND_1_UV_MIN || min_uV > SMPS_BAND_3_UV_MAX) |
| 671 | return -EINVAL; |
| 672 | |
| 673 | /* Round down for set points in the gaps between bands. */ |
| 674 | if (min_uV > SMPS_BAND_1_UV_MAX && min_uV < SMPS_BAND_2_UV_MIN) |
| 675 | min_uV = SMPS_BAND_1_UV_MAX; |
| 676 | else if (min_uV > SMPS_BAND_2_UV_MAX |
| 677 | && min_uV < SMPS_BAND_3_UV_SETPOINT_MIN) |
| 678 | min_uV = SMPS_BAND_2_UV_MAX; |
| 679 | |
| 680 | if (min_uV < SMPS_BAND_2_UV_MIN) { |
| 681 | val = ((min_uV - SMPS_BAND_1_UV_MIN) / SMPS_BAND_1_UV_STEP); |
| 682 | val = PM8901_SMPS_BAND_1_COMPENSATE(val); |
| 683 | band = SMPS_VCTRL_BAND_1; |
| 684 | } else if (min_uV < SMPS_BAND_3_UV_SETPOINT_MIN) { |
| 685 | val = ((min_uV - SMPS_BAND_2_UV_MIN) / SMPS_BAND_2_UV_STEP); |
| 686 | band = SMPS_VCTRL_BAND_2; |
| 687 | } else { |
| 688 | val = ((min_uV - SMPS_BAND_3_UV_MIN) / SMPS_BAND_3_UV_STEP); |
| 689 | band = SMPS_VCTRL_BAND_3; |
| 690 | } |
| 691 | |
Anirudh Ghayal | 9f77e96 | 2011-12-06 12:38:21 +0530 | [diff] [blame] | 692 | rc = pm8901_vreg_write(vreg, vreg->ctrl_addr, band | val, |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 693 | SMPS_VCTRL_BAND_MASK | SMPS_VCTRL_VPROG_MASK, |
| 694 | &vreg->ctrl_reg); |
| 695 | if (rc) |
| 696 | goto bail; |
| 697 | |
Anirudh Ghayal | 9f77e96 | 2011-12-06 12:38:21 +0530 | [diff] [blame] | 698 | rc = pm8901_vreg_write(vreg, vreg->pfm_ctrl_addr, band | val, |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 699 | SMPS_VCTRL_BAND_MASK | SMPS_VCTRL_VPROG_MASK, |
| 700 | &vreg->pfm_ctrl_reg); |
| 701 | bail: |
| 702 | if (rc) |
| 703 | print_write_error(vreg, rc, __func__); |
| 704 | |
| 705 | return rc; |
| 706 | } |
| 707 | |
| 708 | static int pm8901_smps_get_voltage(struct regulator_dev *dev) |
| 709 | { |
| 710 | struct pm8901_vreg *vreg = rdev_get_drvdata(dev); |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 711 | u8 vprog, band; |
| 712 | int ret = 0; |
| 713 | |
| 714 | if ((vreg->pmr_reg & VREG_PMR_STATE_MASK) == VREG_PMR_STATE_LPM) { |
| 715 | vprog = vreg->pfm_ctrl_reg & SMPS_VCTRL_VPROG_MASK; |
| 716 | band = vreg->pfm_ctrl_reg & SMPS_VCTRL_BAND_MASK; |
| 717 | } else { |
| 718 | vprog = vreg->ctrl_reg & SMPS_VCTRL_VPROG_MASK; |
| 719 | band = vreg->ctrl_reg & SMPS_VCTRL_BAND_MASK; |
| 720 | } |
| 721 | |
| 722 | if (band == SMPS_VCTRL_BAND_1) |
| 723 | ret = vprog * SMPS_BAND_1_UV_STEP + SMPS_BAND_1_UV_MIN; |
| 724 | else if (band == SMPS_VCTRL_BAND_2) |
| 725 | ret = vprog * SMPS_BAND_2_UV_STEP + SMPS_BAND_2_UV_MIN; |
| 726 | else |
| 727 | ret = vprog * SMPS_BAND_3_UV_STEP + SMPS_BAND_3_UV_MIN; |
| 728 | |
Anirudh Ghayal | 9f77e96 | 2011-12-06 12:38:21 +0530 | [diff] [blame] | 729 | if (IS_PMIC_8901_V1(pm8xxx_get_revision(vreg->dev->parent))) |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 730 | ret = PMIC_8901_V1_SCALE_INV(ret); |
| 731 | |
| 732 | return ret; |
| 733 | } |
| 734 | |
| 735 | static int pm8901_vs_enable(struct regulator_dev *dev) |
| 736 | { |
| 737 | struct pm8901_vreg *vreg = rdev_get_drvdata(dev); |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 738 | int rc; |
| 739 | |
| 740 | /* Assert enable bit in PMR register. */ |
| 741 | rc = pm8901_vreg_enable(dev); |
| 742 | |
| 743 | /* Make sure that switch is controlled via PMR register */ |
Anirudh Ghayal | 9f77e96 | 2011-12-06 12:38:21 +0530 | [diff] [blame] | 744 | rc = pm8901_vreg_write(vreg, vreg->ctrl_addr, VS_CTRL_USE_PMR, |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 745 | VS_CTRL_ENABLE_MASK, &vreg->ctrl_reg); |
| 746 | if (rc) |
| 747 | print_write_error(vreg, rc, __func__); |
| 748 | |
| 749 | return rc; |
| 750 | } |
| 751 | |
| 752 | static int pm8901_vs_disable(struct regulator_dev *dev) |
| 753 | { |
| 754 | struct pm8901_vreg *vreg = rdev_get_drvdata(dev); |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 755 | int rc; |
| 756 | |
| 757 | /* Disassert enable bit in PMR register. */ |
| 758 | rc = pm8901_vreg_disable(dev); |
| 759 | |
| 760 | /* Make sure that switch is controlled via PMR register */ |
Anirudh Ghayal | 9f77e96 | 2011-12-06 12:38:21 +0530 | [diff] [blame] | 761 | rc = pm8901_vreg_write(vreg, vreg->ctrl_addr, VS_CTRL_USE_PMR, |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 762 | VS_CTRL_ENABLE_MASK, &vreg->ctrl_reg); |
| 763 | if (rc) |
| 764 | print_write_error(vreg, rc, __func__); |
| 765 | |
| 766 | return rc; |
| 767 | } |
| 768 | |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 769 | static struct regulator_ops pm8901_ldo_ops = { |
| 770 | .enable = pm8901_vreg_enable, |
| 771 | .disable = pm8901_ldo_disable, |
| 772 | .is_enabled = pm8901_vreg_is_enabled, |
| 773 | .set_voltage = pm8901_ldo_set_voltage, |
| 774 | .get_voltage = pm8901_ldo_get_voltage, |
| 775 | .set_mode = pm8901_vreg_set_mode, |
| 776 | .get_mode = pm8901_vreg_get_mode, |
| 777 | .get_optimum_mode = pm8901_vreg_get_optimum_mode, |
| 778 | }; |
| 779 | |
| 780 | static struct regulator_ops pm8901_smps_ops = { |
| 781 | .enable = pm8901_vreg_enable, |
| 782 | .disable = pm8901_vreg_disable, |
| 783 | .is_enabled = pm8901_vreg_is_enabled, |
| 784 | .set_voltage = pm8901_smps_set_voltage, |
| 785 | .get_voltage = pm8901_smps_get_voltage, |
| 786 | .set_mode = pm8901_vreg_set_mode, |
| 787 | .get_mode = pm8901_vreg_get_mode, |
| 788 | .get_optimum_mode = pm8901_vreg_get_optimum_mode, |
| 789 | }; |
| 790 | |
| 791 | static struct regulator_ops pm8901_vs_ops = { |
| 792 | .enable = pm8901_vs_enable, |
| 793 | .disable = pm8901_vs_disable, |
| 794 | .is_enabled = pm8901_vreg_is_enabled, |
| 795 | .set_mode = pm8901_vreg_set_mode, |
| 796 | .get_mode = pm8901_vreg_get_mode, |
| 797 | }; |
| 798 | |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 799 | #define VREG_DESCRIP(_id, _name, _ops) \ |
| 800 | [_id] = { \ |
| 801 | .name = _name, \ |
| 802 | .id = _id, \ |
| 803 | .ops = _ops, \ |
| 804 | .type = REGULATOR_VOLTAGE, \ |
| 805 | .owner = THIS_MODULE, \ |
| 806 | } |
| 807 | |
| 808 | static struct regulator_desc pm8901_vreg_descrip[] = { |
| 809 | VREG_DESCRIP(PM8901_VREG_ID_L0, "8901_l0", &pm8901_ldo_ops), |
| 810 | VREG_DESCRIP(PM8901_VREG_ID_L1, "8901_l1", &pm8901_ldo_ops), |
| 811 | VREG_DESCRIP(PM8901_VREG_ID_L2, "8901_l2", &pm8901_ldo_ops), |
| 812 | VREG_DESCRIP(PM8901_VREG_ID_L3, "8901_l3", &pm8901_ldo_ops), |
| 813 | VREG_DESCRIP(PM8901_VREG_ID_L4, "8901_l4", &pm8901_ldo_ops), |
| 814 | VREG_DESCRIP(PM8901_VREG_ID_L5, "8901_l5", &pm8901_ldo_ops), |
| 815 | VREG_DESCRIP(PM8901_VREG_ID_L6, "8901_l6", &pm8901_ldo_ops), |
| 816 | |
| 817 | VREG_DESCRIP(PM8901_VREG_ID_S0, "8901_s0", &pm8901_smps_ops), |
| 818 | VREG_DESCRIP(PM8901_VREG_ID_S1, "8901_s1", &pm8901_smps_ops), |
| 819 | VREG_DESCRIP(PM8901_VREG_ID_S2, "8901_s2", &pm8901_smps_ops), |
| 820 | VREG_DESCRIP(PM8901_VREG_ID_S3, "8901_s3", &pm8901_smps_ops), |
| 821 | VREG_DESCRIP(PM8901_VREG_ID_S4, "8901_s4", &pm8901_smps_ops), |
| 822 | |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 823 | VREG_DESCRIP(PM8901_VREG_ID_LVS0, "8901_lvs0", &pm8901_vs_ops), |
| 824 | VREG_DESCRIP(PM8901_VREG_ID_LVS1, "8901_lvs1", &pm8901_vs_ops), |
| 825 | VREG_DESCRIP(PM8901_VREG_ID_LVS2, "8901_lvs2", &pm8901_vs_ops), |
| 826 | VREG_DESCRIP(PM8901_VREG_ID_LVS3, "8901_lvs3", &pm8901_vs_ops), |
| 827 | VREG_DESCRIP(PM8901_VREG_ID_MVS0, "8901_mvs0", &pm8901_vs_ops), |
| 828 | VREG_DESCRIP(PM8901_VREG_ID_USB_OTG, "8901_usb_otg", &pm8901_vs_ops), |
| 829 | VREG_DESCRIP(PM8901_VREG_ID_HDMI_MVS, "8901_hdmi_mvs", &pm8901_vs_ops), |
| 830 | }; |
| 831 | |
Anirudh Ghayal | 9f77e96 | 2011-12-06 12:38:21 +0530 | [diff] [blame] | 832 | static int pm8901_init_ldo(struct pm8901_vreg *vreg) |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 833 | { |
| 834 | int rc = 0, i; |
| 835 | u8 bank; |
| 836 | |
| 837 | /* Store current regulator register values. */ |
| 838 | for (i = 0; i < LDO_TEST_BANKS; i++) { |
| 839 | bank = REGULATOR_BANK_SEL(i); |
Anirudh Ghayal | 9f77e96 | 2011-12-06 12:38:21 +0530 | [diff] [blame] | 840 | rc = pm8xxx_writeb(vreg->dev->parent, vreg->test_addr, bank); |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 841 | if (rc) |
| 842 | goto bail; |
| 843 | |
Anirudh Ghayal | 9f77e96 | 2011-12-06 12:38:21 +0530 | [diff] [blame] | 844 | rc = pm8xxx_readb(vreg->dev->parent, vreg->test_addr, |
| 845 | &vreg->test_reg[i]); |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 846 | if (rc) |
| 847 | goto bail; |
| 848 | |
| 849 | vreg->test_reg[i] |= REGULATOR_BANK_WRITE; |
| 850 | } |
| 851 | |
| 852 | /* Set pull down enable based on platform data. */ |
Anirudh Ghayal | 9f77e96 | 2011-12-06 12:38:21 +0530 | [diff] [blame] | 853 | rc = pm8901_vreg_write(vreg, vreg->ctrl_addr, |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 854 | (vreg->pdata->pull_down_enable ? LDO_PULL_DOWN_ENABLE : 0), |
| 855 | LDO_PULL_DOWN_ENABLE_MASK, &vreg->ctrl_reg); |
| 856 | bail: |
| 857 | return rc; |
| 858 | } |
| 859 | |
Anirudh Ghayal | 9f77e96 | 2011-12-06 12:38:21 +0530 | [diff] [blame] | 860 | static int pm8901_init_smps(struct pm8901_vreg *vreg) |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 861 | { |
| 862 | int rc; |
| 863 | |
| 864 | /* Store current regulator register values. */ |
Anirudh Ghayal | 9f77e96 | 2011-12-06 12:38:21 +0530 | [diff] [blame] | 865 | rc = pm8xxx_readb(vreg->dev->parent, vreg->pfm_ctrl_addr, |
| 866 | &vreg->pfm_ctrl_reg); |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 867 | if (rc) |
| 868 | goto bail; |
| 869 | |
Anirudh Ghayal | 9f77e96 | 2011-12-06 12:38:21 +0530 | [diff] [blame] | 870 | rc = pm8xxx_readb(vreg->dev->parent, vreg->pwr_cnfg_addr, |
| 871 | &vreg->pwr_cnfg_reg); |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 872 | if (rc) |
| 873 | goto bail; |
| 874 | |
| 875 | /* Set pull down enable based on platform data. */ |
Anirudh Ghayal | 9f77e96 | 2011-12-06 12:38:21 +0530 | [diff] [blame] | 876 | rc = pm8901_vreg_write(vreg, vreg->pwr_cnfg_addr, |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 877 | (vreg->pdata->pull_down_enable ? SMPS_PULL_DOWN_ENABLE : 0), |
| 878 | SMPS_PULL_DOWN_ENABLE_MASK, &vreg->pwr_cnfg_reg); |
| 879 | |
| 880 | bail: |
| 881 | return rc; |
| 882 | } |
| 883 | |
Anirudh Ghayal | 9f77e96 | 2011-12-06 12:38:21 +0530 | [diff] [blame] | 884 | static int pm8901_init_vs(struct pm8901_vreg *vreg) |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 885 | { |
| 886 | int rc = 0; |
| 887 | |
| 888 | /* Set pull down enable based on platform data. */ |
Anirudh Ghayal | 9f77e96 | 2011-12-06 12:38:21 +0530 | [diff] [blame] | 889 | rc = pm8901_vreg_write(vreg, vreg->ctrl_addr, |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 890 | (vreg->pdata->pull_down_enable ? VS_PULL_DOWN_ENABLE : 0), |
| 891 | VS_PULL_DOWN_ENABLE_MASK, &vreg->ctrl_reg); |
| 892 | |
| 893 | return rc; |
| 894 | } |
| 895 | |
Anirudh Ghayal | 9f77e96 | 2011-12-06 12:38:21 +0530 | [diff] [blame] | 896 | static int pm8901_init_regulator(struct pm8901_vreg *vreg) |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 897 | { |
| 898 | int rc; |
| 899 | |
| 900 | /* Store current regulator register values. */ |
Anirudh Ghayal | 9f77e96 | 2011-12-06 12:38:21 +0530 | [diff] [blame] | 901 | rc = pm8xxx_readb(vreg->dev->parent, vreg->ctrl_addr, &vreg->ctrl_reg); |
| 902 | if (rc) |
| 903 | goto bail; |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 904 | |
Anirudh Ghayal | 9f77e96 | 2011-12-06 12:38:21 +0530 | [diff] [blame] | 905 | rc = pm8xxx_readb(vreg->dev->parent, vreg->pmr_addr, &vreg->pmr_reg); |
| 906 | if (rc) |
| 907 | goto bail; |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 908 | |
| 909 | /* Set initial mode based on hardware state. */ |
| 910 | if ((vreg->pmr_reg & VREG_PMR_STATE_MASK) == VREG_PMR_STATE_LPM) |
| 911 | vreg->optimum = REGULATOR_MODE_STANDBY; |
| 912 | else |
| 913 | vreg->optimum = REGULATOR_MODE_FAST; |
| 914 | |
| 915 | vreg->mode_initialized = 0; |
| 916 | |
| 917 | if (vreg->type == REGULATOR_TYPE_LDO) |
Anirudh Ghayal | 9f77e96 | 2011-12-06 12:38:21 +0530 | [diff] [blame] | 918 | rc = pm8901_init_ldo(vreg); |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 919 | else if (vreg->type == REGULATOR_TYPE_SMPS) |
Anirudh Ghayal | 9f77e96 | 2011-12-06 12:38:21 +0530 | [diff] [blame] | 920 | rc = pm8901_init_smps(vreg); |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 921 | else if (vreg->type == REGULATOR_TYPE_VS) |
Anirudh Ghayal | 9f77e96 | 2011-12-06 12:38:21 +0530 | [diff] [blame] | 922 | rc = pm8901_init_vs(vreg); |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 923 | bail: |
| 924 | if (rc) |
| 925 | pr_err("%s: pm8901_read/write failed; initial register states " |
| 926 | "unknown, rc=%d\n", __func__, rc); |
| 927 | |
| 928 | return rc; |
| 929 | } |
| 930 | |
| 931 | static int __devinit pm8901_vreg_probe(struct platform_device *pdev) |
| 932 | { |
| 933 | struct regulator_desc *rdesc; |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 934 | struct pm8901_vreg *vreg; |
| 935 | const char *reg_name = NULL; |
| 936 | int rc = 0; |
| 937 | |
| 938 | if (pdev == NULL) |
| 939 | return -EINVAL; |
| 940 | |
| 941 | if (pdev->id >= 0 && pdev->id < PM8901_VREG_MAX) { |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 942 | rdesc = &pm8901_vreg_descrip[pdev->id]; |
| 943 | vreg = &pm8901_vreg[pdev->id]; |
| 944 | vreg->pdata = pdev->dev.platform_data; |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 945 | reg_name = pm8901_vreg_descrip[pdev->id].name; |
Anirudh Ghayal | 9f77e96 | 2011-12-06 12:38:21 +0530 | [diff] [blame] | 946 | vreg->dev = &pdev->dev; |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 947 | |
Anirudh Ghayal | 9f77e96 | 2011-12-06 12:38:21 +0530 | [diff] [blame] | 948 | rc = pm8901_init_regulator(vreg); |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 949 | if (rc) |
| 950 | goto bail; |
| 951 | |
| 952 | /* Disallow idle and normal modes if pin control isn't set. */ |
| 953 | if (vreg->pdata->pin_ctrl == 0) |
| 954 | vreg->pdata->init_data.constraints.valid_modes_mask |
| 955 | &= ~(REGULATOR_MODE_NORMAL | REGULATOR_MODE_IDLE); |
| 956 | |
| 957 | vreg->rdev = regulator_register(rdesc, &pdev->dev, |
Rajendra Nayak | 11eafc6 | 2011-11-18 16:47:19 +0530 | [diff] [blame] | 958 | &vreg->pdata->init_data, vreg, NULL); |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 959 | if (IS_ERR(vreg->rdev)) { |
| 960 | rc = PTR_ERR(vreg->rdev); |
| 961 | pr_err("%s: regulator_register failed for %s, rc=%d\n", |
| 962 | __func__, reg_name, rc); |
| 963 | } |
| 964 | } else { |
| 965 | rc = -ENODEV; |
| 966 | } |
| 967 | |
| 968 | bail: |
| 969 | if (rc) |
| 970 | pr_err("%s: error for %s, rc=%d\n", __func__, reg_name, rc); |
| 971 | |
| 972 | return rc; |
| 973 | } |
| 974 | |
| 975 | static int __devexit pm8901_vreg_remove(struct platform_device *pdev) |
| 976 | { |
| 977 | regulator_unregister(pm8901_vreg[pdev->id].rdev); |
| 978 | return 0; |
| 979 | } |
| 980 | |
| 981 | static struct platform_driver pm8901_vreg_driver = { |
| 982 | .probe = pm8901_vreg_probe, |
| 983 | .remove = __devexit_p(pm8901_vreg_remove), |
| 984 | .driver = { |
| 985 | .name = "pm8901-regulator", |
| 986 | .owner = THIS_MODULE, |
| 987 | }, |
| 988 | }; |
| 989 | |
| 990 | static int __init pm8901_vreg_init(void) |
| 991 | { |
| 992 | return platform_driver_register(&pm8901_vreg_driver); |
| 993 | } |
| 994 | |
| 995 | static void __exit pm8901_vreg_exit(void) |
| 996 | { |
| 997 | platform_driver_unregister(&pm8901_vreg_driver); |
| 998 | } |
| 999 | |
| 1000 | static void print_write_error(struct pm8901_vreg *vreg, int rc, |
| 1001 | const char *func) |
| 1002 | { |
| 1003 | const char *reg_name = NULL; |
| 1004 | ptrdiff_t id = vreg - pm8901_vreg; |
| 1005 | |
| 1006 | if (id >= 0 && id < PM8901_VREG_MAX) |
| 1007 | reg_name = pm8901_vreg_descrip[id].name; |
| 1008 | pr_err("%s: pm8901_vreg_write failed for %s, rc=%d\n", |
| 1009 | func, reg_name, rc); |
| 1010 | } |
| 1011 | |
| 1012 | subsys_initcall(pm8901_vreg_init); |
| 1013 | module_exit(pm8901_vreg_exit); |
| 1014 | |
| 1015 | MODULE_LICENSE("GPL v2"); |
| 1016 | MODULE_DESCRIPTION("PMIC8901 regulator driver"); |
| 1017 | MODULE_VERSION("1.0"); |
| 1018 | MODULE_ALIAS("platform:pm8901-regulator"); |