blob: 16295cfd5e29d702684108f2a94829bdb20b9cf4 [file] [log] [blame]
Eric Miao49cbe782009-01-20 14:15:18 +08001#ifndef __ASM_MACH_IRQS_H
2#define __ASM_MACH_IRQS_H
3
4/*
5 * Interrupt numbers for PXA168
6 */
7#define IRQ_PXA168_NONE (-1)
8#define IRQ_PXA168_SSP3 0
9#define IRQ_PXA168_SSP2 1
10#define IRQ_PXA168_SSP1 2
11#define IRQ_PXA168_SSP0 3
12#define IRQ_PXA168_PMIC_INT 4
13#define IRQ_PXA168_RTC_INT 5
14#define IRQ_PXA168_RTC_ALARM 6
15#define IRQ_PXA168_TWSI0 7
16#define IRQ_PXA168_GPU 8
17#define IRQ_PXA168_KEYPAD 9
18#define IRQ_PXA168_ONEWIRE 12
19#define IRQ_PXA168_TIMER1 13
20#define IRQ_PXA168_TIMER2 14
21#define IRQ_PXA168_TIMER3 15
22#define IRQ_PXA168_CMU 16
23#define IRQ_PXA168_SSP4 17
24#define IRQ_PXA168_MSP_WAKEUP 19
25#define IRQ_PXA168_CF_WAKEUP 20
26#define IRQ_PXA168_XD_WAKEUP 21
27#define IRQ_PXA168_MFU 22
28#define IRQ_PXA168_MSP 23
29#define IRQ_PXA168_CF 24
30#define IRQ_PXA168_XD 25
31#define IRQ_PXA168_DDR_INT 26
32#define IRQ_PXA168_UART1 27
33#define IRQ_PXA168_UART2 28
34#define IRQ_PXA168_WDT 35
35#define IRQ_PXA168_FRQ_CHANGE 38
36#define IRQ_PXA168_SDH1 39
37#define IRQ_PXA168_SDH2 40
38#define IRQ_PXA168_LCD 41
39#define IRQ_PXA168_CI 42
40#define IRQ_PXA168_USB1 44
41#define IRQ_PXA168_NAND 45
42#define IRQ_PXA168_HIFI_DMA 46
43#define IRQ_PXA168_DMA_INT0 47
44#define IRQ_PXA168_DMA_INT1 48
45#define IRQ_PXA168_GPIOX 49
46#define IRQ_PXA168_USB2 51
47#define IRQ_PXA168_AC97 57
48#define IRQ_PXA168_TWSI1 58
49#define IRQ_PXA168_PMU 60
50#define IRQ_PXA168_SM_INT 63
51
Eric Miao14c6b5e2009-03-20 12:50:22 +080052/*
53 * Interrupt numbers for PXA910
54 */
Eric Miao2a55b912009-04-13 18:02:13 +080055#define IRQ_PXA910_NONE (-1)
Eric Miao14c6b5e2009-03-20 12:50:22 +080056#define IRQ_PXA910_AIRQ 0
57#define IRQ_PXA910_SSP3 1
58#define IRQ_PXA910_SSP2 2
59#define IRQ_PXA910_SSP1 3
60#define IRQ_PXA910_PMIC_INT 4
61#define IRQ_PXA910_RTC_INT 5
62#define IRQ_PXA910_RTC_ALARM 6
63#define IRQ_PXA910_TWSI0 7
64#define IRQ_PXA910_GPU 8
65#define IRQ_PXA910_KEYPAD 9
66#define IRQ_PXA910_ROTARY 10
67#define IRQ_PXA910_TRACKBALL 11
68#define IRQ_PXA910_ONEWIRE 12
69#define IRQ_PXA910_AP1_TIMER1 13
70#define IRQ_PXA910_AP1_TIMER2 14
71#define IRQ_PXA910_AP1_TIMER3 15
72#define IRQ_PXA910_IPC_AP0 16
73#define IRQ_PXA910_IPC_AP1 17
74#define IRQ_PXA910_IPC_AP2 18
75#define IRQ_PXA910_IPC_AP3 19
76#define IRQ_PXA910_IPC_AP4 20
77#define IRQ_PXA910_IPC_CP0 21
78#define IRQ_PXA910_IPC_CP1 22
79#define IRQ_PXA910_IPC_CP2 23
80#define IRQ_PXA910_IPC_CP3 24
81#define IRQ_PXA910_IPC_CP4 25
82#define IRQ_PXA910_L2_DDR 26
83#define IRQ_PXA910_UART2 27
84#define IRQ_PXA910_UART3 28
85#define IRQ_PXA910_AP2_TIMER1 29
86#define IRQ_PXA910_AP2_TIMER2 30
87#define IRQ_PXA910_CP2_TIMER1 31
88#define IRQ_PXA910_CP2_TIMER2 32
89#define IRQ_PXA910_CP2_TIMER3 33
90#define IRQ_PXA910_GSSP 34
91#define IRQ_PXA910_CP2_WDT 35
92#define IRQ_PXA910_MAIN_PMU 36
93#define IRQ_PXA910_CP_FREQ_CHG 37
94#define IRQ_PXA910_AP_FREQ_CHG 38
95#define IRQ_PXA910_MMC 39
96#define IRQ_PXA910_AEU 40
97#define IRQ_PXA910_LCD 41
98#define IRQ_PXA910_CCIC 42
99#define IRQ_PXA910_IRE 43
100#define IRQ_PXA910_USB1 44
101#define IRQ_PXA910_NAND 45
102#define IRQ_PXA910_HIFI_DMA 46
103#define IRQ_PXA910_DMA_INT0 47
104#define IRQ_PXA910_DMA_INT1 48
105#define IRQ_PXA910_AP_GPIO 49
106#define IRQ_PXA910_AP2_TIMER3 50
107#define IRQ_PXA910_USB2 51
108#define IRQ_PXA910_TWSI1 54
109#define IRQ_PXA910_CP_GPIO 55
110#define IRQ_PXA910_UART1 59 /* Slow UART */
111#define IRQ_PXA910_AP_PMU 60
112#define IRQ_PXA910_SM_INT 63 /* from PinMux */
113
Eric Miao49cbe782009-01-20 14:15:18 +0800114#define IRQ_GPIO_START 64
115#define IRQ_GPIO_NUM 128
116#define IRQ_GPIO(x) (IRQ_GPIO_START + (x))
117
118#define NR_IRQS (IRQ_GPIO_START + IRQ_GPIO_NUM)
119
120#endif /* __ASM_MACH_IRQS_H */