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Linus Torvalds1da177e2005-04-16 15:20:36 -07001/*
2 * PCI Express Hot Plug Controller Driver
3 *
4 * Copyright (C) 1995,2001 Compaq Computer Corporation
5 * Copyright (C) 2001 Greg Kroah-Hartman (greg@kroah.com)
6 * Copyright (C) 2001 IBM Corp.
7 * Copyright (C) 2003-2004 Intel Corporation
8 *
9 * All rights reserved.
10 *
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2 of the License, or (at
14 * your option) any later version.
15 *
16 * This program is distributed in the hope that it will be useful, but
17 * WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
19 * NON INFRINGEMENT. See the GNU General Public License for more
20 * details.
21 *
22 * You should have received a copy of the GNU General Public License
23 * along with this program; if not, write to the Free Software
24 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
25 *
Kristen Accardi8cf4c192005-08-16 15:16:10 -070026 * Send feedback to <greg@kroah.com>, <kristen.c.accardi@intel.com>
Linus Torvalds1da177e2005-04-16 15:20:36 -070027 *
28 */
29#ifndef _PCIEHP_H
30#define _PCIEHP_H
31
32#include <linux/types.h>
33#include <linux/pci.h>
34#include <linux/delay.h>
Tim Schmielaude259682006-01-08 01:02:05 -080035#include <linux/sched.h> /* signal_pending() */
Linus Torvalds1da177e2005-04-16 15:20:36 -070036#include <linux/pcieport_if.h>
Ingo Molnar6aa4cdd2006-01-13 16:02:15 +010037#include <linux/mutex.h>
Linus Torvalds1da177e2005-04-16 15:20:36 -070038#include "pci_hotplug.h"
39
40#define MY_NAME "pciehp"
41
42extern int pciehp_poll_mode;
43extern int pciehp_poll_time;
44extern int pciehp_debug;
rajesh.shah@intel.coma3a45ec2005-10-31 16:20:12 -080045extern int pciehp_force;
Linus Torvalds1da177e2005-04-16 15:20:36 -070046
47/*#define dbg(format, arg...) do { if (pciehp_debug) printk(KERN_DEBUG "%s: " format, MY_NAME , ## arg); } while (0)*/
48#define dbg(format, arg...) do { if (pciehp_debug) printk("%s: " format, MY_NAME , ## arg); } while (0)
49#define err(format, arg...) printk(KERN_ERR "%s: " format, MY_NAME , ## arg)
50#define info(format, arg...) printk(KERN_INFO "%s: " format, MY_NAME , ## arg)
51#define warn(format, arg...) printk(KERN_WARNING "%s: " format, MY_NAME , ## arg)
52
rajesh.shah@intel.coma8a2be92005-10-31 16:20:07 -080053struct hotplug_params {
54 u8 cache_line_size;
55 u8 latency_timer;
56 u8 enable_serr;
57 u8 enable_perr;
58};
59
Linus Torvalds1da177e2005-04-16 15:20:36 -070060struct slot {
61 struct slot *next;
62 u8 bus;
63 u8 device;
64 u32 number;
Linus Torvalds1da177e2005-04-16 15:20:36 -070065 u8 state;
Linus Torvalds1da177e2005-04-16 15:20:36 -070066 struct timer_list task_event;
67 u8 hp_slot;
68 struct controller *ctrl;
69 struct hpc_ops *hpc_ops;
70 struct hotplug_slot *hotplug_slot;
71 struct list_head slot_list;
72};
73
Linus Torvalds1da177e2005-04-16 15:20:36 -070074struct event_info {
75 u32 event_type;
76 u8 hp_slot;
77};
78
rajesh.shah@intel.comed6cbcf2005-10-31 16:20:09 -080079typedef u8(*php_intr_callback_t) (u8 hp_slot, void *instance_id);
80
81struct php_ctlr_state_s {
82 struct php_ctlr_state_s *pnext;
83 struct pci_dev *pci_dev;
84 unsigned int irq;
85 unsigned long flags; /* spinlock's */
86 u32 slot_device_offset;
87 u32 num_slots;
88 struct timer_list int_poll_timer; /* Added for poll event */
89 php_intr_callback_t attention_button_callback;
90 php_intr_callback_t switch_change_callback;
91 php_intr_callback_t presence_change_callback;
92 php_intr_callback_t power_fault_callback;
93 void *callback_instance_id;
94 struct ctrl_reg *creg; /* Ptr to controller register space */
95};
96
97#define MAX_EVENTS 10
Linus Torvalds1da177e2005-04-16 15:20:36 -070098struct controller {
99 struct controller *next;
Ingo Molnar6aa4cdd2006-01-13 16:02:15 +0100100 struct mutex crit_sect; /* critical section mutex */
rajesh.shah@intel.comed6cbcf2005-10-31 16:20:09 -0800101 struct php_ctlr_state_s *hpc_ctlr_handle; /* HPC controller handle */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700102 int num_slots; /* Number of slots on ctlr */
103 int slot_num_inc; /* 1 or -1 */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700104 struct pci_dev *pci_dev;
105 struct pci_bus *pci_bus;
rajesh.shah@intel.comed6cbcf2005-10-31 16:20:09 -0800106 struct event_info event_queue[MAX_EVENTS];
Linus Torvalds1da177e2005-04-16 15:20:36 -0700107 struct slot *slot;
108 struct hpc_ops *hpc_ops;
109 wait_queue_head_t queue; /* sleep & wake process */
110 u8 next_event;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700111 u8 bus;
112 u8 device;
113 u8 function;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700114 u8 slot_device_offset;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700115 u32 first_slot; /* First physical slot number */ /* PCIE only has 1 slot */
116 u8 slot_bus; /* Bus where the slots handled by this controller sit */
117 u8 ctrlcap;
118 u16 vendor_id;
Dely Sy8b245e42005-05-06 17:19:09 -0700119 u8 cap_base;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700120};
121
Linus Torvalds1da177e2005-04-16 15:20:36 -0700122#define INT_BUTTON_IGNORE 0
123#define INT_PRESENCE_ON 1
124#define INT_PRESENCE_OFF 2
125#define INT_SWITCH_CLOSE 3
126#define INT_SWITCH_OPEN 4
127#define INT_POWER_FAULT 5
128#define INT_POWER_FAULT_CLEAR 6
129#define INT_BUTTON_PRESS 7
130#define INT_BUTTON_RELEASE 8
131#define INT_BUTTON_CANCEL 9
132
133#define STATIC_STATE 0
134#define BLINKINGON_STATE 1
135#define BLINKINGOFF_STATE 2
136#define POWERON_STATE 3
137#define POWEROFF_STATE 4
138
139#define PCI_TO_PCI_BRIDGE_CLASS 0x00060400
140
141/* Error messages */
142#define INTERLOCK_OPEN 0x00000002
143#define ADD_NOT_SUPPORTED 0x00000003
144#define CARD_FUNCTIONING 0x00000005
145#define ADAPTER_NOT_SAME 0x00000006
146#define NO_ADAPTER_PRESENT 0x00000009
147#define NOT_ENOUGH_RESOURCES 0x0000000B
148#define DEVICE_TYPE_NOT_SUPPORTED 0x0000000C
149#define WRONG_BUS_FREQUENCY 0x0000000D
150#define POWER_FAILURE 0x0000000E
151
152#define REMOVE_NOT_SUPPORTED 0x00000003
153
154#define DISABLE_CARD 1
155
156/* Field definitions in Slot Capabilities Register */
157#define ATTN_BUTTN_PRSN 0x00000001
158#define PWR_CTRL_PRSN 0x00000002
159#define MRL_SENS_PRSN 0x00000004
160#define ATTN_LED_PRSN 0x00000008
161#define PWR_LED_PRSN 0x00000010
162#define HP_SUPR_RM_SUP 0x00000020
163
164#define ATTN_BUTTN(cap) (cap & ATTN_BUTTN_PRSN)
165#define POWER_CTRL(cap) (cap & PWR_CTRL_PRSN)
166#define MRL_SENS(cap) (cap & MRL_SENS_PRSN)
167#define ATTN_LED(cap) (cap & ATTN_LED_PRSN)
168#define PWR_LED(cap) (cap & PWR_LED_PRSN)
169#define HP_SUPR_RM(cap) (cap & HP_SUPR_RM_SUP)
170
171/*
172 * error Messages
173 */
174#define msg_initialization_err "Initialization failure, error=%d\n"
Linus Torvalds1da177e2005-04-16 15:20:36 -0700175#define msg_button_on "PCI slot #%d - powering on due to button press.\n"
176#define msg_button_off "PCI slot #%d - powering off due to button press.\n"
177#define msg_button_cancel "PCI slot #%d - action canceled due to button press.\n"
178#define msg_button_ignore "PCI slot #%d - button press ignored. (action in progress...)\n"
179
180/* controller functions */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700181extern int pciehp_event_start_thread (void);
182extern void pciehp_event_stop_thread (void);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700183extern int pciehp_enable_slot (struct slot *slot);
184extern int pciehp_disable_slot (struct slot *slot);
185
186extern u8 pciehp_handle_attention_button (u8 hp_slot, void *inst_id);
187extern u8 pciehp_handle_switch_change (u8 hp_slot, void *inst_id);
188extern u8 pciehp_handle_presence_change (u8 hp_slot, void *inst_id);
189extern u8 pciehp_handle_power_fault (u8 hp_slot, void *inst_id);
190/* extern void long_delay (int delay); */
191
Linus Torvalds1da177e2005-04-16 15:20:36 -0700192/* pci functions */
rajesh.shah@intel.comca22a5e2005-10-31 16:20:08 -0800193extern int pciehp_configure_device (struct slot *p_slot);
194extern int pciehp_unconfigure_device (struct slot *p_slot);
Rajesh Shah6560aa52005-11-07 13:37:36 -0800195extern int pciehp_get_hp_hw_control_from_firmware(struct pci_dev *dev);
196extern void pciehp_get_hp_params_from_firmware(struct pci_dev *dev,
rajesh.shah@intel.coma8a2be92005-10-31 16:20:07 -0800197 struct hotplug_params *hpp);
198
Linus Torvalds1da177e2005-04-16 15:20:36 -0700199
200
201/* Global variables */
202extern struct controller *pciehp_ctrl_list;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700203
204/* Inline functions */
205
206static inline struct slot *pciehp_find_slot(struct controller *ctrl, u8 device)
207{
208 struct slot *p_slot, *tmp_slot = NULL;
209
210 p_slot = ctrl->slot;
211
Linus Torvalds1da177e2005-04-16 15:20:36 -0700212 while (p_slot && (p_slot->device != device)) {
213 tmp_slot = p_slot;
214 p_slot = p_slot->next;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700215 }
216 if (p_slot == NULL) {
217 err("ERROR: pciehp_find_slot device=0x%x\n", device);
218 p_slot = tmp_slot;
219 }
220
221 return p_slot;
222}
223
224static inline int wait_for_ctrl_irq(struct controller *ctrl)
225{
226 int retval = 0;
227
228 DECLARE_WAITQUEUE(wait, current);
229
Linus Torvalds1da177e2005-04-16 15:20:36 -0700230 add_wait_queue(&ctrl->queue, &wait);
231 if (!pciehp_poll_mode)
232 /* Sleep for up to 1 second */
233 msleep_interruptible(1000);
234 else
235 msleep_interruptible(2500);
236
237 remove_wait_queue(&ctrl->queue, &wait);
238 if (signal_pending(current))
239 retval = -EINTR;
240
Linus Torvalds1da177e2005-04-16 15:20:36 -0700241 return retval;
242}
243
Linus Torvalds1da177e2005-04-16 15:20:36 -0700244#define SLOT_NAME_SIZE 10
245
246static inline void make_slot_name(char *buffer, int buffer_size, struct slot *slot)
247{
Kristen Accardi1248d632005-08-05 12:16:06 -0700248 snprintf(buffer, buffer_size, "%04d_%04d", slot->bus, slot->number);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700249}
250
251enum php_ctlr_type {
252 PCI,
253 ISA,
254 ACPI
255};
256
rajesh.shah@intel.comed6cbcf2005-10-31 16:20:09 -0800257int pcie_init(struct controller *ctrl, struct pcie_device *dev);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700258
259/* This has no meaning for PCI Express, as there is only 1 slot per port */
260int pcie_get_ctlr_slot_config(struct controller *ctrl,
261 int *num_ctlr_slots,
262 int *first_device_num,
263 int *physical_slot_num,
264 u8 *ctrlcap);
265
266struct hpc_ops {
267 int (*power_on_slot) (struct slot *slot);
268 int (*power_off_slot) (struct slot *slot);
269 int (*get_power_status) (struct slot *slot, u8 *status);
270 int (*get_attention_status) (struct slot *slot, u8 *status);
271 int (*set_attention_status) (struct slot *slot, u8 status);
272 int (*get_latch_status) (struct slot *slot, u8 *status);
273 int (*get_adapter_status) (struct slot *slot, u8 *status);
274
275 int (*get_max_bus_speed) (struct slot *slot, enum pci_bus_speed *speed);
276 int (*get_cur_bus_speed) (struct slot *slot, enum pci_bus_speed *speed);
277
278 int (*get_max_lnk_width) (struct slot *slot, enum pcie_link_width *value);
279 int (*get_cur_lnk_width) (struct slot *slot, enum pcie_link_width *value);
280
281 int (*query_power_fault) (struct slot *slot);
282 void (*green_led_on) (struct slot *slot);
283 void (*green_led_off) (struct slot *slot);
284 void (*green_led_blink) (struct slot *slot);
285 void (*release_ctlr) (struct controller *ctrl);
286 int (*check_lnk_status) (struct controller *ctrl);
287};
288
289#endif /* _PCIEHP_H */