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gerrit-public.fairphone.software / kernel / msm / 6caf2c8276d371679a798058e8fdf49f5ff831a3 / . / arch / arm / mach-lh7a40x / irq-lh7a404.c
blob: 122fadabc97d067c02543a324cf85809a9982d1a [file] [log] [blame]
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]1/* arch/arm/mach-lh7a40x/irq-lh7a404.c
2 *
3 * Copyright (C) 2004 Logic Product Development
4 *
5 * This program is free software; you can redistribute it and/or
6 * modify it under the terms of the GNU General Public License
7 * version 2 as published by the Free Software Foundation.
8 *
9 */
10
11#include <linux/init.h>
12#include <linux/module.h>
13#include <linux/interrupt.h>
14#include <linux/ptrace.h>
15
16#include <asm/hardware.h>
17#include <asm/irq.h>
18#include <asm/mach/irq.h>
19#include <asm/arch/irq.h>
20#include <asm/arch/irqs.h>
21
22#define USE_PRIORITIES
23
24/* See Documentation/arm/Sharp-LH/VectoredInterruptController for more
25 * information on using the vectored interrupt controller's
26 * prioritizing feature. */
27
28static unsigned char irq_pri_vic1[] = {
29#if defined (USE_PRIORITIES)
30IRQ_GPIO3INTR,
31#endif
32};
33static unsigned char irq_pri_vic2[] = {
34#if defined (USE_PRIORITIES)
35 IRQ_T3UI, IRQ_GPIO7INTR,
36 IRQ_UART1INTR, IRQ_UART2INTR, IRQ_UART3INTR,
37#endif
38};
39
40 /* CPU IRQ handling */
41
42static void lh7a404_vic1_mask_irq (u32 irq)
43{
44 VIC1_INTENCLR = (1 << irq);
45}
46
47static void lh7a404_vic1_unmask_irq (u32 irq)
48{
49 VIC1_INTEN = (1 << irq);
50}
51
52static void lh7a404_vic2_mask_irq (u32 irq)
53{
54 VIC2_INTENCLR = (1 << (irq - 32));
55}
56
57static void lh7a404_vic2_unmask_irq (u32 irq)
58{
59 VIC2_INTEN = (1 << (irq - 32));
60}
61
62static void lh7a404_vic1_ack_gpio_irq (u32 irq)
63{
64 GPIO_GPIOFEOI = (1 << IRQ_TO_GPIO (irq));
65 VIC1_INTENCLR = (1 << irq);
66}
67
68static void lh7a404_vic2_ack_gpio_irq (u32 irq)
69{
70 GPIO_GPIOFEOI = (1 << IRQ_TO_GPIO (irq));
71 VIC2_INTENCLR = (1 << irq);
72}
73
74static struct irqchip lh7a404_vic1_chip = {
75 .ack = lh7a404_vic1_mask_irq, /* Because level-triggered */
76 .mask = lh7a404_vic1_mask_irq,
77 .unmask = lh7a404_vic1_unmask_irq,
78};
79
80static struct irqchip lh7a404_vic2_chip = {
81 .ack = lh7a404_vic2_mask_irq, /* Because level-triggered */
82 .mask = lh7a404_vic2_mask_irq,
83 .unmask = lh7a404_vic2_unmask_irq,
84};
85
86static struct irqchip lh7a404_gpio_vic1_chip = {
87 .ack = lh7a404_vic1_ack_gpio_irq,
88 .mask = lh7a404_vic1_mask_irq,
89 .unmask = lh7a404_vic1_unmask_irq,
90};
91
92static struct irqchip lh7a404_gpio_vic2_chip = {
93 .ack = lh7a404_vic2_ack_gpio_irq,
94 .mask = lh7a404_vic2_mask_irq,
95 .unmask = lh7a404_vic2_unmask_irq,
96};
97
98 /* IRQ initialization */
99
100void __init lh7a404_init_irq (void)
101{
102 int irq;
103
104 VIC1_INTENCLR = 0xffffffff;
105 VIC2_INTENCLR = 0xffffffff;
106 VIC1_INTSEL = 0; /* All IRQs */
107 VIC2_INTSEL = 0; /* All IRQs */
108 VIC1_NVADDR = VA_VIC1DEFAULT;
109 VIC2_NVADDR = VA_VIC2DEFAULT;
110 VIC1_VECTADDR = 0;
111 VIC2_VECTADDR = 0;
112
113 GPIO_GPIOFINTEN = 0x00; /* Disable all GPIOF interrupts */
114 barrier ();
115
116 /* Install prioritized interrupts, if there are any. */
117 /* The | 0x20*/
118 for (irq = 0; irq < 16; ++irq) {
119 (&VIC1_VAD0)[irq]
120 = (irq < ARRAY_SIZE (irq_pri_vic1))
121 ? (irq_pri_vic1[irq] | VA_VECTORED) : 0;
122 (&VIC1_VECTCNTL0)[irq]
123 = (irq < ARRAY_SIZE (irq_pri_vic1))
124 ? (irq_pri_vic1[irq] | VIC_CNTL_ENABLE) : 0;
125 (&VIC2_VAD0)[irq]
126 = (irq < ARRAY_SIZE (irq_pri_vic2))
127 ? (irq_pri_vic2[irq] | VA_VECTORED) : 0;
128 (&VIC2_VECTCNTL0)[irq]
129 = (irq < ARRAY_SIZE (irq_pri_vic2))
130 ? (irq_pri_vic2[irq] | VIC_CNTL_ENABLE) : 0;
131 }
132
133 for (irq = 0; irq < NR_IRQS; ++irq) {
134 switch (irq) {
135 case IRQ_GPIO0INTR:
136 case IRQ_GPIO1INTR:
137 case IRQ_GPIO2INTR:
138 case IRQ_GPIO3INTR:
139 case IRQ_GPIO4INTR:
140 case IRQ_GPIO5INTR:
141 case IRQ_GPIO6INTR:
142 case IRQ_GPIO7INTR:
143 set_irq_chip (irq, irq < 32
144 ? &lh7a404_gpio_vic1_chip
145 : &lh7a404_gpio_vic2_chip);
146 set_irq_handler (irq, do_level_IRQ); /* OK default */
147 break;
148 default:
149 set_irq_chip (irq, irq < 32
150 ? &lh7a404_vic1_chip
151 : &lh7a404_vic2_chip);
152 set_irq_handler (irq, do_level_IRQ);
153 }
154 set_irq_flags (irq, IRQF_VALID);
155 }
156
157 lh7a40x_init_board_irq ();
158}