Kevin Hilman | a4768d2 | 2009-04-14 07:18:14 -0500 | [diff] [blame] | 1 | /* |
| 2 | * TI DAVINCI dma definitions |
| 3 | * |
| 4 | * Copyright (C) 2006-2009 Texas Instruments. |
| 5 | * |
| 6 | * This program is free software; you can redistribute it and/or modify it |
| 7 | * under the terms of the GNU General Public License as published by the |
| 8 | * Free Software Foundation; either version 2 of the License, or (at your |
| 9 | * option) any later version. |
| 10 | * |
| 11 | * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED |
| 12 | * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF |
| 13 | * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN |
| 14 | * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, |
| 15 | * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT |
| 16 | * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF |
| 17 | * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON |
| 18 | * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
| 19 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF |
| 20 | * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
| 21 | * |
| 22 | * You should have received a copy of the GNU General Public License along |
| 23 | * with this program; if not, write to the Free Software Foundation, Inc., |
| 24 | * 675 Mass Ave, Cambridge, MA 02139, USA. |
| 25 | * |
| 26 | */ |
| 27 | |
| 28 | /* |
| 29 | * This EDMA3 programming framework exposes two basic kinds of resource: |
| 30 | * |
| 31 | * Channel Triggers transfers, usually from a hardware event but |
| 32 | * also manually or by "chaining" from DMA completions. |
| 33 | * Each channel is coupled to a Parameter RAM (PaRAM) slot. |
| 34 | * |
| 35 | * Slot Each PaRAM slot holds a DMA transfer descriptor (PaRAM |
| 36 | * "set"), source and destination addresses, a link to a |
| 37 | * next PaRAM slot (if any), options for the transfer, and |
| 38 | * instructions for updating those addresses. There are |
| 39 | * more than twice as many slots as event channels. |
| 40 | * |
| 41 | * Each PaRAM set describes a sequence of transfers, either for one large |
| 42 | * buffer or for several discontiguous smaller buffers. An EDMA transfer |
| 43 | * is driven only from a channel, which performs the transfers specified |
| 44 | * in its PaRAM slot until there are no more transfers. When that last |
| 45 | * transfer completes, the "link" field may be used to reload the channel's |
| 46 | * PaRAM slot with a new transfer descriptor. |
| 47 | * |
| 48 | * The EDMA Channel Controller (CC) maps requests from channels into physical |
| 49 | * Transfer Controller (TC) requests when the channel triggers (by hardware |
| 50 | * or software events, or by chaining). The two physical DMA channels provided |
| 51 | * by the TCs are thus shared by many logical channels. |
| 52 | * |
| 53 | * DaVinci hardware also has a "QDMA" mechanism which is not currently |
| 54 | * supported through this interface. (DSP firmware uses it though.) |
| 55 | */ |
| 56 | |
| 57 | #ifndef EDMA_H_ |
| 58 | #define EDMA_H_ |
| 59 | |
| 60 | /* PaRAM slots are laid out like this */ |
| 61 | struct edmacc_param { |
| 62 | unsigned int opt; |
| 63 | unsigned int src; |
| 64 | unsigned int a_b_cnt; |
| 65 | unsigned int dst; |
| 66 | unsigned int src_dst_bidx; |
| 67 | unsigned int link_bcntrld; |
| 68 | unsigned int src_dst_cidx; |
| 69 | unsigned int ccnt; |
| 70 | }; |
| 71 | |
| 72 | #define CCINT0_INTERRUPT 16 |
| 73 | #define CCERRINT_INTERRUPT 17 |
| 74 | #define TCERRINT0_INTERRUPT 18 |
| 75 | #define TCERRINT1_INTERRUPT 19 |
| 76 | |
| 77 | /* fields in edmacc_param.opt */ |
| 78 | #define SAM BIT(0) |
| 79 | #define DAM BIT(1) |
| 80 | #define SYNCDIM BIT(2) |
| 81 | #define STATIC BIT(3) |
| 82 | #define EDMA_FWID (0x07 << 8) |
| 83 | #define TCCMODE BIT(11) |
| 84 | #define EDMA_TCC(t) ((t) << 12) |
| 85 | #define TCINTEN BIT(20) |
| 86 | #define ITCINTEN BIT(21) |
| 87 | #define TCCHEN BIT(22) |
| 88 | #define ITCCHEN BIT(23) |
| 89 | |
| 90 | #define TRWORD (0x7<<2) |
| 91 | #define PAENTRY (0x1ff<<5) |
| 92 | |
| 93 | /* Drivers should avoid using these symbolic names for dm644x |
| 94 | * channels, and use platform_device IORESOURCE_DMA resources |
| 95 | * instead. (Other DaVinci chips have different peripherals |
| 96 | * and thus have different DMA channel mappings.) |
| 97 | */ |
| 98 | #define DAVINCI_DMA_MCBSP_TX 2 |
| 99 | #define DAVINCI_DMA_MCBSP_RX 3 |
| 100 | #define DAVINCI_DMA_VPSS_HIST 4 |
| 101 | #define DAVINCI_DMA_VPSS_H3A 5 |
| 102 | #define DAVINCI_DMA_VPSS_PRVU 6 |
| 103 | #define DAVINCI_DMA_VPSS_RSZ 7 |
| 104 | #define DAVINCI_DMA_IMCOP_IMXINT 8 |
| 105 | #define DAVINCI_DMA_IMCOP_VLCDINT 9 |
| 106 | #define DAVINCI_DMA_IMCO_PASQINT 10 |
| 107 | #define DAVINCI_DMA_IMCOP_DSQINT 11 |
| 108 | #define DAVINCI_DMA_SPI_SPIX 16 |
| 109 | #define DAVINCI_DMA_SPI_SPIR 17 |
| 110 | #define DAVINCI_DMA_UART0_URXEVT0 18 |
| 111 | #define DAVINCI_DMA_UART0_UTXEVT0 19 |
| 112 | #define DAVINCI_DMA_UART1_URXEVT1 20 |
| 113 | #define DAVINCI_DMA_UART1_UTXEVT1 21 |
| 114 | #define DAVINCI_DMA_UART2_URXEVT2 22 |
| 115 | #define DAVINCI_DMA_UART2_UTXEVT2 23 |
| 116 | #define DAVINCI_DMA_MEMSTK_MSEVT 24 |
| 117 | #define DAVINCI_DMA_MMCRXEVT 26 |
| 118 | #define DAVINCI_DMA_MMCTXEVT 27 |
| 119 | #define DAVINCI_DMA_I2C_ICREVT 28 |
| 120 | #define DAVINCI_DMA_I2C_ICXEVT 29 |
| 121 | #define DAVINCI_DMA_GPIO_GPINT0 32 |
| 122 | #define DAVINCI_DMA_GPIO_GPINT1 33 |
| 123 | #define DAVINCI_DMA_GPIO_GPINT2 34 |
| 124 | #define DAVINCI_DMA_GPIO_GPINT3 35 |
| 125 | #define DAVINCI_DMA_GPIO_GPINT4 36 |
| 126 | #define DAVINCI_DMA_GPIO_GPINT5 37 |
| 127 | #define DAVINCI_DMA_GPIO_GPINT6 38 |
| 128 | #define DAVINCI_DMA_GPIO_GPINT7 39 |
| 129 | #define DAVINCI_DMA_GPIO_GPBNKINT0 40 |
| 130 | #define DAVINCI_DMA_GPIO_GPBNKINT1 41 |
| 131 | #define DAVINCI_DMA_GPIO_GPBNKINT2 42 |
| 132 | #define DAVINCI_DMA_GPIO_GPBNKINT3 43 |
| 133 | #define DAVINCI_DMA_GPIO_GPBNKINT4 44 |
| 134 | #define DAVINCI_DMA_TIMER0_TINT0 48 |
| 135 | #define DAVINCI_DMA_TIMER1_TINT1 49 |
| 136 | #define DAVINCI_DMA_TIMER2_TINT2 50 |
| 137 | #define DAVINCI_DMA_TIMER3_TINT3 51 |
| 138 | #define DAVINCI_DMA_PWM0 52 |
| 139 | #define DAVINCI_DMA_PWM1 53 |
| 140 | #define DAVINCI_DMA_PWM2 54 |
| 141 | |
Mark A. Greer | 55c79a4 | 2009-06-03 18:36:54 -0700 | [diff] [blame] | 142 | /* DA830 specific EDMA3 information */ |
| 143 | #define EDMA_DA830_NUM_DMACH 32 |
| 144 | #define EDMA_DA830_NUM_TCC 32 |
| 145 | #define EDMA_DA830_NUM_PARAMENTRY 128 |
| 146 | #define EDMA_DA830_NUM_EVQUE 2 |
| 147 | #define EDMA_DA830_NUM_TC 2 |
| 148 | #define EDMA_DA830_CHMAP_EXIST 0 |
| 149 | #define EDMA_DA830_NUM_REGIONS 4 |
| 150 | #define DA830_DMACH2EVENT_MAP0 0x000FC03Fu |
| 151 | #define DA830_DMACH2EVENT_MAP1 0x00000000u |
| 152 | #define DA830_EDMA_ARM_OWN 0x30FFCCFFu |
| 153 | |
| 154 | /* DA830 specific EDMA3 Events Information */ |
| 155 | enum DA830_edma_ch { |
| 156 | DA830_DMACH_MCASP0_RX, |
| 157 | DA830_DMACH_MCASP0_TX, |
| 158 | DA830_DMACH_MCASP1_RX, |
| 159 | DA830_DMACH_MCASP1_TX, |
| 160 | DA830_DMACH_MCASP2_RX, |
| 161 | DA830_DMACH_MCASP2_TX, |
| 162 | DA830_DMACH_GPIO_BNK0INT, |
| 163 | DA830_DMACH_GPIO_BNK1INT, |
| 164 | DA830_DMACH_UART0_RX, |
| 165 | DA830_DMACH_UART0_TX, |
| 166 | DA830_DMACH_TMR64P0_EVTOUT12, |
| 167 | DA830_DMACH_TMR64P0_EVTOUT34, |
| 168 | DA830_DMACH_UART1_RX, |
| 169 | DA830_DMACH_UART1_TX, |
| 170 | DA830_DMACH_SPI0_RX, |
| 171 | DA830_DMACH_SPI0_TX, |
| 172 | DA830_DMACH_MMCSD_RX, |
| 173 | DA830_DMACH_MMCSD_TX, |
| 174 | DA830_DMACH_SPI1_RX, |
| 175 | DA830_DMACH_SPI1_TX, |
| 176 | DA830_DMACH_DMAX_EVTOUT6, |
| 177 | DA830_DMACH_DMAX_EVTOUT7, |
| 178 | DA830_DMACH_GPIO_BNK2INT, |
| 179 | DA830_DMACH_GPIO_BNK3INT, |
| 180 | DA830_DMACH_I2C0_RX, |
| 181 | DA830_DMACH_I2C0_TX, |
| 182 | DA830_DMACH_I2C1_RX, |
| 183 | DA830_DMACH_I2C1_TX, |
| 184 | DA830_DMACH_GPIO_BNK4INT, |
| 185 | DA830_DMACH_GPIO_BNK5INT, |
| 186 | DA830_DMACH_UART2_RX, |
| 187 | DA830_DMACH_UART2_TX |
| 188 | }; |
| 189 | |
Kevin Hilman | a4768d2 | 2009-04-14 07:18:14 -0500 | [diff] [blame] | 190 | /*ch_status paramater of callback function possible values*/ |
| 191 | #define DMA_COMPLETE 1 |
| 192 | #define DMA_CC_ERROR 2 |
| 193 | #define DMA_TC1_ERROR 3 |
| 194 | #define DMA_TC2_ERROR 4 |
| 195 | |
| 196 | enum address_mode { |
| 197 | INCR = 0, |
| 198 | FIFO = 1 |
| 199 | }; |
| 200 | |
| 201 | enum fifo_width { |
| 202 | W8BIT = 0, |
| 203 | W16BIT = 1, |
| 204 | W32BIT = 2, |
| 205 | W64BIT = 3, |
| 206 | W128BIT = 4, |
| 207 | W256BIT = 5 |
| 208 | }; |
| 209 | |
| 210 | enum dma_event_q { |
| 211 | EVENTQ_0 = 0, |
| 212 | EVENTQ_1 = 1, |
Sandeep Paulraj | 10eef5a | 2009-07-27 08:50:16 -0400 | [diff] [blame] | 213 | EVENTQ_2 = 2, |
| 214 | EVENTQ_3 = 3, |
Kevin Hilman | a4768d2 | 2009-04-14 07:18:14 -0500 | [diff] [blame] | 215 | EVENTQ_DEFAULT = -1 |
| 216 | }; |
| 217 | |
| 218 | enum sync_dimension { |
| 219 | ASYNC = 0, |
| 220 | ABSYNC = 1 |
| 221 | }; |
| 222 | |
Sudhakar Rajashekhara | 60902a2 | 2009-05-21 07:41:35 -0400 | [diff] [blame] | 223 | #define EDMA_CTLR_CHAN(ctlr, chan) (((ctlr) << 16) | (chan)) |
| 224 | #define EDMA_CTLR(i) ((i) >> 16) |
| 225 | #define EDMA_CHAN_SLOT(i) ((i) & 0xffff) |
| 226 | |
Kevin Hilman | a4768d2 | 2009-04-14 07:18:14 -0500 | [diff] [blame] | 227 | #define EDMA_CHANNEL_ANY -1 /* for edma_alloc_channel() */ |
| 228 | #define EDMA_SLOT_ANY -1 /* for edma_alloc_slot() */ |
Sandeep Paulraj | 213765d | 2009-07-27 15:10:36 -0400 | [diff] [blame] | 229 | #define EDMA_CONT_PARAMS_ANY 1001 |
| 230 | #define EDMA_CONT_PARAMS_FIXED_EXACT 1002 |
| 231 | #define EDMA_CONT_PARAMS_FIXED_NOT_EXACT 1003 |
Kevin Hilman | a4768d2 | 2009-04-14 07:18:14 -0500 | [diff] [blame] | 232 | |
| 233 | /* alloc/free DMA channels and their dedicated parameter RAM slots */ |
| 234 | int edma_alloc_channel(int channel, |
| 235 | void (*callback)(unsigned channel, u16 ch_status, void *data), |
| 236 | void *data, enum dma_event_q); |
| 237 | void edma_free_channel(unsigned channel); |
| 238 | |
| 239 | /* alloc/free parameter RAM slots */ |
Sudhakar Rajashekhara | 60902a2 | 2009-05-21 07:41:35 -0400 | [diff] [blame] | 240 | int edma_alloc_slot(unsigned ctlr, int slot); |
Kevin Hilman | a4768d2 | 2009-04-14 07:18:14 -0500 | [diff] [blame] | 241 | void edma_free_slot(unsigned slot); |
| 242 | |
Sandeep Paulraj | 213765d | 2009-07-27 15:10:36 -0400 | [diff] [blame] | 243 | /* alloc/free a set of contiguous parameter RAM slots */ |
| 244 | int edma_alloc_cont_slots(unsigned ctlr, unsigned int id, int slot, int count); |
| 245 | int edma_free_cont_slots(unsigned slot, int count); |
| 246 | |
Kevin Hilman | a4768d2 | 2009-04-14 07:18:14 -0500 | [diff] [blame] | 247 | /* calls that operate on part of a parameter RAM slot */ |
| 248 | void edma_set_src(unsigned slot, dma_addr_t src_port, |
| 249 | enum address_mode mode, enum fifo_width); |
| 250 | void edma_set_dest(unsigned slot, dma_addr_t dest_port, |
| 251 | enum address_mode mode, enum fifo_width); |
| 252 | void edma_get_position(unsigned slot, dma_addr_t *src, dma_addr_t *dst); |
| 253 | void edma_set_src_index(unsigned slot, s16 src_bidx, s16 src_cidx); |
| 254 | void edma_set_dest_index(unsigned slot, s16 dest_bidx, s16 dest_cidx); |
| 255 | void edma_set_transfer_params(unsigned slot, u16 acnt, u16 bcnt, u16 ccnt, |
| 256 | u16 bcnt_rld, enum sync_dimension sync_mode); |
| 257 | void edma_link(unsigned from, unsigned to); |
| 258 | void edma_unlink(unsigned from); |
| 259 | |
| 260 | /* calls that operate on an entire parameter RAM slot */ |
| 261 | void edma_write_slot(unsigned slot, const struct edmacc_param *params); |
| 262 | void edma_read_slot(unsigned slot, struct edmacc_param *params); |
| 263 | |
| 264 | /* channel control operations */ |
| 265 | int edma_start(unsigned channel); |
| 266 | void edma_stop(unsigned channel); |
| 267 | void edma_clean_channel(unsigned channel); |
| 268 | void edma_clear_event(unsigned channel); |
| 269 | void edma_pause(unsigned channel); |
| 270 | void edma_resume(unsigned channel); |
| 271 | |
Kevin Hilman | a4768d2 | 2009-04-14 07:18:14 -0500 | [diff] [blame] | 272 | /* platform_data for EDMA driver */ |
| 273 | struct edma_soc_info { |
| 274 | |
| 275 | /* how many dma resources of each type */ |
| 276 | unsigned n_channel; |
| 277 | unsigned n_region; |
| 278 | unsigned n_slot; |
| 279 | unsigned n_tc; |
Sudhakar Rajashekhara | 60902a2 | 2009-05-21 07:41:35 -0400 | [diff] [blame] | 280 | unsigned n_cc; |
Sandeep Paulraj | a0f0202 | 2009-07-27 09:57:07 -0400 | [diff] [blame] | 281 | enum dma_event_q default_queue; |
Kevin Hilman | a4768d2 | 2009-04-14 07:18:14 -0500 | [diff] [blame] | 282 | |
Sudhakar Rajashekhara | 60902a2 | 2009-05-21 07:41:35 -0400 | [diff] [blame] | 283 | const s8 (*queue_tc_mapping)[2]; |
| 284 | const s8 (*queue_priority_mapping)[2]; |
Kevin Hilman | a4768d2 | 2009-04-14 07:18:14 -0500 | [diff] [blame] | 285 | }; |
| 286 | |
| 287 | #endif |