blob: 9623b852c616b4a3a27a6ef3277d03994960484a [file] [log] [blame]
Bartlomiej Zolnierkiewicza77dcc42009-02-02 20:12:23 +01001/*
2 * CS5536 PATA support
3 * (C) 2007 Martin K. Petersen <mkp@mkp.net>
4 * (C) 2009 Bartlomiej Zolnierkiewicz
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 *
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 *
19 * Documentation:
20 * Available from AMD web site.
21 *
22 * The IDE timing registers for the CS5536 live in the Geode Machine
23 * Specific Register file and not PCI config space. Most BIOSes
24 * virtualize the PCI registers so the chip looks like a standard IDE
25 * controller. Unfortunately not all implementations get this right.
26 * In particular some have problems with unaligned accesses to the
27 * virtualized PCI registers. This driver always does full dword
28 * writes to work around the issue. Also, in case of a bad BIOS this
29 * driver can be loaded with the "msr=1" parameter which forces using
30 * the Machine Specific Registers to configure the device.
31 */
32
33#include <linux/kernel.h>
34#include <linux/module.h>
35#include <linux/pci.h>
36#include <linux/init.h>
37#include <linux/ide.h>
38#include <asm/msr.h>
39
40#define DRV_NAME "cs5536"
41
42enum {
43 MSR_IDE_CFG = 0x51300010,
44 PCI_IDE_CFG = 0x40,
45
46 CFG = 0,
47 DTC = 2,
48 CAST = 3,
49 ETC = 4,
50
51 IDE_CFG_CHANEN = (1 << 1),
52 IDE_CFG_CABLE = (1 << 17) | (1 << 16),
53
54 IDE_D0_SHIFT = 24,
55 IDE_D1_SHIFT = 16,
56 IDE_DRV_MASK = 0xff,
57
58 IDE_CAST_D0_SHIFT = 6,
59 IDE_CAST_D1_SHIFT = 4,
60 IDE_CAST_DRV_MASK = 0x3,
61
62 IDE_CAST_CMD_SHIFT = 24,
63 IDE_CAST_CMD_MASK = 0xff,
64
65 IDE_ETC_UDMA_MASK = 0xc0,
66};
67
68static int use_msr;
69
70static int cs5536_read(struct pci_dev *pdev, int reg, u32 *val)
71{
72 if (unlikely(use_msr)) {
73 u32 dummy;
74
75 rdmsr(MSR_IDE_CFG + reg, *val, dummy);
76 return 0;
77 }
78
79 return pci_read_config_dword(pdev, PCI_IDE_CFG + reg * 4, val);
80}
81
82static int cs5536_write(struct pci_dev *pdev, int reg, int val)
83{
84 if (unlikely(use_msr)) {
85 wrmsr(MSR_IDE_CFG + reg, val, 0);
86 return 0;
87 }
88
89 return pci_write_config_dword(pdev, PCI_IDE_CFG + reg * 4, val);
90}
91
92static void cs5536_program_dtc(ide_drive_t *drive, u8 tim)
93{
94 struct pci_dev *pdev = to_pci_dev(drive->hwif->dev);
95 int dshift = (drive->dn & 1) ? IDE_D1_SHIFT : IDE_D0_SHIFT;
96 u32 dtc;
97
98 cs5536_read(pdev, DTC, &dtc);
99 dtc &= ~(IDE_DRV_MASK << dshift);
100 dtc |= tim << dshift;
101 cs5536_write(pdev, DTC, dtc);
102}
103
104/**
105 * cs5536_cable_detect - detect cable type
106 * @hwif: Port to detect on
107 *
108 * Perform cable detection for ATA66 capable cable.
109 *
110 * Returns a cable type.
111 */
112
113static u8 cs5536_cable_detect(ide_hwif_t *hwif)
114{
115 struct pci_dev *pdev = to_pci_dev(hwif->dev);
116 u32 cfg;
117
118 cs5536_read(pdev, CFG, &cfg);
119
120 if (cfg & IDE_CFG_CABLE)
121 return ATA_CBL_PATA80;
122 else
123 return ATA_CBL_PATA40;
124}
125
126/**
127 * cs5536_set_pio_mode - PIO timing setup
128 * @drive: ATA device
129 * @pio: PIO mode number
130 */
131
132static void cs5536_set_pio_mode(ide_drive_t *drive, const u8 pio)
133{
134 static const u8 drv_timings[5] = {
135 0x98, 0x55, 0x32, 0x21, 0x20,
136 };
137
138 static const u8 addr_timings[5] = {
139 0x2, 0x1, 0x0, 0x0, 0x0,
140 };
141
142 static const u8 cmd_timings[5] = {
143 0x99, 0x92, 0x90, 0x22, 0x20,
144 };
145
146 struct pci_dev *pdev = to_pci_dev(drive->hwif->dev);
147 ide_drive_t *pair = ide_get_pair_dev(drive);
148 int cshift = (drive->dn & 1) ? IDE_CAST_D1_SHIFT : IDE_CAST_D0_SHIFT;
Joao Ramos5bfb1512009-06-15 22:13:44 +0200149 unsigned long timings = (unsigned long)ide_get_drivedata(drive);
Bartlomiej Zolnierkiewicza77dcc42009-02-02 20:12:23 +0100150 u32 cast;
151 u8 cmd_pio = pio;
152
153 if (pair)
154 cmd_pio = min(pio, ide_get_best_pio_mode(pair, 255, 4));
155
Joao Ramos5bfb1512009-06-15 22:13:44 +0200156 timings &= (IDE_DRV_MASK << 8);
157 timings |= drv_timings[pio];
158 ide_set_drivedata(drive, (void *)timings);
Bartlomiej Zolnierkiewicza77dcc42009-02-02 20:12:23 +0100159
160 cs5536_program_dtc(drive, drv_timings[pio]);
161
162 cs5536_read(pdev, CAST, &cast);
163
164 cast &= ~(IDE_CAST_DRV_MASK << cshift);
165 cast |= addr_timings[pio] << cshift;
166
167 cast &= ~(IDE_CAST_CMD_MASK << IDE_CAST_CMD_SHIFT);
168 cast |= cmd_timings[cmd_pio] << IDE_CAST_CMD_SHIFT;
169
170 cs5536_write(pdev, CAST, cast);
171}
172
173/**
174 * cs5536_set_dma_mode - DMA timing setup
175 * @drive: ATA device
176 * @mode: DMA mode
177 */
178
179static void cs5536_set_dma_mode(ide_drive_t *drive, const u8 mode)
180{
181 static const u8 udma_timings[6] = {
182 0xc2, 0xc1, 0xc0, 0xc4, 0xc5, 0xc6,
183 };
184
185 static const u8 mwdma_timings[3] = {
186 0x67, 0x21, 0x20,
187 };
188
189 struct pci_dev *pdev = to_pci_dev(drive->hwif->dev);
190 int dshift = (drive->dn & 1) ? IDE_D1_SHIFT : IDE_D0_SHIFT;
Joao Ramos5bfb1512009-06-15 22:13:44 +0200191 unsigned long timings = (unsigned long)ide_get_drivedata(drive);
Bartlomiej Zolnierkiewicza77dcc42009-02-02 20:12:23 +0100192 u32 etc;
193
194 cs5536_read(pdev, ETC, &etc);
195
196 if (mode >= XFER_UDMA_0) {
197 etc &= ~(IDE_DRV_MASK << dshift);
198 etc |= udma_timings[mode - XFER_UDMA_0] << dshift;
199 } else { /* MWDMA */
200 etc &= ~(IDE_ETC_UDMA_MASK << dshift);
Joao Ramos5bfb1512009-06-15 22:13:44 +0200201 timings &= IDE_DRV_MASK;
202 timings |= mwdma_timings[mode - XFER_MW_DMA_0] << 8;
203 ide_set_drivedata(drive, (void *)timings);
Bartlomiej Zolnierkiewicza77dcc42009-02-02 20:12:23 +0100204 }
205
206 cs5536_write(pdev, ETC, etc);
207}
208
209static void cs5536_dma_start(ide_drive_t *drive)
210{
Joao Ramos5bfb1512009-06-15 22:13:44 +0200211 unsigned long timings = (unsigned long)ide_get_drivedata(drive);
212
Bartlomiej Zolnierkiewicza77dcc42009-02-02 20:12:23 +0100213 if (drive->current_speed < XFER_UDMA_0 &&
Joao Ramos5bfb1512009-06-15 22:13:44 +0200214 (timings >> 8) != (timings & IDE_DRV_MASK))
215 cs5536_program_dtc(drive, timings >> 8);
Bartlomiej Zolnierkiewicza77dcc42009-02-02 20:12:23 +0100216
217 ide_dma_start(drive);
218}
219
220static int cs5536_dma_end(ide_drive_t *drive)
221{
222 int ret = ide_dma_end(drive);
Joao Ramos5bfb1512009-06-15 22:13:44 +0200223 unsigned long timings = (unsigned long)ide_get_drivedata(drive);
Bartlomiej Zolnierkiewicza77dcc42009-02-02 20:12:23 +0100224
225 if (drive->current_speed < XFER_UDMA_0 &&
Joao Ramos5bfb1512009-06-15 22:13:44 +0200226 (timings >> 8) != (timings & IDE_DRV_MASK))
227 cs5536_program_dtc(drive, timings & IDE_DRV_MASK);
Bartlomiej Zolnierkiewicza77dcc42009-02-02 20:12:23 +0100228
229 return ret;
230}
231
232static const struct ide_port_ops cs5536_port_ops = {
233 .set_pio_mode = cs5536_set_pio_mode,
234 .set_dma_mode = cs5536_set_dma_mode,
235 .cable_detect = cs5536_cable_detect,
236};
237
238static const struct ide_dma_ops cs5536_dma_ops = {
239 .dma_host_set = ide_dma_host_set,
240 .dma_setup = ide_dma_setup,
Bartlomiej Zolnierkiewicza77dcc42009-02-02 20:12:23 +0100241 .dma_start = cs5536_dma_start,
242 .dma_end = cs5536_dma_end,
243 .dma_test_irq = ide_dma_test_irq,
244 .dma_lost_irq = ide_dma_lost_irq,
Bartlomiej Zolnierkiewicz22117d62009-03-27 12:46:47 +0100245 .dma_timer_expiry = ide_dma_sff_timer_expiry,
Sergei Shtylyov15da90b2009-04-18 17:42:20 +0200246 .dma_sff_read_status = ide_dma_sff_read_status,
Bartlomiej Zolnierkiewicza77dcc42009-02-02 20:12:23 +0100247};
248
249static const struct ide_port_info cs5536_info = {
250 .name = DRV_NAME,
251 .port_ops = &cs5536_port_ops,
252 .dma_ops = &cs5536_dma_ops,
253 .host_flags = IDE_HFLAG_SINGLE,
254 .pio_mask = ATA_PIO4,
255 .mwdma_mask = ATA_MWDMA2,
256 .udma_mask = ATA_UDMA5,
257};
258
259/**
260 * cs5536_init_one
261 * @dev: PCI device
262 * @id: Entry in match table
263 */
264
265static int cs5536_init_one(struct pci_dev *dev, const struct pci_device_id *id)
266{
267 u32 cfg;
268
269 if (use_msr)
270 printk(KERN_INFO DRV_NAME ": Using MSR regs instead of PCI\n");
271
272 cs5536_read(dev, CFG, &cfg);
273
274 if ((cfg & IDE_CFG_CHANEN) == 0) {
275 printk(KERN_ERR DRV_NAME ": disabled by BIOS\n");
276 return -ENODEV;
277 }
278
279 return ide_pci_init_one(dev, &cs5536_info, NULL);
280}
281
282static const struct pci_device_id cs5536_pci_tbl[] = {
283 { PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_CS5536_IDE), },
284 { },
285};
286
287static struct pci_driver cs5536_pci_driver = {
288 .name = DRV_NAME,
289 .id_table = cs5536_pci_tbl,
290 .probe = cs5536_init_one,
291 .remove = ide_pci_remove,
292 .suspend = ide_pci_suspend,
293 .resume = ide_pci_resume,
294};
295
296static int __init cs5536_init(void)
297{
298 return pci_register_driver(&cs5536_pci_driver);
299}
300
301static void __exit cs5536_exit(void)
302{
303 pci_unregister_driver(&cs5536_pci_driver);
304}
305
306MODULE_AUTHOR("Martin K. Petersen, Bartlomiej Zolnierkiewicz");
307MODULE_DESCRIPTION("low-level driver for the CS5536 IDE controller");
308MODULE_LICENSE("GPL");
309MODULE_DEVICE_TABLE(pci, cs5536_pci_tbl);
310
311module_param_named(msr, use_msr, int, 0644);
312MODULE_PARM_DESC(msr, "Force using MSR to configure IDE function (Default: 0)");
313
314module_init(cs5536_init);
315module_exit(cs5536_exit);