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Ben Dooks3ba81f32009-07-16 05:24:08 +00001/* drivers/net/ks8851.h
2 *
3 * Copyright 2009 Simtec Electronics
4 * Ben Dooks <ben@simtec.co.uk>
5 *
6 * KS8851 register definitions
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11*/
12
13#define KS_CCR 0x08
14#define CCR_EEPROM (1 << 9)
15#define CCR_SPI (1 << 8)
16#define CCR_32PIN (1 << 0)
17
18/* MAC address registers */
Ben Dooks160d0fa2009-10-19 23:49:04 +000019#define KS_MAR(_m) 0x15 - (_m)
Ben Dooks3ba81f32009-07-16 05:24:08 +000020#define KS_MARL 0x10
21#define KS_MARM 0x12
22#define KS_MARH 0x14
23
24#define KS_OBCR 0x20
25#define OBCR_ODS_16mA (1 << 6)
26
27#define KS_EEPCR 0x22
Sebastien Jana4bdfff2010-05-05 08:45:53 +000028#define EEPCR_EESRWA (1 << 5)
Ben Dooks3ba81f32009-07-16 05:24:08 +000029#define EEPCR_EESA (1 << 4)
Sebastien Jana4bdfff2010-05-05 08:45:53 +000030#define EEPCR_EESB_OFFSET 3
31#define EEPCR_EESB (1 << EEPCR_EESB_OFFSET)
Ben Dooks3ba81f32009-07-16 05:24:08 +000032#define EEPCR_EEDO (1 << 2)
33#define EEPCR_EESCK (1 << 1)
34#define EEPCR_EECS (1 << 0)
35
Sebastien Jana4bdfff2010-05-05 08:45:53 +000036#define EEPROM_OP_LEN 3 /* bits:*/
37#define EEPROM_OP_READ 0x06
38#define EEPROM_OP_EWEN 0x04
39#define EEPROM_OP_WRITE 0x05
40#define EEPROM_OP_EWDS 0x14
41
42#define EEPROM_DATA_LEN 16 /* 16 bits EEPROM */
43#define EEPROM_WRITE_TIME 4 /* wrt ack time in ms */
44#define EEPROM_SK_PERIOD 400 /* in us */
45
Ben Dooks3ba81f32009-07-16 05:24:08 +000046#define KS_MBIR 0x24
47#define MBIR_TXMBF (1 << 12)
48#define MBIR_TXMBFA (1 << 11)
49#define MBIR_RXMBF (1 << 4)
50#define MBIR_RXMBFA (1 << 3)
51
52#define KS_GRR 0x26
53#define GRR_QMU (1 << 1)
54#define GRR_GSR (1 << 0)
55
56#define KS_WFCR 0x2A
57#define WFCR_MPRXE (1 << 7)
58#define WFCR_WF3E (1 << 3)
59#define WFCR_WF2E (1 << 2)
60#define WFCR_WF1E (1 << 1)
61#define WFCR_WF0E (1 << 0)
62
63#define KS_WF0CRC0 0x30
64#define KS_WF0CRC1 0x32
65#define KS_WF0BM0 0x34
66#define KS_WF0BM1 0x36
67#define KS_WF0BM2 0x38
68#define KS_WF0BM3 0x3A
69
70#define KS_WF1CRC0 0x40
71#define KS_WF1CRC1 0x42
72#define KS_WF1BM0 0x44
73#define KS_WF1BM1 0x46
74#define KS_WF1BM2 0x48
75#define KS_WF1BM3 0x4A
76
77#define KS_WF2CRC0 0x50
78#define KS_WF2CRC1 0x52
79#define KS_WF2BM0 0x54
80#define KS_WF2BM1 0x56
81#define KS_WF2BM2 0x58
82#define KS_WF2BM3 0x5A
83
84#define KS_WF3CRC0 0x60
85#define KS_WF3CRC1 0x62
86#define KS_WF3BM0 0x64
87#define KS_WF3BM1 0x66
88#define KS_WF3BM2 0x68
89#define KS_WF3BM3 0x6A
90
91#define KS_TXCR 0x70
92#define TXCR_TCGICMP (1 << 8)
93#define TXCR_TCGUDP (1 << 7)
94#define TXCR_TCGTCP (1 << 6)
95#define TXCR_TCGIP (1 << 5)
96#define TXCR_FTXQ (1 << 4)
97#define TXCR_TXFCE (1 << 3)
98#define TXCR_TXPE (1 << 2)
99#define TXCR_TXCRC (1 << 1)
100#define TXCR_TXE (1 << 0)
101
102#define KS_TXSR 0x72
103#define TXSR_TXLC (1 << 13)
104#define TXSR_TXMC (1 << 12)
105#define TXSR_TXFID_MASK (0x3f << 0)
106#define TXSR_TXFID_SHIFT (0)
107#define TXSR_TXFID_GET(_v) (((_v) >> 0) & 0x3f)
108
109#define KS_RXCR1 0x74
110#define RXCR1_FRXQ (1 << 15)
111#define RXCR1_RXUDPFCC (1 << 14)
112#define RXCR1_RXTCPFCC (1 << 13)
113#define RXCR1_RXIPFCC (1 << 12)
114#define RXCR1_RXPAFMA (1 << 11)
115#define RXCR1_RXFCE (1 << 10)
116#define RXCR1_RXEFE (1 << 9)
117#define RXCR1_RXMAFMA (1 << 8)
118#define RXCR1_RXBE (1 << 7)
119#define RXCR1_RXME (1 << 6)
120#define RXCR1_RXUE (1 << 5)
121#define RXCR1_RXAE (1 << 4)
122#define RXCR1_RXINVF (1 << 1)
123#define RXCR1_RXE (1 << 0)
124
125#define KS_RXCR2 0x76
126#define RXCR2_SRDBL_MASK (0x7 << 5)
127#define RXCR2_SRDBL_SHIFT (5)
128#define RXCR2_SRDBL_4B (0x0 << 5)
129#define RXCR2_SRDBL_8B (0x1 << 5)
130#define RXCR2_SRDBL_16B (0x2 << 5)
131#define RXCR2_SRDBL_32B (0x3 << 5)
132#define RXCR2_SRDBL_FRAME (0x4 << 5)
133#define RXCR2_IUFFP (1 << 4)
134#define RXCR2_RXIUFCEZ (1 << 3)
135#define RXCR2_UDPLFE (1 << 2)
136#define RXCR2_RXICMPFCC (1 << 1)
137#define RXCR2_RXSAF (1 << 0)
138
139#define KS_TXMIR 0x78
140
141#define KS_RXFHSR 0x7C
142#define RXFSHR_RXFV (1 << 15)
143#define RXFSHR_RXICMPFCS (1 << 13)
144#define RXFSHR_RXIPFCS (1 << 12)
145#define RXFSHR_RXTCPFCS (1 << 11)
146#define RXFSHR_RXUDPFCS (1 << 10)
147#define RXFSHR_RXBF (1 << 7)
148#define RXFSHR_RXMF (1 << 6)
149#define RXFSHR_RXUF (1 << 5)
150#define RXFSHR_RXMR (1 << 4)
151#define RXFSHR_RXFT (1 << 3)
152#define RXFSHR_RXFTL (1 << 2)
153#define RXFSHR_RXRF (1 << 1)
154#define RXFSHR_RXCE (1 << 0)
155
156#define KS_RXFHBCR 0x7E
157#define KS_TXQCR 0x80
158#define TXQCR_AETFE (1 << 2)
159#define TXQCR_TXQMAM (1 << 1)
160#define TXQCR_METFE (1 << 0)
161
162#define KS_RXQCR 0x82
163#define RXQCR_RXDTTS (1 << 12)
164#define RXQCR_RXDBCTS (1 << 11)
165#define RXQCR_RXFCTS (1 << 10)
166#define RXQCR_RXIPHTOE (1 << 9)
167#define RXQCR_RXDTTE (1 << 7)
168#define RXQCR_RXDBCTE (1 << 6)
169#define RXQCR_RXFCTE (1 << 5)
170#define RXQCR_ADRFE (1 << 4)
171#define RXQCR_SDA (1 << 3)
172#define RXQCR_RRXEF (1 << 0)
173
174#define KS_TXFDPR 0x84
175#define TXFDPR_TXFPAI (1 << 14)
176#define TXFDPR_TXFP_MASK (0x7ff << 0)
177#define TXFDPR_TXFP_SHIFT (0)
178
179#define KS_RXFDPR 0x86
180#define RXFDPR_RXFPAI (1 << 14)
181
182#define KS_RXDTTR 0x8C
183#define KS_RXDBCTR 0x8E
184
185#define KS_IER 0x90
186#define KS_ISR 0x92
187#define IRQ_LCI (1 << 15)
188#define IRQ_TXI (1 << 14)
189#define IRQ_RXI (1 << 13)
190#define IRQ_RXOI (1 << 11)
191#define IRQ_TXPSI (1 << 9)
192#define IRQ_RXPSI (1 << 8)
193#define IRQ_TXSAI (1 << 6)
194#define IRQ_RXWFDI (1 << 5)
195#define IRQ_RXMPDI (1 << 4)
196#define IRQ_LDI (1 << 3)
197#define IRQ_EDI (1 << 2)
198#define IRQ_SPIBEI (1 << 1)
199#define IRQ_DEDI (1 << 0)
200
201#define KS_RXFCTR 0x9C
202#define KS_RXFC 0x9D
203#define RXFCTR_RXFC_MASK (0xff << 8)
204#define RXFCTR_RXFC_SHIFT (8)
205#define RXFCTR_RXFC_GET(_v) (((_v) >> 8) & 0xff)
206#define RXFCTR_RXFCT_MASK (0xff << 0)
207#define RXFCTR_RXFCT_SHIFT (0)
208
209#define KS_TXNTFSR 0x9E
210
211#define KS_MAHTR0 0xA0
212#define KS_MAHTR1 0xA2
213#define KS_MAHTR2 0xA4
214#define KS_MAHTR3 0xA6
215
216#define KS_FCLWR 0xB0
217#define KS_FCHWR 0xB2
218#define KS_FCOWR 0xB4
219
220#define KS_CIDER 0xC0
221#define CIDER_ID 0x8870
222#define CIDER_REV_MASK (0x7 << 1)
223#define CIDER_REV_SHIFT (1)
224#define CIDER_REV_GET(_v) (((_v) >> 1) & 0x7)
225
226#define KS_CGCR 0xC6
227
228#define KS_IACR 0xC8
229#define IACR_RDEN (1 << 12)
230#define IACR_TSEL_MASK (0x3 << 10)
231#define IACR_TSEL_SHIFT (10)
232#define IACR_TSEL_MIB (0x3 << 10)
233#define IACR_ADDR_MASK (0x1f << 0)
234#define IACR_ADDR_SHIFT (0)
235
236#define KS_IADLR 0xD0
237#define KS_IAHDR 0xD2
238
239#define KS_PMECR 0xD4
240#define PMECR_PME_DELAY (1 << 14)
241#define PMECR_PME_POL (1 << 12)
242#define PMECR_WOL_WAKEUP (1 << 11)
243#define PMECR_WOL_MAGICPKT (1 << 10)
244#define PMECR_WOL_LINKUP (1 << 9)
245#define PMECR_WOL_ENERGY (1 << 8)
246#define PMECR_AUTO_WAKE_EN (1 << 7)
247#define PMECR_WAKEUP_NORMAL (1 << 6)
248#define PMECR_WKEVT_MASK (0xf << 2)
249#define PMECR_WKEVT_SHIFT (2)
250#define PMECR_WKEVT_GET(_v) (((_v) >> 2) & 0xf)
251#define PMECR_WKEVT_ENERGY (0x1 << 2)
252#define PMECR_WKEVT_LINK (0x2 << 2)
253#define PMECR_WKEVT_MAGICPKT (0x4 << 2)
254#define PMECR_WKEVT_FRAME (0x8 << 2)
255#define PMECR_PM_MASK (0x3 << 0)
256#define PMECR_PM_SHIFT (0)
257#define PMECR_PM_NORMAL (0x0 << 0)
258#define PMECR_PM_ENERGY (0x1 << 0)
259#define PMECR_PM_SOFTDOWN (0x2 << 0)
260#define PMECR_PM_POWERSAVE (0x3 << 0)
261
262/* Standard MII PHY data */
263#define KS_P1MBCR 0xE4
264#define KS_P1MBSR 0xE6
265#define KS_PHY1ILR 0xE8
266#define KS_PHY1IHR 0xEA
267#define KS_P1ANAR 0xEC
268#define KS_P1ANLPR 0xEE
269
270#define KS_P1SCLMD 0xF4
271#define P1SCLMD_LEDOFF (1 << 15)
272#define P1SCLMD_TXIDS (1 << 14)
273#define P1SCLMD_RESTARTAN (1 << 13)
274#define P1SCLMD_DISAUTOMDIX (1 << 10)
275#define P1SCLMD_FORCEMDIX (1 << 9)
276#define P1SCLMD_AUTONEGEN (1 << 7)
277#define P1SCLMD_FORCE100 (1 << 6)
278#define P1SCLMD_FORCEFDX (1 << 5)
279#define P1SCLMD_ADV_FLOW (1 << 4)
280#define P1SCLMD_ADV_100BT_FDX (1 << 3)
281#define P1SCLMD_ADV_100BT_HDX (1 << 2)
282#define P1SCLMD_ADV_10BT_FDX (1 << 1)
283#define P1SCLMD_ADV_10BT_HDX (1 << 0)
284
285#define KS_P1CR 0xF6
286#define P1CR_HP_MDIX (1 << 15)
287#define P1CR_REV_POL (1 << 13)
288#define P1CR_OP_100M (1 << 10)
289#define P1CR_OP_FDX (1 << 9)
290#define P1CR_OP_MDI (1 << 7)
291#define P1CR_AN_DONE (1 << 6)
292#define P1CR_LINK_GOOD (1 << 5)
293#define P1CR_PNTR_FLOW (1 << 4)
294#define P1CR_PNTR_100BT_FDX (1 << 3)
295#define P1CR_PNTR_100BT_HDX (1 << 2)
296#define P1CR_PNTR_10BT_FDX (1 << 1)
297#define P1CR_PNTR_10BT_HDX (1 << 0)
298
299/* TX Frame control */
300
301#define TXFR_TXIC (1 << 15)
302#define TXFR_TXFID_MASK (0x3f << 0)
303#define TXFR_TXFID_SHIFT (0)
304
305/* SPI frame opcodes */
306#define KS_SPIOP_RD (0x00)
307#define KS_SPIOP_WR (0x40)
308#define KS_SPIOP_RXFIFO (0x80)
309#define KS_SPIOP_TXFIFO (0xC0)