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Haavard Skinnemoen89e57852006-11-09 14:51:17 +01001/*
2 * Atmel MACB Ethernet Controller driver
3 *
4 * Copyright (C) 2004-2006 Atmel Corporation
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 */
10#ifndef _MACB_H
11#define _MACB_H
12
13/* MACB register offsets */
14#define MACB_NCR 0x0000
15#define MACB_NCFGR 0x0004
16#define MACB_NSR 0x0008
17#define MACB_TSR 0x0014
18#define MACB_RBQP 0x0018
19#define MACB_TBQP 0x001c
20#define MACB_RSR 0x0020
21#define MACB_ISR 0x0024
22#define MACB_IER 0x0028
23#define MACB_IDR 0x002c
24#define MACB_IMR 0x0030
25#define MACB_MAN 0x0034
26#define MACB_PTR 0x0038
27#define MACB_PFR 0x003c
28#define MACB_FTO 0x0040
29#define MACB_SCF 0x0044
30#define MACB_MCF 0x0048
31#define MACB_FRO 0x004c
32#define MACB_FCSE 0x0050
33#define MACB_ALE 0x0054
34#define MACB_DTF 0x0058
35#define MACB_LCOL 0x005c
36#define MACB_EXCOL 0x0060
37#define MACB_TUND 0x0064
38#define MACB_CSE 0x0068
39#define MACB_RRE 0x006c
40#define MACB_ROVR 0x0070
41#define MACB_RSE 0x0074
42#define MACB_ELE 0x0078
43#define MACB_RJA 0x007c
44#define MACB_USF 0x0080
45#define MACB_STE 0x0084
46#define MACB_RLE 0x0088
47#define MACB_TPF 0x008c
48#define MACB_HRB 0x0090
49#define MACB_HRT 0x0094
50#define MACB_SA1B 0x0098
51#define MACB_SA1T 0x009c
52#define MACB_SA2B 0x00a0
53#define MACB_SA2T 0x00a4
54#define MACB_SA3B 0x00a8
55#define MACB_SA3T 0x00ac
56#define MACB_SA4B 0x00b0
57#define MACB_SA4T 0x00b4
58#define MACB_TID 0x00b8
59#define MACB_TPQ 0x00bc
60#define MACB_USRIO 0x00c0
61#define MACB_WOL 0x00c4
62
63/* Bitfields in NCR */
64#define MACB_LB_OFFSET 0
65#define MACB_LB_SIZE 1
66#define MACB_LLB_OFFSET 1
67#define MACB_LLB_SIZE 1
68#define MACB_RE_OFFSET 2
69#define MACB_RE_SIZE 1
70#define MACB_TE_OFFSET 3
71#define MACB_TE_SIZE 1
72#define MACB_MPE_OFFSET 4
73#define MACB_MPE_SIZE 1
74#define MACB_CLRSTAT_OFFSET 5
75#define MACB_CLRSTAT_SIZE 1
76#define MACB_INCSTAT_OFFSET 6
77#define MACB_INCSTAT_SIZE 1
78#define MACB_WESTAT_OFFSET 7
79#define MACB_WESTAT_SIZE 1
80#define MACB_BP_OFFSET 8
81#define MACB_BP_SIZE 1
82#define MACB_TSTART_OFFSET 9
83#define MACB_TSTART_SIZE 1
84#define MACB_THALT_OFFSET 10
85#define MACB_THALT_SIZE 1
86#define MACB_NCR_TPF_OFFSET 11
87#define MACB_NCR_TPF_SIZE 1
88#define MACB_TZQ_OFFSET 12
89#define MACB_TZQ_SIZE 1
90
91/* Bitfields in NCFGR */
92#define MACB_SPD_OFFSET 0
93#define MACB_SPD_SIZE 1
94#define MACB_FD_OFFSET 1
95#define MACB_FD_SIZE 1
96#define MACB_BIT_RATE_OFFSET 2
97#define MACB_BIT_RATE_SIZE 1
98#define MACB_JFRAME_OFFSET 3
99#define MACB_JFRAME_SIZE 1
100#define MACB_CAF_OFFSET 4
101#define MACB_CAF_SIZE 1
102#define MACB_NBC_OFFSET 5
103#define MACB_NBC_SIZE 1
104#define MACB_NCFGR_MTI_OFFSET 6
105#define MACB_NCFGR_MTI_SIZE 1
106#define MACB_UNI_OFFSET 7
107#define MACB_UNI_SIZE 1
108#define MACB_BIG_OFFSET 8
109#define MACB_BIG_SIZE 1
110#define MACB_EAE_OFFSET 9
111#define MACB_EAE_SIZE 1
112#define MACB_CLK_OFFSET 10
113#define MACB_CLK_SIZE 2
114#define MACB_RTY_OFFSET 12
115#define MACB_RTY_SIZE 1
116#define MACB_PAE_OFFSET 13
117#define MACB_PAE_SIZE 1
118#define MACB_RBOF_OFFSET 14
119#define MACB_RBOF_SIZE 2
120#define MACB_RLCE_OFFSET 16
121#define MACB_RLCE_SIZE 1
122#define MACB_DRFCS_OFFSET 17
123#define MACB_DRFCS_SIZE 1
124#define MACB_EFRHD_OFFSET 18
125#define MACB_EFRHD_SIZE 1
126#define MACB_IRXFCS_OFFSET 19
127#define MACB_IRXFCS_SIZE 1
128
129/* Bitfields in NSR */
130#define MACB_NSR_LINK_OFFSET 0
131#define MACB_NSR_LINK_SIZE 1
132#define MACB_MDIO_OFFSET 1
133#define MACB_MDIO_SIZE 1
134#define MACB_IDLE_OFFSET 2
135#define MACB_IDLE_SIZE 1
136
137/* Bitfields in TSR */
138#define MACB_UBR_OFFSET 0
139#define MACB_UBR_SIZE 1
140#define MACB_COL_OFFSET 1
141#define MACB_COL_SIZE 1
142#define MACB_TSR_RLE_OFFSET 2
143#define MACB_TSR_RLE_SIZE 1
144#define MACB_TGO_OFFSET 3
145#define MACB_TGO_SIZE 1
146#define MACB_BEX_OFFSET 4
147#define MACB_BEX_SIZE 1
148#define MACB_COMP_OFFSET 5
149#define MACB_COMP_SIZE 1
150#define MACB_UND_OFFSET 6
151#define MACB_UND_SIZE 1
152
153/* Bitfields in RSR */
154#define MACB_BNA_OFFSET 0
155#define MACB_BNA_SIZE 1
156#define MACB_REC_OFFSET 1
157#define MACB_REC_SIZE 1
158#define MACB_OVR_OFFSET 2
159#define MACB_OVR_SIZE 1
160
161/* Bitfields in ISR/IER/IDR/IMR */
162#define MACB_MFD_OFFSET 0
163#define MACB_MFD_SIZE 1
164#define MACB_RCOMP_OFFSET 1
165#define MACB_RCOMP_SIZE 1
166#define MACB_RXUBR_OFFSET 2
167#define MACB_RXUBR_SIZE 1
168#define MACB_TXUBR_OFFSET 3
169#define MACB_TXUBR_SIZE 1
170#define MACB_ISR_TUND_OFFSET 4
171#define MACB_ISR_TUND_SIZE 1
172#define MACB_ISR_RLE_OFFSET 5
173#define MACB_ISR_RLE_SIZE 1
174#define MACB_TXERR_OFFSET 6
175#define MACB_TXERR_SIZE 1
176#define MACB_TCOMP_OFFSET 7
177#define MACB_TCOMP_SIZE 1
178#define MACB_ISR_LINK_OFFSET 9
179#define MACB_ISR_LINK_SIZE 1
180#define MACB_ISR_ROVR_OFFSET 10
181#define MACB_ISR_ROVR_SIZE 1
182#define MACB_HRESP_OFFSET 11
183#define MACB_HRESP_SIZE 1
184#define MACB_PFR_OFFSET 12
185#define MACB_PFR_SIZE 1
186#define MACB_PTZ_OFFSET 13
187#define MACB_PTZ_SIZE 1
188
189/* Bitfields in MAN */
190#define MACB_DATA_OFFSET 0
191#define MACB_DATA_SIZE 16
192#define MACB_CODE_OFFSET 16
193#define MACB_CODE_SIZE 2
194#define MACB_REGA_OFFSET 18
195#define MACB_REGA_SIZE 5
196#define MACB_PHYA_OFFSET 23
197#define MACB_PHYA_SIZE 5
198#define MACB_RW_OFFSET 28
199#define MACB_RW_SIZE 2
200#define MACB_SOF_OFFSET 30
201#define MACB_SOF_SIZE 2
202
Andrew Victor0cc86742007-02-07 16:40:44 +0100203/* Bitfields in USRIO (AVR32) */
Haavard Skinnemoen89e57852006-11-09 14:51:17 +0100204#define MACB_MII_OFFSET 0
205#define MACB_MII_SIZE 1
206#define MACB_EAM_OFFSET 1
207#define MACB_EAM_SIZE 1
208#define MACB_TX_PAUSE_OFFSET 2
209#define MACB_TX_PAUSE_SIZE 1
210#define MACB_TX_PAUSE_ZERO_OFFSET 3
211#define MACB_TX_PAUSE_ZERO_SIZE 1
212
Andrew Victor0cc86742007-02-07 16:40:44 +0100213/* Bitfields in USRIO (AT91) */
214#define MACB_RMII_OFFSET 0
215#define MACB_RMII_SIZE 1
216#define MACB_CLKEN_OFFSET 1
217#define MACB_CLKEN_SIZE 1
218
Haavard Skinnemoen89e57852006-11-09 14:51:17 +0100219/* Bitfields in WOL */
220#define MACB_IP_OFFSET 0
221#define MACB_IP_SIZE 16
222#define MACB_MAG_OFFSET 16
223#define MACB_MAG_SIZE 1
224#define MACB_ARP_OFFSET 17
225#define MACB_ARP_SIZE 1
226#define MACB_SA1_OFFSET 18
227#define MACB_SA1_SIZE 1
228#define MACB_WOL_MTI_OFFSET 19
229#define MACB_WOL_MTI_SIZE 1
230
231/* Constants for CLK */
232#define MACB_CLK_DIV8 0
233#define MACB_CLK_DIV16 1
234#define MACB_CLK_DIV32 2
235#define MACB_CLK_DIV64 3
236
237/* Constants for MAN register */
238#define MACB_MAN_SOF 1
239#define MACB_MAN_WRITE 1
240#define MACB_MAN_READ 2
241#define MACB_MAN_CODE 2
242
243/* Bit manipulation macros */
244#define MACB_BIT(name) \
245 (1 << MACB_##name##_OFFSET)
246#define MACB_BF(name,value) \
247 (((value) & ((1 << MACB_##name##_SIZE) - 1)) \
248 << MACB_##name##_OFFSET)
249#define MACB_BFEXT(name,value)\
250 (((value) >> MACB_##name##_OFFSET) \
251 & ((1 << MACB_##name##_SIZE) - 1))
252#define MACB_BFINS(name,value,old) \
253 (((old) & ~(((1 << MACB_##name##_SIZE) - 1) \
254 << MACB_##name##_OFFSET)) \
255 | MACB_BF(name,value))
256
257/* Register access macros */
258#define macb_readl(port,reg) \
Haavard Skinnemoen0f0d84e2006-12-08 14:38:30 +0100259 __raw_readl((port)->regs + MACB_##reg)
Haavard Skinnemoen89e57852006-11-09 14:51:17 +0100260#define macb_writel(port,reg,value) \
Haavard Skinnemoen0f0d84e2006-12-08 14:38:30 +0100261 __raw_writel((value), (port)->regs + MACB_##reg)
Haavard Skinnemoen89e57852006-11-09 14:51:17 +0100262
263struct dma_desc {
264 u32 addr;
265 u32 ctrl;
266};
267
268/* DMA descriptor bitfields */
269#define MACB_RX_USED_OFFSET 0
270#define MACB_RX_USED_SIZE 1
271#define MACB_RX_WRAP_OFFSET 1
272#define MACB_RX_WRAP_SIZE 1
273#define MACB_RX_WADDR_OFFSET 2
274#define MACB_RX_WADDR_SIZE 30
275
276#define MACB_RX_FRMLEN_OFFSET 0
277#define MACB_RX_FRMLEN_SIZE 12
278#define MACB_RX_OFFSET_OFFSET 12
279#define MACB_RX_OFFSET_SIZE 2
280#define MACB_RX_SOF_OFFSET 14
281#define MACB_RX_SOF_SIZE 1
282#define MACB_RX_EOF_OFFSET 15
283#define MACB_RX_EOF_SIZE 1
284#define MACB_RX_CFI_OFFSET 16
285#define MACB_RX_CFI_SIZE 1
286#define MACB_RX_VLAN_PRI_OFFSET 17
287#define MACB_RX_VLAN_PRI_SIZE 3
288#define MACB_RX_PRI_TAG_OFFSET 20
289#define MACB_RX_PRI_TAG_SIZE 1
290#define MACB_RX_VLAN_TAG_OFFSET 21
291#define MACB_RX_VLAN_TAG_SIZE 1
292#define MACB_RX_TYPEID_MATCH_OFFSET 22
293#define MACB_RX_TYPEID_MATCH_SIZE 1
294#define MACB_RX_SA4_MATCH_OFFSET 23
295#define MACB_RX_SA4_MATCH_SIZE 1
296#define MACB_RX_SA3_MATCH_OFFSET 24
297#define MACB_RX_SA3_MATCH_SIZE 1
298#define MACB_RX_SA2_MATCH_OFFSET 25
299#define MACB_RX_SA2_MATCH_SIZE 1
300#define MACB_RX_SA1_MATCH_OFFSET 26
301#define MACB_RX_SA1_MATCH_SIZE 1
302#define MACB_RX_EXT_MATCH_OFFSET 28
303#define MACB_RX_EXT_MATCH_SIZE 1
304#define MACB_RX_UHASH_MATCH_OFFSET 29
305#define MACB_RX_UHASH_MATCH_SIZE 1
306#define MACB_RX_MHASH_MATCH_OFFSET 30
307#define MACB_RX_MHASH_MATCH_SIZE 1
308#define MACB_RX_BROADCAST_OFFSET 31
309#define MACB_RX_BROADCAST_SIZE 1
310
311#define MACB_TX_FRMLEN_OFFSET 0
312#define MACB_TX_FRMLEN_SIZE 11
313#define MACB_TX_LAST_OFFSET 15
314#define MACB_TX_LAST_SIZE 1
315#define MACB_TX_NOCRC_OFFSET 16
316#define MACB_TX_NOCRC_SIZE 1
317#define MACB_TX_BUF_EXHAUSTED_OFFSET 27
318#define MACB_TX_BUF_EXHAUSTED_SIZE 1
319#define MACB_TX_UNDERRUN_OFFSET 28
320#define MACB_TX_UNDERRUN_SIZE 1
321#define MACB_TX_ERROR_OFFSET 29
322#define MACB_TX_ERROR_SIZE 1
323#define MACB_TX_WRAP_OFFSET 30
324#define MACB_TX_WRAP_SIZE 1
325#define MACB_TX_USED_OFFSET 31
326#define MACB_TX_USED_SIZE 1
327
328struct ring_info {
329 struct sk_buff *skb;
330 dma_addr_t mapping;
331};
332
333/*
334 * Hardware-collected statistics. Used when updating the network
335 * device stats by a periodic timer.
336 */
337struct macb_stats {
338 u32 rx_pause_frames;
339 u32 tx_ok;
340 u32 tx_single_cols;
341 u32 tx_multiple_cols;
342 u32 rx_ok;
343 u32 rx_fcs_errors;
344 u32 rx_align_errors;
345 u32 tx_deferred;
346 u32 tx_late_cols;
347 u32 tx_excessive_cols;
348 u32 tx_underruns;
349 u32 tx_carrier_errors;
350 u32 rx_resource_errors;
351 u32 rx_overruns;
352 u32 rx_symbol_errors;
353 u32 rx_oversize_pkts;
354 u32 rx_jabbers;
355 u32 rx_undersize_pkts;
356 u32 sqe_test_errors;
357 u32 rx_length_mismatch;
358 u32 tx_pause_frames;
359};
360
361struct macb {
362 void __iomem *regs;
363
364 unsigned int rx_tail;
365 struct dma_desc *rx_ring;
366 void *rx_buffers;
367
368 unsigned int tx_head, tx_tail;
369 struct dma_desc *tx_ring;
370 struct ring_info *tx_skb;
371
372 spinlock_t lock;
373 struct platform_device *pdev;
374 struct clk *pclk;
375 struct clk *hclk;
376 struct net_device *dev;
Stephen Hemmingerbea33482007-10-03 16:41:36 -0700377 struct napi_struct napi;
Haavard Skinnemoen89e57852006-11-09 14:51:17 +0100378 struct net_device_stats stats;
379 struct macb_stats hw_stats;
380
381 dma_addr_t rx_ring_dma;
382 dma_addr_t tx_ring_dma;
383 dma_addr_t rx_buffers_dma;
384
385 unsigned int rx_pending, tx_pending;
386
Lennert Buytenhek298cf9b2008-10-08 16:29:57 -0700387 struct mii_bus *mii_bus;
frederic RODO6c36a702007-07-12 19:07:24 +0200388 struct phy_device *phy_dev;
389 unsigned int link;
390 unsigned int speed;
391 unsigned int duplex;
Haavard Skinnemoen89e57852006-11-09 14:51:17 +0100392};
393
394#endif /* _MACB_H */