Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1 | /* |
| 2 | * Code to handle IP32 IRQs |
| 3 | * |
| 4 | * This file is subject to the terms and conditions of the GNU General Public |
| 5 | * License. See the file "COPYING" in the main directory of this archive |
| 6 | * for more details. |
| 7 | * |
| 8 | * Copyright (C) 2000 Harald Koerfgen |
| 9 | * Copyright (C) 2001 Keith M Wesolowski |
| 10 | */ |
| 11 | #include <linux/init.h> |
| 12 | #include <linux/kernel_stat.h> |
| 13 | #include <linux/types.h> |
| 14 | #include <linux/interrupt.h> |
| 15 | #include <linux/irq.h> |
| 16 | #include <linux/bitops.h> |
| 17 | #include <linux/kernel.h> |
| 18 | #include <linux/slab.h> |
| 19 | #include <linux/mm.h> |
| 20 | #include <linux/random.h> |
| 21 | #include <linux/sched.h> |
| 22 | |
Ralf Baechle | dd67b15 | 2007-10-14 14:02:26 +0100 | [diff] [blame] | 23 | #include <asm/irq_cpu.h> |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 24 | #include <asm/mipsregs.h> |
| 25 | #include <asm/signal.h> |
| 26 | #include <asm/system.h> |
| 27 | #include <asm/time.h> |
| 28 | #include <asm/ip32/crime.h> |
| 29 | #include <asm/ip32/mace.h> |
| 30 | #include <asm/ip32/ip32_ints.h> |
| 31 | |
| 32 | /* issue a PIO read to make sure no PIO writes are pending */ |
| 33 | static void inline flush_crime_bus(void) |
| 34 | { |
Ralf Baechle | b6d7c7a | 2006-05-30 02:13:16 +0100 | [diff] [blame] | 35 | crime->control; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 36 | } |
| 37 | |
| 38 | static void inline flush_mace_bus(void) |
| 39 | { |
Ralf Baechle | b6d7c7a | 2006-05-30 02:13:16 +0100 | [diff] [blame] | 40 | mace->perif.ctrl.misc; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 41 | } |
| 42 | |
Ralf Baechle | dd67b15 | 2007-10-14 14:02:26 +0100 | [diff] [blame] | 43 | /* |
| 44 | * O2 irq map |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 45 | * |
| 46 | * IP0 -> software (ignored) |
| 47 | * IP1 -> software (ignored) |
| 48 | * IP2 -> (irq0) C crime 1.1 all interrupts; crime 1.5 ??? |
| 49 | * IP3 -> (irq1) X unknown |
| 50 | * IP4 -> (irq2) X unknown |
| 51 | * IP5 -> (irq3) X unknown |
| 52 | * IP6 -> (irq4) X unknown |
Ralf Baechle | dd67b15 | 2007-10-14 14:02:26 +0100 | [diff] [blame] | 53 | * IP7 -> (irq5) 7 CPU count/compare timer (system timer) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 54 | * |
| 55 | * crime: (C) |
| 56 | * |
| 57 | * CRIME_INT_STAT 31:0: |
| 58 | * |
Ralf Baechle | dd67b15 | 2007-10-14 14:02:26 +0100 | [diff] [blame] | 59 | * 0 -> 8 Video in 1 |
| 60 | * 1 -> 9 Video in 2 |
| 61 | * 2 -> 10 Video out |
| 62 | * 3 -> 11 Mace ethernet |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 63 | * 4 -> S SuperIO sub-interrupt |
| 64 | * 5 -> M Miscellaneous sub-interrupt |
| 65 | * 6 -> A Audio sub-interrupt |
Ralf Baechle | dd67b15 | 2007-10-14 14:02:26 +0100 | [diff] [blame] | 66 | * 7 -> 15 PCI bridge errors |
| 67 | * 8 -> 16 PCI SCSI aic7xxx 0 |
| 68 | * 9 -> 17 PCI SCSI aic7xxx 1 |
| 69 | * 10 -> 18 PCI slot 0 |
| 70 | * 11 -> 19 unused (PCI slot 1) |
| 71 | * 12 -> 20 unused (PCI slot 2) |
| 72 | * 13 -> 21 unused (PCI shared 0) |
| 73 | * 14 -> 22 unused (PCI shared 1) |
| 74 | * 15 -> 23 unused (PCI shared 2) |
| 75 | * 16 -> 24 GBE0 (E) |
| 76 | * 17 -> 25 GBE1 (E) |
| 77 | * 18 -> 26 GBE2 (E) |
| 78 | * 19 -> 27 GBE3 (E) |
| 79 | * 20 -> 28 CPU errors |
| 80 | * 21 -> 29 Memory errors |
| 81 | * 22 -> 30 RE empty edge (E) |
| 82 | * 23 -> 31 RE full edge (E) |
| 83 | * 24 -> 32 RE idle edge (E) |
| 84 | * 25 -> 33 RE empty level |
| 85 | * 26 -> 34 RE full level |
| 86 | * 27 -> 35 RE idle level |
| 87 | * 28 -> 36 unused (software 0) (E) |
| 88 | * 29 -> 37 unused (software 1) (E) |
| 89 | * 30 -> 38 unused (software 2) - crime 1.5 CPU SysCorError (E) |
| 90 | * 31 -> 39 VICE |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 91 | * |
| 92 | * S, M, A: Use the MACE ISA interrupt register |
| 93 | * MACE_ISA_INT_STAT 31:0 |
| 94 | * |
Ralf Baechle | dd67b15 | 2007-10-14 14:02:26 +0100 | [diff] [blame] | 95 | * 0-7 -> 40-47 Audio |
| 96 | * 8 -> 48 RTC |
| 97 | * 9 -> 49 Keyboard |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 98 | * 10 -> X Keyboard polled |
Ralf Baechle | dd67b15 | 2007-10-14 14:02:26 +0100 | [diff] [blame] | 99 | * 11 -> 51 Mouse |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 100 | * 12 -> X Mouse polled |
Ralf Baechle | dd67b15 | 2007-10-14 14:02:26 +0100 | [diff] [blame] | 101 | * 13-15 -> 53-55 Count/compare timers |
| 102 | * 16-19 -> 56-59 Parallel (16 E) |
| 103 | * 20-25 -> 60-62 Serial 1 (22 E) |
| 104 | * 26-31 -> 66-71 Serial 2 (28 E) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 105 | * |
Ralf Baechle | dd67b15 | 2007-10-14 14:02:26 +0100 | [diff] [blame] | 106 | * Note that this means IRQs 12-14, 50, and 52 do not exist. This is a |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 107 | * different IRQ map than IRIX uses, but that's OK as Linux irq handling |
| 108 | * is quite different anyway. |
| 109 | */ |
| 110 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 111 | /* Some initial interrupts to set up */ |
Ralf Baechle | 937a801 | 2006-10-07 19:44:33 +0100 | [diff] [blame] | 112 | extern irqreturn_t crime_memerr_intr(int irq, void *dev_id); |
| 113 | extern irqreturn_t crime_cpuerr_intr(int irq, void *dev_id); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 114 | |
Thomas Gleixner | 4e45171 | 2007-08-28 09:03:01 +0000 | [diff] [blame] | 115 | struct irqaction memerr_irq = { |
| 116 | .handler = crime_memerr_intr, |
| 117 | .flags = IRQF_DISABLED, |
| 118 | .mask = CPU_MASK_NONE, |
| 119 | .name = "CRIME memory error", |
| 120 | }; |
Ralf Baechle | 8a13ecd | 2007-10-28 18:46:39 +0000 | [diff] [blame] | 121 | |
Thomas Gleixner | 4e45171 | 2007-08-28 09:03:01 +0000 | [diff] [blame] | 122 | struct irqaction cpuerr_irq = { |
| 123 | .handler = crime_cpuerr_intr, |
| 124 | .flags = IRQF_DISABLED, |
| 125 | .mask = CPU_MASK_NONE, |
| 126 | .name = "CRIME CPU error", |
| 127 | }; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 128 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 129 | /* |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 130 | * This is for pure CRIME interrupts - ie not MACE. The advantage? |
| 131 | * We get to split the register in half and do faster lookups. |
| 132 | */ |
| 133 | |
| 134 | static uint64_t crime_mask; |
| 135 | |
Ralf Baechle | 8a13ecd | 2007-10-28 18:46:39 +0000 | [diff] [blame] | 136 | static inline void crime_enable_irq(unsigned int irq) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 137 | { |
Ralf Baechle | 8a13ecd | 2007-10-28 18:46:39 +0000 | [diff] [blame] | 138 | unsigned int bit = irq - CRIME_IRQ_BASE; |
| 139 | |
| 140 | crime_mask |= 1 << bit; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 141 | crime->imask = crime_mask; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 142 | } |
| 143 | |
Ralf Baechle | 8a13ecd | 2007-10-28 18:46:39 +0000 | [diff] [blame] | 144 | static inline void crime_disable_irq(unsigned int irq) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 145 | { |
Ralf Baechle | 8a13ecd | 2007-10-28 18:46:39 +0000 | [diff] [blame] | 146 | unsigned int bit = irq - CRIME_IRQ_BASE; |
| 147 | |
| 148 | crime_mask &= ~(1 << bit); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 149 | crime->imask = crime_mask; |
| 150 | flush_crime_bus(); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 151 | } |
| 152 | |
Ralf Baechle | 8a13ecd | 2007-10-28 18:46:39 +0000 | [diff] [blame] | 153 | static void crime_level_mask_and_ack_irq(unsigned int irq) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 154 | { |
Ralf Baechle | 8a13ecd | 2007-10-28 18:46:39 +0000 | [diff] [blame] | 155 | crime_disable_irq(irq); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 156 | } |
| 157 | |
Ralf Baechle | 8a13ecd | 2007-10-28 18:46:39 +0000 | [diff] [blame] | 158 | static void crime_level_end_irq(unsigned int irq) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 159 | { |
| 160 | if (!(irq_desc[irq].status & (IRQ_DISABLED | IRQ_INPROGRESS))) |
Ralf Baechle | 8a13ecd | 2007-10-28 18:46:39 +0000 | [diff] [blame] | 161 | crime_enable_irq(irq); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 162 | } |
| 163 | |
Ralf Baechle | 8a13ecd | 2007-10-28 18:46:39 +0000 | [diff] [blame] | 164 | static struct irq_chip crime_level_interrupt = { |
| 165 | .name = "IP32 CRIME", |
| 166 | .ack = crime_level_mask_and_ack_irq, |
| 167 | .mask = crime_disable_irq, |
| 168 | .mask_ack = crime_level_mask_and_ack_irq, |
| 169 | .unmask = crime_enable_irq, |
| 170 | .end = crime_level_end_irq, |
| 171 | }; |
| 172 | |
| 173 | static void crime_edge_mask_and_ack_irq(unsigned int irq) |
| 174 | { |
| 175 | unsigned int bit = irq - CRIME_IRQ_BASE; |
| 176 | uint64_t crime_int; |
| 177 | |
| 178 | /* Edge triggered interrupts must be cleared. */ |
| 179 | |
| 180 | crime_int = crime->hard_int; |
| 181 | crime_int &= ~(1 << bit); |
| 182 | crime->hard_int = crime_int; |
| 183 | |
| 184 | crime_disable_irq(irq); |
| 185 | } |
| 186 | |
| 187 | static void crime_edge_end_irq(unsigned int irq) |
| 188 | { |
| 189 | if (!(irq_desc[irq].status & (IRQ_DISABLED | IRQ_INPROGRESS))) |
| 190 | crime_enable_irq(irq); |
| 191 | } |
| 192 | |
| 193 | static struct irq_chip crime_edge_interrupt = { |
| 194 | .name = "IP32 CRIME", |
| 195 | .ack = crime_edge_mask_and_ack_irq, |
| 196 | .mask = crime_disable_irq, |
| 197 | .mask_ack = crime_edge_mask_and_ack_irq, |
| 198 | .unmask = crime_enable_irq, |
| 199 | .end = crime_edge_end_irq, |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 200 | }; |
| 201 | |
| 202 | /* |
| 203 | * This is for MACE PCI interrupts. We can decrease bus traffic by masking |
| 204 | * as close to the source as possible. This also means we can take the |
| 205 | * next chunk of the CRIME register in one piece. |
| 206 | */ |
| 207 | |
| 208 | static unsigned long macepci_mask; |
| 209 | |
| 210 | static void enable_macepci_irq(unsigned int irq) |
| 211 | { |
Ralf Baechle | 98ce472 | 2007-10-30 15:43:44 +0000 | [diff] [blame] | 212 | macepci_mask |= MACEPCI_CONTROL_INT(irq - MACEPCI_SCSI0_IRQ); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 213 | mace->pci.control = macepci_mask; |
Ralf Baechle | 98ce472 | 2007-10-30 15:43:44 +0000 | [diff] [blame] | 214 | crime_mask |= 1 << (irq - CRIME_IRQ_BASE); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 215 | crime->imask = crime_mask; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 216 | } |
| 217 | |
| 218 | static void disable_macepci_irq(unsigned int irq) |
| 219 | { |
Ralf Baechle | 98ce472 | 2007-10-30 15:43:44 +0000 | [diff] [blame] | 220 | crime_mask &= ~(1 << (irq - CRIME_IRQ_BASE)); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 221 | crime->imask = crime_mask; |
| 222 | flush_crime_bus(); |
Ralf Baechle | 98ce472 | 2007-10-30 15:43:44 +0000 | [diff] [blame] | 223 | macepci_mask &= ~MACEPCI_CONTROL_INT(irq - MACEPCI_SCSI0_IRQ); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 224 | mace->pci.control = macepci_mask; |
| 225 | flush_mace_bus(); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 226 | } |
| 227 | |
| 228 | static void end_macepci_irq(unsigned int irq) |
| 229 | { |
| 230 | if (!(irq_desc[irq].status & (IRQ_DISABLED|IRQ_INPROGRESS))) |
| 231 | enable_macepci_irq(irq); |
| 232 | } |
| 233 | |
Ralf Baechle | 94dee17 | 2006-07-02 14:41:42 +0100 | [diff] [blame] | 234 | static struct irq_chip ip32_macepci_interrupt = { |
Atsushi Nemoto | 70d21cd | 2007-01-15 00:07:25 +0900 | [diff] [blame] | 235 | .name = "IP32 MACE PCI", |
Atsushi Nemoto | 1603b5a | 2006-11-02 02:08:36 +0900 | [diff] [blame] | 236 | .ack = disable_macepci_irq, |
| 237 | .mask = disable_macepci_irq, |
| 238 | .mask_ack = disable_macepci_irq, |
| 239 | .unmask = enable_macepci_irq, |
Ralf Baechle | 8ab00b9 | 2005-02-28 13:39:57 +0000 | [diff] [blame] | 240 | .end = end_macepci_irq, |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 241 | }; |
| 242 | |
| 243 | /* This is used for MACE ISA interrupts. That means bits 4-6 in the |
| 244 | * CRIME register. |
| 245 | */ |
| 246 | |
| 247 | #define MACEISA_AUDIO_INT (MACEISA_AUDIO_SW_INT | \ |
| 248 | MACEISA_AUDIO_SC_INT | \ |
| 249 | MACEISA_AUDIO1_DMAT_INT | \ |
| 250 | MACEISA_AUDIO1_OF_INT | \ |
| 251 | MACEISA_AUDIO2_DMAT_INT | \ |
| 252 | MACEISA_AUDIO2_MERR_INT | \ |
| 253 | MACEISA_AUDIO3_DMAT_INT | \ |
| 254 | MACEISA_AUDIO3_MERR_INT) |
| 255 | #define MACEISA_MISC_INT (MACEISA_RTC_INT | \ |
| 256 | MACEISA_KEYB_INT | \ |
| 257 | MACEISA_KEYB_POLL_INT | \ |
| 258 | MACEISA_MOUSE_INT | \ |
| 259 | MACEISA_MOUSE_POLL_INT | \ |
Thiemo Seufer | cfbae5d | 2006-07-05 18:43:29 +0100 | [diff] [blame] | 260 | MACEISA_TIMER0_INT | \ |
| 261 | MACEISA_TIMER1_INT | \ |
| 262 | MACEISA_TIMER2_INT) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 263 | #define MACEISA_SUPERIO_INT (MACEISA_PARALLEL_INT | \ |
| 264 | MACEISA_PAR_CTXA_INT | \ |
| 265 | MACEISA_PAR_CTXB_INT | \ |
| 266 | MACEISA_PAR_MERR_INT | \ |
| 267 | MACEISA_SERIAL1_INT | \ |
| 268 | MACEISA_SERIAL1_TDMAT_INT | \ |
| 269 | MACEISA_SERIAL1_TDMAPR_INT | \ |
| 270 | MACEISA_SERIAL1_TDMAME_INT | \ |
| 271 | MACEISA_SERIAL1_RDMAT_INT | \ |
| 272 | MACEISA_SERIAL1_RDMAOR_INT | \ |
| 273 | MACEISA_SERIAL2_INT | \ |
| 274 | MACEISA_SERIAL2_TDMAT_INT | \ |
| 275 | MACEISA_SERIAL2_TDMAPR_INT | \ |
| 276 | MACEISA_SERIAL2_TDMAME_INT | \ |
| 277 | MACEISA_SERIAL2_RDMAT_INT | \ |
| 278 | MACEISA_SERIAL2_RDMAOR_INT) |
| 279 | |
| 280 | static unsigned long maceisa_mask; |
| 281 | |
Ralf Baechle | 49a89ef | 2007-10-11 23:46:15 +0100 | [diff] [blame] | 282 | static void enable_maceisa_irq(unsigned int irq) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 283 | { |
| 284 | unsigned int crime_int = 0; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 285 | |
Ralf Baechle | 8a13ecd | 2007-10-28 18:46:39 +0000 | [diff] [blame] | 286 | pr_debug("maceisa enable: %u\n", irq); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 287 | |
| 288 | switch (irq) { |
| 289 | case MACEISA_AUDIO_SW_IRQ ... MACEISA_AUDIO3_MERR_IRQ: |
| 290 | crime_int = MACE_AUDIO_INT; |
| 291 | break; |
Thiemo Seufer | cfbae5d | 2006-07-05 18:43:29 +0100 | [diff] [blame] | 292 | case MACEISA_RTC_IRQ ... MACEISA_TIMER2_IRQ: |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 293 | crime_int = MACE_MISC_INT; |
| 294 | break; |
| 295 | case MACEISA_PARALLEL_IRQ ... MACEISA_SERIAL2_RDMAOR_IRQ: |
| 296 | crime_int = MACE_SUPERIO_INT; |
| 297 | break; |
| 298 | } |
Ralf Baechle | 8a13ecd | 2007-10-28 18:46:39 +0000 | [diff] [blame] | 299 | pr_debug("crime_int %08x enabled\n", crime_int); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 300 | crime_mask |= crime_int; |
| 301 | crime->imask = crime_mask; |
Ralf Baechle | 98ce472 | 2007-10-30 15:43:44 +0000 | [diff] [blame] | 302 | maceisa_mask |= 1 << (irq - MACEISA_AUDIO_SW_IRQ); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 303 | mace->perif.ctrl.imask = maceisa_mask; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 304 | } |
| 305 | |
| 306 | static void disable_maceisa_irq(unsigned int irq) |
| 307 | { |
| 308 | unsigned int crime_int = 0; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 309 | |
Ralf Baechle | 98ce472 | 2007-10-30 15:43:44 +0000 | [diff] [blame] | 310 | maceisa_mask &= ~(1 << (irq - MACEISA_AUDIO_SW_IRQ)); |
Ralf Baechle | 8a13ecd | 2007-10-28 18:46:39 +0000 | [diff] [blame] | 311 | if (!(maceisa_mask & MACEISA_AUDIO_INT)) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 312 | crime_int |= MACE_AUDIO_INT; |
Ralf Baechle | 8a13ecd | 2007-10-28 18:46:39 +0000 | [diff] [blame] | 313 | if (!(maceisa_mask & MACEISA_MISC_INT)) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 314 | crime_int |= MACE_MISC_INT; |
Ralf Baechle | 8a13ecd | 2007-10-28 18:46:39 +0000 | [diff] [blame] | 315 | if (!(maceisa_mask & MACEISA_SUPERIO_INT)) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 316 | crime_int |= MACE_SUPERIO_INT; |
| 317 | crime_mask &= ~crime_int; |
| 318 | crime->imask = crime_mask; |
| 319 | flush_crime_bus(); |
| 320 | mace->perif.ctrl.imask = maceisa_mask; |
| 321 | flush_mace_bus(); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 322 | } |
| 323 | |
| 324 | static void mask_and_ack_maceisa_irq(unsigned int irq) |
| 325 | { |
Atsushi Nemoto | 1603b5a | 2006-11-02 02:08:36 +0900 | [diff] [blame] | 326 | unsigned long mace_int; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 327 | |
Ralf Baechle | c87e090 | 2009-03-30 14:49:44 +0200 | [diff] [blame] | 328 | /* edge triggered */ |
| 329 | mace_int = mace->perif.ctrl.istat; |
| 330 | mace_int &= ~(1 << (irq - MACEISA_AUDIO_SW_IRQ)); |
| 331 | mace->perif.ctrl.istat = mace_int; |
| 332 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 333 | disable_maceisa_irq(irq); |
| 334 | } |
| 335 | |
| 336 | static void end_maceisa_irq(unsigned irq) |
| 337 | { |
| 338 | if (!(irq_desc[irq].status & (IRQ_DISABLED | IRQ_INPROGRESS))) |
| 339 | enable_maceisa_irq(irq); |
| 340 | } |
| 341 | |
Ralf Baechle | c87e090 | 2009-03-30 14:49:44 +0200 | [diff] [blame] | 342 | static struct irq_chip ip32_maceisa_level_interrupt = { |
| 343 | .name = "IP32 MACE ISA", |
| 344 | .ack = disable_maceisa_irq, |
| 345 | .mask = disable_maceisa_irq, |
| 346 | .mask_ack = disable_maceisa_irq, |
| 347 | .unmask = enable_maceisa_irq, |
| 348 | .end = end_maceisa_irq, |
| 349 | }; |
| 350 | |
| 351 | static struct irq_chip ip32_maceisa_edge_interrupt = { |
Ralf Baechle | 8a13ecd | 2007-10-28 18:46:39 +0000 | [diff] [blame] | 352 | .name = "IP32 MACE ISA", |
| 353 | .ack = mask_and_ack_maceisa_irq, |
| 354 | .mask = disable_maceisa_irq, |
| 355 | .mask_ack = mask_and_ack_maceisa_irq, |
| 356 | .unmask = enable_maceisa_irq, |
| 357 | .end = end_maceisa_irq, |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 358 | }; |
| 359 | |
| 360 | /* This is used for regular non-ISA, non-PCI MACE interrupts. That means |
| 361 | * bits 0-3 and 7 in the CRIME register. |
| 362 | */ |
| 363 | |
| 364 | static void enable_mace_irq(unsigned int irq) |
| 365 | { |
Ralf Baechle | 98ce472 | 2007-10-30 15:43:44 +0000 | [diff] [blame] | 366 | unsigned int bit = irq - CRIME_IRQ_BASE; |
| 367 | |
| 368 | crime_mask |= (1 << bit); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 369 | crime->imask = crime_mask; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 370 | } |
| 371 | |
| 372 | static void disable_mace_irq(unsigned int irq) |
| 373 | { |
Ralf Baechle | 98ce472 | 2007-10-30 15:43:44 +0000 | [diff] [blame] | 374 | unsigned int bit = irq - CRIME_IRQ_BASE; |
| 375 | |
| 376 | crime_mask &= ~(1 << bit); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 377 | crime->imask = crime_mask; |
| 378 | flush_crime_bus(); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 379 | } |
| 380 | |
| 381 | static void end_mace_irq(unsigned int irq) |
| 382 | { |
| 383 | if (!(irq_desc[irq].status & (IRQ_DISABLED|IRQ_INPROGRESS))) |
| 384 | enable_mace_irq(irq); |
| 385 | } |
| 386 | |
Ralf Baechle | 94dee17 | 2006-07-02 14:41:42 +0100 | [diff] [blame] | 387 | static struct irq_chip ip32_mace_interrupt = { |
Atsushi Nemoto | 70d21cd | 2007-01-15 00:07:25 +0900 | [diff] [blame] | 388 | .name = "IP32 MACE", |
Atsushi Nemoto | 1603b5a | 2006-11-02 02:08:36 +0900 | [diff] [blame] | 389 | .ack = disable_mace_irq, |
| 390 | .mask = disable_mace_irq, |
| 391 | .mask_ack = disable_mace_irq, |
| 392 | .unmask = enable_mace_irq, |
Ralf Baechle | 8ab00b9 | 2005-02-28 13:39:57 +0000 | [diff] [blame] | 393 | .end = end_mace_irq, |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 394 | }; |
| 395 | |
Ralf Baechle | 937a801 | 2006-10-07 19:44:33 +0100 | [diff] [blame] | 396 | static void ip32_unknown_interrupt(void) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 397 | { |
Ralf Baechle | 49a89ef | 2007-10-11 23:46:15 +0100 | [diff] [blame] | 398 | printk("Unknown interrupt occurred!\n"); |
| 399 | printk("cp0_status: %08x\n", read_c0_status()); |
| 400 | printk("cp0_cause: %08x\n", read_c0_cause()); |
| 401 | printk("CRIME intr mask: %016lx\n", crime->imask); |
| 402 | printk("CRIME intr status: %016lx\n", crime->istat); |
| 403 | printk("CRIME hardware intr register: %016lx\n", crime->hard_int); |
| 404 | printk("MACE ISA intr mask: %08lx\n", mace->perif.ctrl.imask); |
| 405 | printk("MACE ISA intr status: %08lx\n", mace->perif.ctrl.istat); |
| 406 | printk("MACE PCI control register: %08x\n", mace->pci.control); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 407 | |
| 408 | printk("Register dump:\n"); |
Ralf Baechle | 937a801 | 2006-10-07 19:44:33 +0100 | [diff] [blame] | 409 | show_regs(get_irq_regs()); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 410 | |
| 411 | printk("Please mail this report to linux-mips@linux-mips.org\n"); |
| 412 | printk("Spinning..."); |
| 413 | while(1) ; |
| 414 | } |
| 415 | |
| 416 | /* CRIME 1.1 appears to deliver all interrupts to this one pin. */ |
| 417 | /* change this to loop over all edge-triggered irqs, exception masked out ones */ |
Ralf Baechle | 937a801 | 2006-10-07 19:44:33 +0100 | [diff] [blame] | 418 | static void ip32_irq0(void) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 419 | { |
| 420 | uint64_t crime_int; |
| 421 | int irq = 0; |
| 422 | |
Ralf Baechle | dd67b15 | 2007-10-14 14:02:26 +0100 | [diff] [blame] | 423 | /* |
| 424 | * Sanity check interrupt numbering enum. |
| 425 | * MACE got 32 interrupts and there are 32 MACE ISA interrupts daisy |
| 426 | * chained. |
| 427 | */ |
| 428 | BUILD_BUG_ON(CRIME_VICE_IRQ - MACE_VID_IN1_IRQ != 31); |
| 429 | BUILD_BUG_ON(MACEISA_SERIAL2_RDMAOR_IRQ - MACEISA_AUDIO_SW_IRQ != 31); |
| 430 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 431 | crime_int = crime->istat & crime_mask; |
Thomas Bogendoerfer | 1faf7f2 | 2008-06-24 00:48:05 +0200 | [diff] [blame] | 432 | |
| 433 | /* crime sometime delivers spurious interrupts, ignore them */ |
| 434 | if (unlikely(crime_int == 0)) |
| 435 | return; |
| 436 | |
Ralf Baechle | dd67b15 | 2007-10-14 14:02:26 +0100 | [diff] [blame] | 437 | irq = MACE_VID_IN1_IRQ + __ffs(crime_int); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 438 | |
| 439 | if (crime_int & CRIME_MACEISA_INT_MASK) { |
| 440 | unsigned long mace_int = mace->perif.ctrl.istat; |
Ralf Baechle | dd67b15 | 2007-10-14 14:02:26 +0100 | [diff] [blame] | 441 | irq = __ffs(mace_int & maceisa_mask) + MACEISA_AUDIO_SW_IRQ; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 442 | } |
Ralf Baechle | dd67b15 | 2007-10-14 14:02:26 +0100 | [diff] [blame] | 443 | |
Ralf Baechle | 8a13ecd | 2007-10-28 18:46:39 +0000 | [diff] [blame] | 444 | pr_debug("*irq %u*\n", irq); |
Ralf Baechle | 937a801 | 2006-10-07 19:44:33 +0100 | [diff] [blame] | 445 | do_IRQ(irq); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 446 | } |
| 447 | |
Ralf Baechle | 937a801 | 2006-10-07 19:44:33 +0100 | [diff] [blame] | 448 | static void ip32_irq1(void) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 449 | { |
Ralf Baechle | 937a801 | 2006-10-07 19:44:33 +0100 | [diff] [blame] | 450 | ip32_unknown_interrupt(); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 451 | } |
| 452 | |
Ralf Baechle | 937a801 | 2006-10-07 19:44:33 +0100 | [diff] [blame] | 453 | static void ip32_irq2(void) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 454 | { |
Ralf Baechle | 937a801 | 2006-10-07 19:44:33 +0100 | [diff] [blame] | 455 | ip32_unknown_interrupt(); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 456 | } |
| 457 | |
Ralf Baechle | 937a801 | 2006-10-07 19:44:33 +0100 | [diff] [blame] | 458 | static void ip32_irq3(void) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 459 | { |
Ralf Baechle | 937a801 | 2006-10-07 19:44:33 +0100 | [diff] [blame] | 460 | ip32_unknown_interrupt(); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 461 | } |
| 462 | |
Ralf Baechle | 937a801 | 2006-10-07 19:44:33 +0100 | [diff] [blame] | 463 | static void ip32_irq4(void) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 464 | { |
Ralf Baechle | 937a801 | 2006-10-07 19:44:33 +0100 | [diff] [blame] | 465 | ip32_unknown_interrupt(); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 466 | } |
| 467 | |
Ralf Baechle | 937a801 | 2006-10-07 19:44:33 +0100 | [diff] [blame] | 468 | static void ip32_irq5(void) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 469 | { |
Ralf Baechle | dd67b15 | 2007-10-14 14:02:26 +0100 | [diff] [blame] | 470 | do_IRQ(MIPS_CPU_IRQ_BASE + 7); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 471 | } |
| 472 | |
Ralf Baechle | 937a801 | 2006-10-07 19:44:33 +0100 | [diff] [blame] | 473 | asmlinkage void plat_irq_dispatch(void) |
Ralf Baechle | e4ac58a | 2006-04-03 17:56:36 +0100 | [diff] [blame] | 474 | { |
Thiemo Seufer | 119537c | 2007-03-19 00:13:37 +0000 | [diff] [blame] | 475 | unsigned int pending = read_c0_status() & read_c0_cause(); |
Ralf Baechle | e4ac58a | 2006-04-03 17:56:36 +0100 | [diff] [blame] | 476 | |
| 477 | if (likely(pending & IE_IRQ0)) |
Ralf Baechle | 937a801 | 2006-10-07 19:44:33 +0100 | [diff] [blame] | 478 | ip32_irq0(); |
Ralf Baechle | e4ac58a | 2006-04-03 17:56:36 +0100 | [diff] [blame] | 479 | else if (unlikely(pending & IE_IRQ1)) |
Ralf Baechle | 937a801 | 2006-10-07 19:44:33 +0100 | [diff] [blame] | 480 | ip32_irq1(); |
Ralf Baechle | e4ac58a | 2006-04-03 17:56:36 +0100 | [diff] [blame] | 481 | else if (unlikely(pending & IE_IRQ2)) |
Ralf Baechle | 937a801 | 2006-10-07 19:44:33 +0100 | [diff] [blame] | 482 | ip32_irq2(); |
Ralf Baechle | e4ac58a | 2006-04-03 17:56:36 +0100 | [diff] [blame] | 483 | else if (unlikely(pending & IE_IRQ3)) |
Ralf Baechle | 937a801 | 2006-10-07 19:44:33 +0100 | [diff] [blame] | 484 | ip32_irq3(); |
Ralf Baechle | e4ac58a | 2006-04-03 17:56:36 +0100 | [diff] [blame] | 485 | else if (unlikely(pending & IE_IRQ4)) |
Ralf Baechle | 937a801 | 2006-10-07 19:44:33 +0100 | [diff] [blame] | 486 | ip32_irq4(); |
Ralf Baechle | e4ac58a | 2006-04-03 17:56:36 +0100 | [diff] [blame] | 487 | else if (likely(pending & IE_IRQ5)) |
Ralf Baechle | 937a801 | 2006-10-07 19:44:33 +0100 | [diff] [blame] | 488 | ip32_irq5(); |
Ralf Baechle | e4ac58a | 2006-04-03 17:56:36 +0100 | [diff] [blame] | 489 | } |
| 490 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 491 | void __init arch_init_irq(void) |
| 492 | { |
| 493 | unsigned int irq; |
| 494 | |
| 495 | /* Install our interrupt handler, then clear and disable all |
| 496 | * CRIME and MACE interrupts. */ |
| 497 | crime->imask = 0; |
| 498 | crime->hard_int = 0; |
| 499 | crime->soft_int = 0; |
| 500 | mace->perif.ctrl.istat = 0; |
| 501 | mace->perif.ctrl.imask = 0; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 502 | |
Ralf Baechle | dd67b15 | 2007-10-14 14:02:26 +0100 | [diff] [blame] | 503 | mips_cpu_irq_init(); |
Ralf Baechle | 98ce472 | 2007-10-30 15:43:44 +0000 | [diff] [blame] | 504 | for (irq = CRIME_IRQ_BASE; irq <= IP32_IRQ_MAX; irq++) { |
Ralf Baechle | dd67b15 | 2007-10-14 14:02:26 +0100 | [diff] [blame] | 505 | switch (irq) { |
| 506 | case MACE_VID_IN1_IRQ ... MACE_PCI_BRIDGE_IRQ: |
Ralf Baechle | c87e090 | 2009-03-30 14:49:44 +0200 | [diff] [blame] | 507 | set_irq_chip_and_handler_name(irq,&ip32_mace_interrupt, |
| 508 | handle_level_irq, "level"); |
Ralf Baechle | dd67b15 | 2007-10-14 14:02:26 +0100 | [diff] [blame] | 509 | break; |
Ralf Baechle | c87e090 | 2009-03-30 14:49:44 +0200 | [diff] [blame] | 510 | |
Ralf Baechle | dd67b15 | 2007-10-14 14:02:26 +0100 | [diff] [blame] | 511 | case MACEPCI_SCSI0_IRQ ... MACEPCI_SHARED2_IRQ: |
Ralf Baechle | c87e090 | 2009-03-30 14:49:44 +0200 | [diff] [blame] | 512 | set_irq_chip_and_handler_name(irq, |
| 513 | &ip32_macepci_interrupt, handle_level_irq, |
| 514 | "level"); |
Ralf Baechle | dd67b15 | 2007-10-14 14:02:26 +0100 | [diff] [blame] | 515 | break; |
Ralf Baechle | c87e090 | 2009-03-30 14:49:44 +0200 | [diff] [blame] | 516 | |
Ralf Baechle | 8a13ecd | 2007-10-28 18:46:39 +0000 | [diff] [blame] | 517 | case CRIME_GBE0_IRQ ... CRIME_GBE3_IRQ: |
Ralf Baechle | c87e090 | 2009-03-30 14:49:44 +0200 | [diff] [blame] | 518 | set_irq_chip_and_handler_name(irq, |
| 519 | &crime_edge_interrupt, handle_edge_irq, "edge"); |
Ralf Baechle | 8a13ecd | 2007-10-28 18:46:39 +0000 | [diff] [blame] | 520 | break; |
| 521 | case CRIME_CPUERR_IRQ: |
| 522 | case CRIME_MEMERR_IRQ: |
Ralf Baechle | c87e090 | 2009-03-30 14:49:44 +0200 | [diff] [blame] | 523 | set_irq_chip_and_handler_name(irq, |
| 524 | &crime_level_interrupt, handle_level_irq, |
| 525 | "level"); |
Ralf Baechle | 8a13ecd | 2007-10-28 18:46:39 +0000 | [diff] [blame] | 526 | break; |
Ralf Baechle | c87e090 | 2009-03-30 14:49:44 +0200 | [diff] [blame] | 527 | |
Ralf Baechle | 8a13ecd | 2007-10-28 18:46:39 +0000 | [diff] [blame] | 528 | case CRIME_RE_EMPTY_E_IRQ ... CRIME_RE_IDLE_E_IRQ: |
| 529 | case CRIME_SOFT0_IRQ ... CRIME_SOFT2_IRQ: |
Ralf Baechle | c87e090 | 2009-03-30 14:49:44 +0200 | [diff] [blame] | 530 | set_irq_chip_and_handler_name(irq, |
| 531 | &crime_edge_interrupt, handle_edge_irq, "edge"); |
Ralf Baechle | 8a13ecd | 2007-10-28 18:46:39 +0000 | [diff] [blame] | 532 | break; |
Ralf Baechle | c87e090 | 2009-03-30 14:49:44 +0200 | [diff] [blame] | 533 | |
Ralf Baechle | 8a13ecd | 2007-10-28 18:46:39 +0000 | [diff] [blame] | 534 | case CRIME_VICE_IRQ: |
Ralf Baechle | c87e090 | 2009-03-30 14:49:44 +0200 | [diff] [blame] | 535 | set_irq_chip_and_handler_name(irq, |
| 536 | &crime_edge_interrupt, handle_edge_irq, "edge"); |
Ralf Baechle | dd67b15 | 2007-10-14 14:02:26 +0100 | [diff] [blame] | 537 | break; |
Ralf Baechle | c87e090 | 2009-03-30 14:49:44 +0200 | [diff] [blame] | 538 | |
| 539 | case MACEISA_PARALLEL_IRQ: |
| 540 | case MACEISA_SERIAL1_TDMAPR_IRQ: |
| 541 | case MACEISA_SERIAL2_TDMAPR_IRQ: |
| 542 | set_irq_chip_and_handler_name(irq, |
| 543 | &ip32_maceisa_edge_interrupt, handle_edge_irq, |
| 544 | "edge"); |
| 545 | break; |
| 546 | |
Ralf Baechle | dd67b15 | 2007-10-14 14:02:26 +0100 | [diff] [blame] | 547 | default: |
Ralf Baechle | c87e090 | 2009-03-30 14:49:44 +0200 | [diff] [blame] | 548 | set_irq_chip_and_handler_name(irq, |
| 549 | &ip32_maceisa_level_interrupt, handle_level_irq, |
| 550 | "level"); |
Ralf Baechle | 8a13ecd | 2007-10-28 18:46:39 +0000 | [diff] [blame] | 551 | break; |
Ralf Baechle | dd67b15 | 2007-10-14 14:02:26 +0100 | [diff] [blame] | 552 | } |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 553 | } |
| 554 | setup_irq(CRIME_MEMERR_IRQ, &memerr_irq); |
| 555 | setup_irq(CRIME_CPUERR_IRQ, &cpuerr_irq); |
| 556 | |
| 557 | #define ALLINTS (IE_IRQ0 | IE_IRQ1 | IE_IRQ2 | IE_IRQ3 | IE_IRQ4 | IE_IRQ5) |
| 558 | change_c0_status(ST0_IM, ALLINTS); |
| 559 | } |