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Zhang Wei173acc72008-03-01 07:42:48 -07001/*
2 * Freescale MPC85xx, MPC83xx DMA Engine support
3 *
Li Yange2c8e4252010-11-11 20:16:29 +08004 * Copyright (C) 2007-2010 Freescale Semiconductor, Inc. All rights reserved.
Zhang Wei173acc72008-03-01 07:42:48 -07005 *
6 * Author:
7 * Zhang Wei <wei.zhang@freescale.com>, Jul 2007
8 * Ebony Zhu <ebony.zhu@freescale.com>, May 2007
9 *
10 * Description:
11 * DMA engine driver for Freescale MPC8540 DMA controller, which is
12 * also fit for MPC8560, MPC8555, MPC8548, MPC8641, and etc.
Stefan Weilc2e07b32010-08-03 19:44:52 +020013 * The support for MPC8349 DMA controller is also added.
Zhang Wei173acc72008-03-01 07:42:48 -070014 *
Ira W. Snydera7aea372009-04-23 16:17:54 -070015 * This driver instructs the DMA controller to issue the PCI Read Multiple
16 * command for PCI read operations, instead of using the default PCI Read Line
17 * command. Please be aware that this setting may result in read pre-fetching
18 * on some platforms.
19 *
Zhang Wei173acc72008-03-01 07:42:48 -070020 * This is free software; you can redistribute it and/or modify
21 * it under the terms of the GNU General Public License as published by
22 * the Free Software Foundation; either version 2 of the License, or
23 * (at your option) any later version.
24 *
25 */
26
27#include <linux/init.h>
28#include <linux/module.h>
29#include <linux/pci.h>
Tejun Heo5a0e3ad2010-03-24 17:04:11 +090030#include <linux/slab.h>
Zhang Wei173acc72008-03-01 07:42:48 -070031#include <linux/interrupt.h>
32#include <linux/dmaengine.h>
33#include <linux/delay.h>
34#include <linux/dma-mapping.h>
35#include <linux/dmapool.h>
36#include <linux/of_platform.h>
37
Russell King - ARM Linuxd2ebfb32012-03-06 22:34:26 +000038#include "dmaengine.h"
Zhang Wei173acc72008-03-01 07:42:48 -070039#include "fsldma.h"
40
Ira Snyderb1584712011-03-03 07:54:55 +000041#define chan_dbg(chan, fmt, arg...) \
42 dev_dbg(chan->dev, "%s: " fmt, chan->name, ##arg)
43#define chan_err(chan, fmt, arg...) \
44 dev_err(chan->dev, "%s: " fmt, chan->name, ##arg)
Ira Snyderc14330412010-09-30 11:46:45 +000045
Ira Snyderb1584712011-03-03 07:54:55 +000046static const char msg_ld_oom[] = "No free memory for link descriptor";
Zhang Wei173acc72008-03-01 07:42:48 -070047
Ira Snydere8bd84d2011-03-03 07:54:54 +000048/*
49 * Register Helpers
50 */
Zhang Wei173acc72008-03-01 07:42:48 -070051
Ira Snydera1c03312010-01-06 13:34:05 +000052static void set_sr(struct fsldma_chan *chan, u32 val)
Zhang Wei173acc72008-03-01 07:42:48 -070053{
Ira Snydera1c03312010-01-06 13:34:05 +000054 DMA_OUT(chan, &chan->regs->sr, val, 32);
Zhang Wei173acc72008-03-01 07:42:48 -070055}
56
Ira Snydera1c03312010-01-06 13:34:05 +000057static u32 get_sr(struct fsldma_chan *chan)
Zhang Wei173acc72008-03-01 07:42:48 -070058{
Ira Snydera1c03312010-01-06 13:34:05 +000059 return DMA_IN(chan, &chan->regs->sr, 32);
Zhang Wei173acc72008-03-01 07:42:48 -070060}
61
Ira Snydera1c03312010-01-06 13:34:05 +000062static void set_cdar(struct fsldma_chan *chan, dma_addr_t addr)
Zhang Wei173acc72008-03-01 07:42:48 -070063{
Ira Snydera1c03312010-01-06 13:34:05 +000064 DMA_OUT(chan, &chan->regs->cdar, addr | FSL_DMA_SNEN, 64);
Zhang Wei173acc72008-03-01 07:42:48 -070065}
66
Ira Snydera1c03312010-01-06 13:34:05 +000067static dma_addr_t get_cdar(struct fsldma_chan *chan)
Zhang Wei173acc72008-03-01 07:42:48 -070068{
Ira Snydera1c03312010-01-06 13:34:05 +000069 return DMA_IN(chan, &chan->regs->cdar, 64) & ~FSL_DMA_SNEN;
Zhang Wei173acc72008-03-01 07:42:48 -070070}
71
Ira Snydera1c03312010-01-06 13:34:05 +000072static u32 get_bcr(struct fsldma_chan *chan)
Zhang Weif79abb62008-03-18 18:45:00 -070073{
Ira Snydera1c03312010-01-06 13:34:05 +000074 return DMA_IN(chan, &chan->regs->bcr, 32);
Zhang Weif79abb62008-03-18 18:45:00 -070075}
76
Ira Snydere8bd84d2011-03-03 07:54:54 +000077/*
78 * Descriptor Helpers
79 */
80
Zhang Wei173acc72008-03-01 07:42:48 -070081static void set_desc_cnt(struct fsldma_chan *chan,
82 struct fsl_dma_ld_hw *hw, u32 count)
Zhang Wei173acc72008-03-01 07:42:48 -070083{
Zhang Wei173acc72008-03-01 07:42:48 -070084 hw->count = CPU_TO_DMA(chan, count, 32);
Zhang Wei173acc72008-03-01 07:42:48 -070085}
86
Ira Snyder9c4d1e72011-03-03 07:54:59 +000087static u32 get_desc_cnt(struct fsldma_chan *chan, struct fsl_desc_sw *desc)
Zhang Wei173acc72008-03-01 07:42:48 -070088{
Ira Snyder9c4d1e72011-03-03 07:54:59 +000089 return DMA_TO_CPU(chan, desc->hw.count, 32);
Zhang Wei173acc72008-03-01 07:42:48 -070090}
91
Zhang Wei173acc72008-03-01 07:42:48 -070092static void set_desc_src(struct fsldma_chan *chan,
Ira Snyder31f43062011-03-03 07:54:57 +000093 struct fsl_dma_ld_hw *hw, dma_addr_t src)
Zhang Wei173acc72008-03-01 07:42:48 -070094{
Zhang Wei173acc72008-03-01 07:42:48 -070095 u64 snoop_bits;
Dan Williams900325a2009-03-02 15:33:46 -070096
Zhang Wei173acc72008-03-01 07:42:48 -070097 snoop_bits = ((chan->feature & FSL_DMA_IP_MASK) == FSL_DMA_IP_85XX)
98 ? ((u64)FSL_DMA_SATR_SREADTYPE_SNOOP_READ << 32) : 0;
99 hw->src_addr = CPU_TO_DMA(chan, snoop_bits | src, 64);
Zhang Wei173acc72008-03-01 07:42:48 -0700100}
101
Ira Snyder9c4d1e72011-03-03 07:54:59 +0000102static dma_addr_t get_desc_src(struct fsldma_chan *chan,
103 struct fsl_desc_sw *desc)
104{
105 u64 snoop_bits;
106
107 snoop_bits = ((chan->feature & FSL_DMA_IP_MASK) == FSL_DMA_IP_85XX)
108 ? ((u64)FSL_DMA_SATR_SREADTYPE_SNOOP_READ << 32) : 0;
109 return DMA_TO_CPU(chan, desc->hw.src_addr, 64) & ~snoop_bits;
110}
111
Zhang Wei173acc72008-03-01 07:42:48 -0700112static void set_desc_dst(struct fsldma_chan *chan,
Ira Snyder31f43062011-03-03 07:54:57 +0000113 struct fsl_dma_ld_hw *hw, dma_addr_t dst)
Zhang Wei173acc72008-03-01 07:42:48 -0700114{
115 u64 snoop_bits;
116
117 snoop_bits = ((chan->feature & FSL_DMA_IP_MASK) == FSL_DMA_IP_85XX)
118 ? ((u64)FSL_DMA_DATR_DWRITETYPE_SNOOP_WRITE << 32) : 0;
119 hw->dst_addr = CPU_TO_DMA(chan, snoop_bits | dst, 64);
120}
121
Ira Snyder9c4d1e72011-03-03 07:54:59 +0000122static dma_addr_t get_desc_dst(struct fsldma_chan *chan,
123 struct fsl_desc_sw *desc)
124{
125 u64 snoop_bits;
126
127 snoop_bits = ((chan->feature & FSL_DMA_IP_MASK) == FSL_DMA_IP_85XX)
128 ? ((u64)FSL_DMA_DATR_DWRITETYPE_SNOOP_WRITE << 32) : 0;
129 return DMA_TO_CPU(chan, desc->hw.dst_addr, 64) & ~snoop_bits;
130}
131
Zhang Wei173acc72008-03-01 07:42:48 -0700132static void set_desc_next(struct fsldma_chan *chan,
Ira Snyder31f43062011-03-03 07:54:57 +0000133 struct fsl_dma_ld_hw *hw, dma_addr_t next)
Zhang Wei173acc72008-03-01 07:42:48 -0700134{
135 u64 snoop_bits;
136
137 snoop_bits = ((chan->feature & FSL_DMA_IP_MASK) == FSL_DMA_IP_83XX)
138 ? FSL_DMA_SNEN : 0;
139 hw->next_ln_addr = CPU_TO_DMA(chan, snoop_bits | next, 64);
140}
141
Ira Snyder31f43062011-03-03 07:54:57 +0000142static void set_ld_eol(struct fsldma_chan *chan, struct fsl_desc_sw *desc)
Zhang Wei173acc72008-03-01 07:42:48 -0700143{
Ira Snyder776c8942009-05-15 11:33:20 -0700144 u64 snoop_bits;
145
Ira Snydera1c03312010-01-06 13:34:05 +0000146 snoop_bits = ((chan->feature & FSL_DMA_IP_MASK) == FSL_DMA_IP_83XX)
Ira Snyder776c8942009-05-15 11:33:20 -0700147 ? FSL_DMA_SNEN : 0;
148
Ira Snydera1c03312010-01-06 13:34:05 +0000149 desc->hw.next_ln_addr = CPU_TO_DMA(chan,
150 DMA_TO_CPU(chan, desc->hw.next_ln_addr, 64) | FSL_DMA_EOL
Ira Snyder776c8942009-05-15 11:33:20 -0700151 | snoop_bits, 64);
Zhang Wei173acc72008-03-01 07:42:48 -0700152}
153
Ira Snydere8bd84d2011-03-03 07:54:54 +0000154/*
155 * DMA Engine Hardware Control Helpers
156 */
Zhang Wei173acc72008-03-01 07:42:48 -0700157
Ira Snydere8bd84d2011-03-03 07:54:54 +0000158static void dma_init(struct fsldma_chan *chan)
Zhang Wei173acc72008-03-01 07:42:48 -0700159{
Ira Snydere8bd84d2011-03-03 07:54:54 +0000160 /* Reset the channel */
161 DMA_OUT(chan, &chan->regs->mr, 0, 32);
Zhang Wei173acc72008-03-01 07:42:48 -0700162
Ira Snydere8bd84d2011-03-03 07:54:54 +0000163 switch (chan->feature & FSL_DMA_IP_MASK) {
164 case FSL_DMA_IP_85XX:
165 /* Set the channel to below modes:
166 * EIE - Error interrupt enable
Ira Snydere8bd84d2011-03-03 07:54:54 +0000167 * EOLNIE - End of links interrupt enable
168 * BWC - Bandwidth sharing among channels
169 */
170 DMA_OUT(chan, &chan->regs->mr, FSL_DMA_MR_BWC
Ira Snyderf04cd402011-03-03 07:54:58 +0000171 | FSL_DMA_MR_EIE | FSL_DMA_MR_EOLNIE, 32);
Ira Snydere8bd84d2011-03-03 07:54:54 +0000172 break;
173 case FSL_DMA_IP_83XX:
174 /* Set the channel to below modes:
175 * EOTIE - End-of-transfer interrupt enable
176 * PRC_RM - PCI read multiple
177 */
178 DMA_OUT(chan, &chan->regs->mr, FSL_DMA_MR_EOTIE
179 | FSL_DMA_MR_PRC_RM, 32);
180 break;
181 }
Zhang Wei173acc72008-03-01 07:42:48 -0700182}
183
184static int dma_is_idle(struct fsldma_chan *chan)
185{
186 u32 sr = get_sr(chan);
187 return (!(sr & FSL_DMA_SR_CB)) || (sr & FSL_DMA_SR_CH);
188}
189
Ira Snyderf04cd402011-03-03 07:54:58 +0000190/*
191 * Start the DMA controller
192 *
193 * Preconditions:
194 * - the CDAR register must point to the start descriptor
195 * - the MRn[CS] bit must be cleared
196 */
Zhang Wei173acc72008-03-01 07:42:48 -0700197static void dma_start(struct fsldma_chan *chan)
198{
199 u32 mode;
200
201 mode = DMA_IN(chan, &chan->regs->mr, 32);
202
Ira Snyderf04cd402011-03-03 07:54:58 +0000203 if (chan->feature & FSL_DMA_CHAN_PAUSE_EXT) {
204 DMA_OUT(chan, &chan->regs->bcr, 0, 32);
205 mode |= FSL_DMA_MR_EMP_EN;
206 } else {
207 mode &= ~FSL_DMA_MR_EMP_EN;
Zhang Wei173acc72008-03-01 07:42:48 -0700208 }
209
Ira Snyderf04cd402011-03-03 07:54:58 +0000210 if (chan->feature & FSL_DMA_CHAN_START_EXT) {
Zhang Wei173acc72008-03-01 07:42:48 -0700211 mode |= FSL_DMA_MR_EMS_EN;
Ira Snyderf04cd402011-03-03 07:54:58 +0000212 } else {
213 mode &= ~FSL_DMA_MR_EMS_EN;
Zhang Wei173acc72008-03-01 07:42:48 -0700214 mode |= FSL_DMA_MR_CS;
Ira Snyderf04cd402011-03-03 07:54:58 +0000215 }
Zhang Wei173acc72008-03-01 07:42:48 -0700216
217 DMA_OUT(chan, &chan->regs->mr, mode, 32);
218}
219
220static void dma_halt(struct fsldma_chan *chan)
221{
222 u32 mode;
223 int i;
224
Ira Snydera00ae342011-03-03 07:55:01 +0000225 /* read the mode register */
Zhang Wei173acc72008-03-01 07:42:48 -0700226 mode = DMA_IN(chan, &chan->regs->mr, 32);
Ira Snydera00ae342011-03-03 07:55:01 +0000227
228 /*
229 * The 85xx controller supports channel abort, which will stop
230 * the current transfer. On 83xx, this bit is the transfer error
231 * mask bit, which should not be changed.
232 */
233 if ((chan->feature & FSL_DMA_IP_MASK) == FSL_DMA_IP_85XX) {
234 mode |= FSL_DMA_MR_CA;
235 DMA_OUT(chan, &chan->regs->mr, mode, 32);
236
237 mode &= ~FSL_DMA_MR_CA;
238 }
239
240 /* stop the DMA controller */
241 mode &= ~(FSL_DMA_MR_CS | FSL_DMA_MR_EMS_EN);
Zhang Wei173acc72008-03-01 07:42:48 -0700242 DMA_OUT(chan, &chan->regs->mr, mode, 32);
243
Ira Snydera00ae342011-03-03 07:55:01 +0000244 /* wait for the DMA controller to become idle */
Zhang Wei173acc72008-03-01 07:42:48 -0700245 for (i = 0; i < 100; i++) {
246 if (dma_is_idle(chan))
247 return;
248
249 udelay(10);
250 }
251
252 if (!dma_is_idle(chan))
Ira Snyderb1584712011-03-03 07:54:55 +0000253 chan_err(chan, "DMA halt timeout!\n");
Zhang Wei173acc72008-03-01 07:42:48 -0700254}
255
Zhang Wei173acc72008-03-01 07:42:48 -0700256/**
257 * fsl_chan_set_src_loop_size - Set source address hold transfer size
Ira Snydera1c03312010-01-06 13:34:05 +0000258 * @chan : Freescale DMA channel
Zhang Wei173acc72008-03-01 07:42:48 -0700259 * @size : Address loop size, 0 for disable loop
260 *
261 * The set source address hold transfer size. The source
262 * address hold or loop transfer size is when the DMA transfer
263 * data from source address (SA), if the loop size is 4, the DMA will
264 * read data from SA, SA + 1, SA + 2, SA + 3, then loop back to SA,
265 * SA + 1 ... and so on.
266 */
Ira Snydera1c03312010-01-06 13:34:05 +0000267static void fsl_chan_set_src_loop_size(struct fsldma_chan *chan, int size)
Zhang Wei173acc72008-03-01 07:42:48 -0700268{
Ira Snyder272ca652010-01-06 13:33:59 +0000269 u32 mode;
270
Ira Snydera1c03312010-01-06 13:34:05 +0000271 mode = DMA_IN(chan, &chan->regs->mr, 32);
Ira Snyder272ca652010-01-06 13:33:59 +0000272
Zhang Wei173acc72008-03-01 07:42:48 -0700273 switch (size) {
274 case 0:
Ira Snyder272ca652010-01-06 13:33:59 +0000275 mode &= ~FSL_DMA_MR_SAHE;
Zhang Wei173acc72008-03-01 07:42:48 -0700276 break;
277 case 1:
278 case 2:
279 case 4:
280 case 8:
Ira Snyder272ca652010-01-06 13:33:59 +0000281 mode |= FSL_DMA_MR_SAHE | (__ilog2(size) << 14);
Zhang Wei173acc72008-03-01 07:42:48 -0700282 break;
283 }
Ira Snyder272ca652010-01-06 13:33:59 +0000284
Ira Snydera1c03312010-01-06 13:34:05 +0000285 DMA_OUT(chan, &chan->regs->mr, mode, 32);
Zhang Wei173acc72008-03-01 07:42:48 -0700286}
287
288/**
Ira Snyder738f5f72010-01-06 13:34:02 +0000289 * fsl_chan_set_dst_loop_size - Set destination address hold transfer size
Ira Snydera1c03312010-01-06 13:34:05 +0000290 * @chan : Freescale DMA channel
Zhang Wei173acc72008-03-01 07:42:48 -0700291 * @size : Address loop size, 0 for disable loop
292 *
293 * The set destination address hold transfer size. The destination
294 * address hold or loop transfer size is when the DMA transfer
295 * data to destination address (TA), if the loop size is 4, the DMA will
296 * write data to TA, TA + 1, TA + 2, TA + 3, then loop back to TA,
297 * TA + 1 ... and so on.
298 */
Ira Snydera1c03312010-01-06 13:34:05 +0000299static void fsl_chan_set_dst_loop_size(struct fsldma_chan *chan, int size)
Zhang Wei173acc72008-03-01 07:42:48 -0700300{
Ira Snyder272ca652010-01-06 13:33:59 +0000301 u32 mode;
302
Ira Snydera1c03312010-01-06 13:34:05 +0000303 mode = DMA_IN(chan, &chan->regs->mr, 32);
Ira Snyder272ca652010-01-06 13:33:59 +0000304
Zhang Wei173acc72008-03-01 07:42:48 -0700305 switch (size) {
306 case 0:
Ira Snyder272ca652010-01-06 13:33:59 +0000307 mode &= ~FSL_DMA_MR_DAHE;
Zhang Wei173acc72008-03-01 07:42:48 -0700308 break;
309 case 1:
310 case 2:
311 case 4:
312 case 8:
Ira Snyder272ca652010-01-06 13:33:59 +0000313 mode |= FSL_DMA_MR_DAHE | (__ilog2(size) << 16);
Zhang Wei173acc72008-03-01 07:42:48 -0700314 break;
315 }
Ira Snyder272ca652010-01-06 13:33:59 +0000316
Ira Snydera1c03312010-01-06 13:34:05 +0000317 DMA_OUT(chan, &chan->regs->mr, mode, 32);
Zhang Wei173acc72008-03-01 07:42:48 -0700318}
319
320/**
Ira Snydere6c7ecb2009-09-08 17:53:04 -0700321 * fsl_chan_set_request_count - Set DMA Request Count for external control
Ira Snydera1c03312010-01-06 13:34:05 +0000322 * @chan : Freescale DMA channel
Ira Snydere6c7ecb2009-09-08 17:53:04 -0700323 * @size : Number of bytes to transfer in a single request
324 *
325 * The Freescale DMA channel can be controlled by the external signal DREQ#.
326 * The DMA request count is how many bytes are allowed to transfer before
327 * pausing the channel, after which a new assertion of DREQ# resumes channel
328 * operation.
329 *
330 * A size of 0 disables external pause control. The maximum size is 1024.
331 */
Ira Snydera1c03312010-01-06 13:34:05 +0000332static void fsl_chan_set_request_count(struct fsldma_chan *chan, int size)
Ira Snydere6c7ecb2009-09-08 17:53:04 -0700333{
Ira Snyder272ca652010-01-06 13:33:59 +0000334 u32 mode;
335
Ira Snydere6c7ecb2009-09-08 17:53:04 -0700336 BUG_ON(size > 1024);
Ira Snyder272ca652010-01-06 13:33:59 +0000337
Ira Snydera1c03312010-01-06 13:34:05 +0000338 mode = DMA_IN(chan, &chan->regs->mr, 32);
Ira Snyder272ca652010-01-06 13:33:59 +0000339 mode |= (__ilog2(size) << 24) & 0x0f000000;
340
Ira Snydera1c03312010-01-06 13:34:05 +0000341 DMA_OUT(chan, &chan->regs->mr, mode, 32);
Ira Snydere6c7ecb2009-09-08 17:53:04 -0700342}
343
344/**
Zhang Wei173acc72008-03-01 07:42:48 -0700345 * fsl_chan_toggle_ext_pause - Toggle channel external pause status
Ira Snydera1c03312010-01-06 13:34:05 +0000346 * @chan : Freescale DMA channel
Ira Snydere6c7ecb2009-09-08 17:53:04 -0700347 * @enable : 0 is disabled, 1 is enabled.
Zhang Wei173acc72008-03-01 07:42:48 -0700348 *
Ira Snydere6c7ecb2009-09-08 17:53:04 -0700349 * The Freescale DMA channel can be controlled by the external signal DREQ#.
350 * The DMA Request Count feature should be used in addition to this feature
351 * to set the number of bytes to transfer before pausing the channel.
Zhang Wei173acc72008-03-01 07:42:48 -0700352 */
Ira Snydera1c03312010-01-06 13:34:05 +0000353static void fsl_chan_toggle_ext_pause(struct fsldma_chan *chan, int enable)
Zhang Wei173acc72008-03-01 07:42:48 -0700354{
Ira Snydere6c7ecb2009-09-08 17:53:04 -0700355 if (enable)
Ira Snydera1c03312010-01-06 13:34:05 +0000356 chan->feature |= FSL_DMA_CHAN_PAUSE_EXT;
Ira Snydere6c7ecb2009-09-08 17:53:04 -0700357 else
Ira Snydera1c03312010-01-06 13:34:05 +0000358 chan->feature &= ~FSL_DMA_CHAN_PAUSE_EXT;
Zhang Wei173acc72008-03-01 07:42:48 -0700359}
360
361/**
362 * fsl_chan_toggle_ext_start - Toggle channel external start status
Ira Snydera1c03312010-01-06 13:34:05 +0000363 * @chan : Freescale DMA channel
Zhang Wei173acc72008-03-01 07:42:48 -0700364 * @enable : 0 is disabled, 1 is enabled.
365 *
366 * If enable the external start, the channel can be started by an
367 * external DMA start pin. So the dma_start() does not start the
368 * transfer immediately. The DMA channel will wait for the
369 * control pin asserted.
370 */
Ira Snydera1c03312010-01-06 13:34:05 +0000371static void fsl_chan_toggle_ext_start(struct fsldma_chan *chan, int enable)
Zhang Wei173acc72008-03-01 07:42:48 -0700372{
373 if (enable)
Ira Snydera1c03312010-01-06 13:34:05 +0000374 chan->feature |= FSL_DMA_CHAN_START_EXT;
Zhang Wei173acc72008-03-01 07:42:48 -0700375 else
Ira Snydera1c03312010-01-06 13:34:05 +0000376 chan->feature &= ~FSL_DMA_CHAN_START_EXT;
Zhang Wei173acc72008-03-01 07:42:48 -0700377}
378
Ira Snyder31f43062011-03-03 07:54:57 +0000379static void append_ld_queue(struct fsldma_chan *chan, struct fsl_desc_sw *desc)
Ira Snyder9c3a50b2010-01-06 13:34:06 +0000380{
381 struct fsl_desc_sw *tail = to_fsl_desc(chan->ld_pending.prev);
382
383 if (list_empty(&chan->ld_pending))
384 goto out_splice;
385
386 /*
387 * Add the hardware descriptor to the chain of hardware descriptors
388 * that already exists in memory.
389 *
390 * This will un-set the EOL bit of the existing transaction, and the
391 * last link in this transaction will become the EOL descriptor.
392 */
393 set_desc_next(chan, &tail->hw, desc->async_tx.phys);
394
395 /*
396 * Add the software descriptor and all children to the list
397 * of pending transactions
398 */
399out_splice:
400 list_splice_tail_init(&desc->tx_list, &chan->ld_pending);
401}
402
Zhang Wei173acc72008-03-01 07:42:48 -0700403static dma_cookie_t fsl_dma_tx_submit(struct dma_async_tx_descriptor *tx)
404{
Ira Snydera1c03312010-01-06 13:34:05 +0000405 struct fsldma_chan *chan = to_fsl_chan(tx->chan);
Dan Williamseda34232009-09-08 17:53:02 -0700406 struct fsl_desc_sw *desc = tx_to_fsl_desc(tx);
407 struct fsl_desc_sw *child;
Zhang Wei173acc72008-03-01 07:42:48 -0700408 unsigned long flags;
409 dma_cookie_t cookie;
410
Ira Snydera1c03312010-01-06 13:34:05 +0000411 spin_lock_irqsave(&chan->desc_lock, flags);
Zhang Wei173acc72008-03-01 07:42:48 -0700412
Ira Snyder9c3a50b2010-01-06 13:34:06 +0000413 /*
414 * assign cookies to all of the software descriptors
415 * that make up this transaction
416 */
Dan Williamseda34232009-09-08 17:53:02 -0700417 list_for_each_entry(child, &desc->tx_list, node) {
Russell King - ARM Linux884485e2012-03-06 22:34:46 +0000418 cookie = dma_cookie_assign(&child->async_tx);
Ira Snyderbcfb7462009-05-15 14:27:16 -0700419 }
420
Ira Snyder9c3a50b2010-01-06 13:34:06 +0000421 /* put this transaction onto the tail of the pending queue */
Ira Snydera1c03312010-01-06 13:34:05 +0000422 append_ld_queue(chan, desc);
Zhang Wei173acc72008-03-01 07:42:48 -0700423
Ira Snydera1c03312010-01-06 13:34:05 +0000424 spin_unlock_irqrestore(&chan->desc_lock, flags);
Zhang Wei173acc72008-03-01 07:42:48 -0700425
426 return cookie;
427}
428
429/**
430 * fsl_dma_alloc_descriptor - Allocate descriptor from channel's DMA pool.
Ira Snydera1c03312010-01-06 13:34:05 +0000431 * @chan : Freescale DMA channel
Zhang Wei173acc72008-03-01 07:42:48 -0700432 *
433 * Return - The descriptor allocated. NULL for failed.
434 */
Ira Snyder31f43062011-03-03 07:54:57 +0000435static struct fsl_desc_sw *fsl_dma_alloc_descriptor(struct fsldma_chan *chan)
Zhang Wei173acc72008-03-01 07:42:48 -0700436{
Ira Snyder9c3a50b2010-01-06 13:34:06 +0000437 struct fsl_desc_sw *desc;
Zhang Wei173acc72008-03-01 07:42:48 -0700438 dma_addr_t pdesc;
Zhang Wei173acc72008-03-01 07:42:48 -0700439
Ira Snyder9c3a50b2010-01-06 13:34:06 +0000440 desc = dma_pool_alloc(chan->desc_pool, GFP_ATOMIC, &pdesc);
441 if (!desc) {
Ira Snyderb1584712011-03-03 07:54:55 +0000442 chan_dbg(chan, "out of memory for link descriptor\n");
Ira Snyder9c3a50b2010-01-06 13:34:06 +0000443 return NULL;
Zhang Wei173acc72008-03-01 07:42:48 -0700444 }
445
Ira Snyder9c3a50b2010-01-06 13:34:06 +0000446 memset(desc, 0, sizeof(*desc));
447 INIT_LIST_HEAD(&desc->tx_list);
448 dma_async_tx_descriptor_init(&desc->async_tx, &chan->common);
449 desc->async_tx.tx_submit = fsl_dma_tx_submit;
450 desc->async_tx.phys = pdesc;
451
Ira Snyder0ab09c32011-03-03 07:54:56 +0000452#ifdef FSL_DMA_LD_DEBUG
453 chan_dbg(chan, "LD %p allocated\n", desc);
454#endif
455
Ira Snyder9c3a50b2010-01-06 13:34:06 +0000456 return desc;
Zhang Wei173acc72008-03-01 07:42:48 -0700457}
458
Zhang Wei173acc72008-03-01 07:42:48 -0700459/**
460 * fsl_dma_alloc_chan_resources - Allocate resources for DMA channel.
Ira Snydera1c03312010-01-06 13:34:05 +0000461 * @chan : Freescale DMA channel
Zhang Wei173acc72008-03-01 07:42:48 -0700462 *
463 * This function will create a dma pool for descriptor allocation.
464 *
465 * Return - The number of descriptors allocated.
466 */
Ira Snydera1c03312010-01-06 13:34:05 +0000467static int fsl_dma_alloc_chan_resources(struct dma_chan *dchan)
Zhang Wei173acc72008-03-01 07:42:48 -0700468{
Ira Snydera1c03312010-01-06 13:34:05 +0000469 struct fsldma_chan *chan = to_fsl_chan(dchan);
Timur Tabi77cd62e2008-09-26 17:00:11 -0700470
471 /* Has this channel already been allocated? */
Ira Snydera1c03312010-01-06 13:34:05 +0000472 if (chan->desc_pool)
Timur Tabi77cd62e2008-09-26 17:00:11 -0700473 return 1;
Zhang Wei173acc72008-03-01 07:42:48 -0700474
Ira Snyder9c3a50b2010-01-06 13:34:06 +0000475 /*
476 * We need the descriptor to be aligned to 32bytes
Zhang Wei173acc72008-03-01 07:42:48 -0700477 * for meeting FSL DMA specification requirement.
478 */
Ira Snyderb1584712011-03-03 07:54:55 +0000479 chan->desc_pool = dma_pool_create(chan->name, chan->dev,
Ira Snyder9c3a50b2010-01-06 13:34:06 +0000480 sizeof(struct fsl_desc_sw),
481 __alignof__(struct fsl_desc_sw), 0);
Ira Snydera1c03312010-01-06 13:34:05 +0000482 if (!chan->desc_pool) {
Ira Snyderb1584712011-03-03 07:54:55 +0000483 chan_err(chan, "unable to allocate descriptor pool\n");
Ira Snyder9c3a50b2010-01-06 13:34:06 +0000484 return -ENOMEM;
Zhang Wei173acc72008-03-01 07:42:48 -0700485 }
486
Ira Snyder9c3a50b2010-01-06 13:34:06 +0000487 /* there is at least one descriptor free to be allocated */
Zhang Wei173acc72008-03-01 07:42:48 -0700488 return 1;
489}
490
491/**
Ira Snyder9c3a50b2010-01-06 13:34:06 +0000492 * fsldma_free_desc_list - Free all descriptors in a queue
493 * @chan: Freescae DMA channel
494 * @list: the list to free
495 *
496 * LOCKING: must hold chan->desc_lock
497 */
498static void fsldma_free_desc_list(struct fsldma_chan *chan,
499 struct list_head *list)
500{
501 struct fsl_desc_sw *desc, *_desc;
502
503 list_for_each_entry_safe(desc, _desc, list, node) {
504 list_del(&desc->node);
Ira Snyder0ab09c32011-03-03 07:54:56 +0000505#ifdef FSL_DMA_LD_DEBUG
506 chan_dbg(chan, "LD %p free\n", desc);
507#endif
Ira Snyder9c3a50b2010-01-06 13:34:06 +0000508 dma_pool_free(chan->desc_pool, desc, desc->async_tx.phys);
509 }
510}
511
512static void fsldma_free_desc_list_reverse(struct fsldma_chan *chan,
513 struct list_head *list)
514{
515 struct fsl_desc_sw *desc, *_desc;
516
517 list_for_each_entry_safe_reverse(desc, _desc, list, node) {
518 list_del(&desc->node);
Ira Snyder0ab09c32011-03-03 07:54:56 +0000519#ifdef FSL_DMA_LD_DEBUG
520 chan_dbg(chan, "LD %p free\n", desc);
521#endif
Ira Snyder9c3a50b2010-01-06 13:34:06 +0000522 dma_pool_free(chan->desc_pool, desc, desc->async_tx.phys);
523 }
524}
525
526/**
Zhang Wei173acc72008-03-01 07:42:48 -0700527 * fsl_dma_free_chan_resources - Free all resources of the channel.
Ira Snydera1c03312010-01-06 13:34:05 +0000528 * @chan : Freescale DMA channel
Zhang Wei173acc72008-03-01 07:42:48 -0700529 */
Ira Snydera1c03312010-01-06 13:34:05 +0000530static void fsl_dma_free_chan_resources(struct dma_chan *dchan)
Zhang Wei173acc72008-03-01 07:42:48 -0700531{
Ira Snydera1c03312010-01-06 13:34:05 +0000532 struct fsldma_chan *chan = to_fsl_chan(dchan);
Zhang Wei173acc72008-03-01 07:42:48 -0700533 unsigned long flags;
534
Ira Snyderb1584712011-03-03 07:54:55 +0000535 chan_dbg(chan, "free all channel resources\n");
Ira Snydera1c03312010-01-06 13:34:05 +0000536 spin_lock_irqsave(&chan->desc_lock, flags);
Ira Snyder9c3a50b2010-01-06 13:34:06 +0000537 fsldma_free_desc_list(chan, &chan->ld_pending);
538 fsldma_free_desc_list(chan, &chan->ld_running);
Ira Snydera1c03312010-01-06 13:34:05 +0000539 spin_unlock_irqrestore(&chan->desc_lock, flags);
Timur Tabi77cd62e2008-09-26 17:00:11 -0700540
Ira Snyder9c3a50b2010-01-06 13:34:06 +0000541 dma_pool_destroy(chan->desc_pool);
Ira Snydera1c03312010-01-06 13:34:05 +0000542 chan->desc_pool = NULL;
Zhang Wei173acc72008-03-01 07:42:48 -0700543}
544
Zhang Wei2187c262008-03-13 17:45:28 -0700545static struct dma_async_tx_descriptor *
Ira Snydera1c03312010-01-06 13:34:05 +0000546fsl_dma_prep_interrupt(struct dma_chan *dchan, unsigned long flags)
Zhang Wei2187c262008-03-13 17:45:28 -0700547{
Ira Snydera1c03312010-01-06 13:34:05 +0000548 struct fsldma_chan *chan;
Zhang Wei2187c262008-03-13 17:45:28 -0700549 struct fsl_desc_sw *new;
550
Ira Snydera1c03312010-01-06 13:34:05 +0000551 if (!dchan)
Zhang Wei2187c262008-03-13 17:45:28 -0700552 return NULL;
553
Ira Snydera1c03312010-01-06 13:34:05 +0000554 chan = to_fsl_chan(dchan);
Zhang Wei2187c262008-03-13 17:45:28 -0700555
Ira Snydera1c03312010-01-06 13:34:05 +0000556 new = fsl_dma_alloc_descriptor(chan);
Zhang Wei2187c262008-03-13 17:45:28 -0700557 if (!new) {
Ira Snyderb1584712011-03-03 07:54:55 +0000558 chan_err(chan, "%s\n", msg_ld_oom);
Zhang Wei2187c262008-03-13 17:45:28 -0700559 return NULL;
560 }
561
562 new->async_tx.cookie = -EBUSY;
Dan Williams636bdea2008-04-17 20:17:26 -0700563 new->async_tx.flags = flags;
Zhang Wei2187c262008-03-13 17:45:28 -0700564
Zhang Weif79abb62008-03-18 18:45:00 -0700565 /* Insert the link descriptor to the LD ring */
Dan Williamseda34232009-09-08 17:53:02 -0700566 list_add_tail(&new->node, &new->tx_list);
Zhang Weif79abb62008-03-18 18:45:00 -0700567
Ira Snyder31f43062011-03-03 07:54:57 +0000568 /* Set End-of-link to the last link descriptor of new list */
Ira Snydera1c03312010-01-06 13:34:05 +0000569 set_ld_eol(chan, new);
Zhang Wei2187c262008-03-13 17:45:28 -0700570
571 return &new->async_tx;
572}
573
Ira Snyder31f43062011-03-03 07:54:57 +0000574static struct dma_async_tx_descriptor *
575fsl_dma_prep_memcpy(struct dma_chan *dchan,
576 dma_addr_t dma_dst, dma_addr_t dma_src,
Zhang Wei173acc72008-03-01 07:42:48 -0700577 size_t len, unsigned long flags)
578{
Ira Snydera1c03312010-01-06 13:34:05 +0000579 struct fsldma_chan *chan;
Zhang Wei173acc72008-03-01 07:42:48 -0700580 struct fsl_desc_sw *first = NULL, *prev = NULL, *new;
581 size_t copy;
Zhang Wei173acc72008-03-01 07:42:48 -0700582
Ira Snydera1c03312010-01-06 13:34:05 +0000583 if (!dchan)
Zhang Wei173acc72008-03-01 07:42:48 -0700584 return NULL;
585
586 if (!len)
587 return NULL;
588
Ira Snydera1c03312010-01-06 13:34:05 +0000589 chan = to_fsl_chan(dchan);
Zhang Wei173acc72008-03-01 07:42:48 -0700590
591 do {
592
593 /* Allocate the link descriptor from DMA pool */
Ira Snydera1c03312010-01-06 13:34:05 +0000594 new = fsl_dma_alloc_descriptor(chan);
Zhang Wei173acc72008-03-01 07:42:48 -0700595 if (!new) {
Ira Snyderb1584712011-03-03 07:54:55 +0000596 chan_err(chan, "%s\n", msg_ld_oom);
Ira Snyder2e077f82009-05-15 09:59:46 -0700597 goto fail;
Zhang Wei173acc72008-03-01 07:42:48 -0700598 }
Zhang Wei173acc72008-03-01 07:42:48 -0700599
Zhang Wei56822842008-03-13 10:45:27 -0700600 copy = min(len, (size_t)FSL_DMA_BCR_MAX_CNT);
Zhang Wei173acc72008-03-01 07:42:48 -0700601
Ira Snydera1c03312010-01-06 13:34:05 +0000602 set_desc_cnt(chan, &new->hw, copy);
603 set_desc_src(chan, &new->hw, dma_src);
604 set_desc_dst(chan, &new->hw, dma_dst);
Zhang Wei173acc72008-03-01 07:42:48 -0700605
606 if (!first)
607 first = new;
608 else
Ira Snydera1c03312010-01-06 13:34:05 +0000609 set_desc_next(chan, &prev->hw, new->async_tx.phys);
Zhang Wei173acc72008-03-01 07:42:48 -0700610
611 new->async_tx.cookie = 0;
Dan Williams636bdea2008-04-17 20:17:26 -0700612 async_tx_ack(&new->async_tx);
Zhang Wei173acc72008-03-01 07:42:48 -0700613
614 prev = new;
615 len -= copy;
616 dma_src += copy;
Ira Snyder738f5f72010-01-06 13:34:02 +0000617 dma_dst += copy;
Zhang Wei173acc72008-03-01 07:42:48 -0700618
619 /* Insert the link descriptor to the LD ring */
Dan Williamseda34232009-09-08 17:53:02 -0700620 list_add_tail(&new->node, &first->tx_list);
Zhang Wei173acc72008-03-01 07:42:48 -0700621 } while (len);
622
Dan Williams636bdea2008-04-17 20:17:26 -0700623 new->async_tx.flags = flags; /* client is in control of this ack */
Zhang Wei173acc72008-03-01 07:42:48 -0700624 new->async_tx.cookie = -EBUSY;
625
Ira Snyder31f43062011-03-03 07:54:57 +0000626 /* Set End-of-link to the last link descriptor of new list */
Ira Snydera1c03312010-01-06 13:34:05 +0000627 set_ld_eol(chan, new);
Zhang Wei173acc72008-03-01 07:42:48 -0700628
Ira Snyder2e077f82009-05-15 09:59:46 -0700629 return &first->async_tx;
630
631fail:
632 if (!first)
633 return NULL;
634
Ira Snyder9c3a50b2010-01-06 13:34:06 +0000635 fsldma_free_desc_list_reverse(chan, &first->tx_list);
Ira Snyder2e077f82009-05-15 09:59:46 -0700636 return NULL;
Zhang Wei173acc72008-03-01 07:42:48 -0700637}
638
Ira Snyderc14330412010-09-30 11:46:45 +0000639static struct dma_async_tx_descriptor *fsl_dma_prep_sg(struct dma_chan *dchan,
640 struct scatterlist *dst_sg, unsigned int dst_nents,
641 struct scatterlist *src_sg, unsigned int src_nents,
642 unsigned long flags)
643{
644 struct fsl_desc_sw *first = NULL, *prev = NULL, *new = NULL;
645 struct fsldma_chan *chan = to_fsl_chan(dchan);
646 size_t dst_avail, src_avail;
647 dma_addr_t dst, src;
648 size_t len;
649
650 /* basic sanity checks */
651 if (dst_nents == 0 || src_nents == 0)
652 return NULL;
653
654 if (dst_sg == NULL || src_sg == NULL)
655 return NULL;
656
657 /*
658 * TODO: should we check that both scatterlists have the same
659 * TODO: number of bytes in total? Is that really an error?
660 */
661
662 /* get prepared for the loop */
663 dst_avail = sg_dma_len(dst_sg);
664 src_avail = sg_dma_len(src_sg);
665
666 /* run until we are out of scatterlist entries */
667 while (true) {
668
669 /* create the largest transaction possible */
670 len = min_t(size_t, src_avail, dst_avail);
671 len = min_t(size_t, len, FSL_DMA_BCR_MAX_CNT);
672 if (len == 0)
673 goto fetch;
674
675 dst = sg_dma_address(dst_sg) + sg_dma_len(dst_sg) - dst_avail;
676 src = sg_dma_address(src_sg) + sg_dma_len(src_sg) - src_avail;
677
678 /* allocate and populate the descriptor */
679 new = fsl_dma_alloc_descriptor(chan);
680 if (!new) {
Ira Snyderb1584712011-03-03 07:54:55 +0000681 chan_err(chan, "%s\n", msg_ld_oom);
Ira Snyderc14330412010-09-30 11:46:45 +0000682 goto fail;
683 }
Ira Snyderc14330412010-09-30 11:46:45 +0000684
685 set_desc_cnt(chan, &new->hw, len);
686 set_desc_src(chan, &new->hw, src);
687 set_desc_dst(chan, &new->hw, dst);
688
689 if (!first)
690 first = new;
691 else
692 set_desc_next(chan, &prev->hw, new->async_tx.phys);
693
694 new->async_tx.cookie = 0;
695 async_tx_ack(&new->async_tx);
696 prev = new;
697
698 /* Insert the link descriptor to the LD ring */
699 list_add_tail(&new->node, &first->tx_list);
700
701 /* update metadata */
702 dst_avail -= len;
703 src_avail -= len;
704
705fetch:
706 /* fetch the next dst scatterlist entry */
707 if (dst_avail == 0) {
708
709 /* no more entries: we're done */
710 if (dst_nents == 0)
711 break;
712
713 /* fetch the next entry: if there are no more: done */
714 dst_sg = sg_next(dst_sg);
715 if (dst_sg == NULL)
716 break;
717
718 dst_nents--;
719 dst_avail = sg_dma_len(dst_sg);
720 }
721
722 /* fetch the next src scatterlist entry */
723 if (src_avail == 0) {
724
725 /* no more entries: we're done */
726 if (src_nents == 0)
727 break;
728
729 /* fetch the next entry: if there are no more: done */
730 src_sg = sg_next(src_sg);
731 if (src_sg == NULL)
732 break;
733
734 src_nents--;
735 src_avail = sg_dma_len(src_sg);
736 }
737 }
738
739 new->async_tx.flags = flags; /* client is in control of this ack */
740 new->async_tx.cookie = -EBUSY;
741
742 /* Set End-of-link to the last link descriptor of new list */
743 set_ld_eol(chan, new);
744
745 return &first->async_tx;
746
747fail:
748 if (!first)
749 return NULL;
750
751 fsldma_free_desc_list_reverse(chan, &first->tx_list);
752 return NULL;
753}
754
Zhang Wei173acc72008-03-01 07:42:48 -0700755/**
Ira Snyderbbea0b62009-09-08 17:53:04 -0700756 * fsl_dma_prep_slave_sg - prepare descriptors for a DMA_SLAVE transaction
757 * @chan: DMA channel
758 * @sgl: scatterlist to transfer to/from
759 * @sg_len: number of entries in @scatterlist
760 * @direction: DMA direction
761 * @flags: DMAEngine flags
Alexandre Bounine185ecb52012-03-08 15:35:13 -0500762 * @context: transaction context (ignored)
Ira Snyderbbea0b62009-09-08 17:53:04 -0700763 *
764 * Prepare a set of descriptors for a DMA_SLAVE transaction. Following the
765 * DMA_SLAVE API, this gets the device-specific information from the
766 * chan->private variable.
767 */
768static struct dma_async_tx_descriptor *fsl_dma_prep_slave_sg(
Ira Snydera1c03312010-01-06 13:34:05 +0000769 struct dma_chan *dchan, struct scatterlist *sgl, unsigned int sg_len,
Alexandre Bounine185ecb52012-03-08 15:35:13 -0500770 enum dma_transfer_direction direction, unsigned long flags,
771 void *context)
Ira Snyderbbea0b62009-09-08 17:53:04 -0700772{
Ira Snyderbbea0b62009-09-08 17:53:04 -0700773 /*
Ira Snyder968f19a2010-09-30 11:46:46 +0000774 * This operation is not supported on the Freescale DMA controller
Ira Snyderbbea0b62009-09-08 17:53:04 -0700775 *
Ira Snyder968f19a2010-09-30 11:46:46 +0000776 * However, we need to provide the function pointer to allow the
777 * device_control() method to work.
Ira Snyderbbea0b62009-09-08 17:53:04 -0700778 */
Ira Snyderbbea0b62009-09-08 17:53:04 -0700779 return NULL;
780}
781
Linus Walleijc3635c72010-03-26 16:44:01 -0700782static int fsl_dma_device_control(struct dma_chan *dchan,
Linus Walleij05827632010-05-17 16:30:42 -0700783 enum dma_ctrl_cmd cmd, unsigned long arg)
Ira Snyderbbea0b62009-09-08 17:53:04 -0700784{
Ira Snyder968f19a2010-09-30 11:46:46 +0000785 struct dma_slave_config *config;
Ira Snydera1c03312010-01-06 13:34:05 +0000786 struct fsldma_chan *chan;
Ira Snyderbbea0b62009-09-08 17:53:04 -0700787 unsigned long flags;
Ira Snyder968f19a2010-09-30 11:46:46 +0000788 int size;
Linus Walleijc3635c72010-03-26 16:44:01 -0700789
Ira Snydera1c03312010-01-06 13:34:05 +0000790 if (!dchan)
Linus Walleijc3635c72010-03-26 16:44:01 -0700791 return -EINVAL;
Ira Snyderbbea0b62009-09-08 17:53:04 -0700792
Ira Snydera1c03312010-01-06 13:34:05 +0000793 chan = to_fsl_chan(dchan);
Ira Snyderbbea0b62009-09-08 17:53:04 -0700794
Ira Snyder968f19a2010-09-30 11:46:46 +0000795 switch (cmd) {
796 case DMA_TERMINATE_ALL:
Ira Snyderf04cd402011-03-03 07:54:58 +0000797 spin_lock_irqsave(&chan->desc_lock, flags);
798
Ira Snyder968f19a2010-09-30 11:46:46 +0000799 /* Halt the DMA engine */
800 dma_halt(chan);
Ira Snyderbbea0b62009-09-08 17:53:04 -0700801
Ira Snyder968f19a2010-09-30 11:46:46 +0000802 /* Remove and free all of the descriptors in the LD queue */
803 fsldma_free_desc_list(chan, &chan->ld_pending);
804 fsldma_free_desc_list(chan, &chan->ld_running);
Ira Snyderf04cd402011-03-03 07:54:58 +0000805 chan->idle = true;
Ira Snyderbbea0b62009-09-08 17:53:04 -0700806
Ira Snyder968f19a2010-09-30 11:46:46 +0000807 spin_unlock_irqrestore(&chan->desc_lock, flags);
808 return 0;
809
810 case DMA_SLAVE_CONFIG:
811 config = (struct dma_slave_config *)arg;
812
813 /* make sure the channel supports setting burst size */
814 if (!chan->set_request_count)
815 return -ENXIO;
816
817 /* we set the controller burst size depending on direction */
Vinod Kouldb8196d2011-10-13 22:34:23 +0530818 if (config->direction == DMA_MEM_TO_DEV)
Ira Snyder968f19a2010-09-30 11:46:46 +0000819 size = config->dst_addr_width * config->dst_maxburst;
820 else
821 size = config->src_addr_width * config->src_maxburst;
822
823 chan->set_request_count(chan, size);
824 return 0;
825
826 case FSLDMA_EXTERNAL_START:
827
828 /* make sure the channel supports external start */
829 if (!chan->toggle_ext_start)
830 return -ENXIO;
831
832 chan->toggle_ext_start(chan, arg);
833 return 0;
834
835 default:
836 return -ENXIO;
837 }
Linus Walleijc3635c72010-03-26 16:44:01 -0700838
839 return 0;
Ira Snyderbbea0b62009-09-08 17:53:04 -0700840}
841
842/**
Ira Snyder9c4d1e72011-03-03 07:54:59 +0000843 * fsldma_cleanup_descriptor - cleanup and free a single link descriptor
Ira Snyder9c3a50b2010-01-06 13:34:06 +0000844 * @chan: Freescale DMA channel
Ira Snyder9c4d1e72011-03-03 07:54:59 +0000845 * @desc: descriptor to cleanup and free
Ira Snyder9c3a50b2010-01-06 13:34:06 +0000846 *
Ira Snyder9c4d1e72011-03-03 07:54:59 +0000847 * This function is used on a descriptor which has been executed by the DMA
848 * controller. It will run any callbacks, submit any dependencies, and then
849 * free the descriptor.
Ira Snyder9c3a50b2010-01-06 13:34:06 +0000850 */
Ira Snyder9c4d1e72011-03-03 07:54:59 +0000851static void fsldma_cleanup_descriptor(struct fsldma_chan *chan,
852 struct fsl_desc_sw *desc)
Ira Snyder9c3a50b2010-01-06 13:34:06 +0000853{
Ira Snyder9c4d1e72011-03-03 07:54:59 +0000854 struct dma_async_tx_descriptor *txd = &desc->async_tx;
855 struct device *dev = chan->common.device->dev;
856 dma_addr_t src = get_desc_src(chan, desc);
857 dma_addr_t dst = get_desc_dst(chan, desc);
858 u32 len = get_desc_cnt(chan, desc);
Zhang Wei173acc72008-03-01 07:42:48 -0700859
Ira Snyder9c4d1e72011-03-03 07:54:59 +0000860 /* Run the link descriptor callback function */
861 if (txd->callback) {
862#ifdef FSL_DMA_LD_DEBUG
863 chan_dbg(chan, "LD %p callback\n", desc);
864#endif
865 txd->callback(txd->callback_param);
Zhang Wei173acc72008-03-01 07:42:48 -0700866 }
Ira Snyder9c3a50b2010-01-06 13:34:06 +0000867
Ira Snyder9c4d1e72011-03-03 07:54:59 +0000868 /* Run any dependencies */
869 dma_run_dependencies(txd);
870
871 /* Unmap the dst buffer, if requested */
872 if (!(txd->flags & DMA_COMPL_SKIP_DEST_UNMAP)) {
873 if (txd->flags & DMA_COMPL_DEST_UNMAP_SINGLE)
874 dma_unmap_single(dev, dst, len, DMA_FROM_DEVICE);
875 else
876 dma_unmap_page(dev, dst, len, DMA_FROM_DEVICE);
877 }
878
879 /* Unmap the src buffer, if requested */
880 if (!(txd->flags & DMA_COMPL_SKIP_SRC_UNMAP)) {
881 if (txd->flags & DMA_COMPL_SRC_UNMAP_SINGLE)
882 dma_unmap_single(dev, src, len, DMA_TO_DEVICE);
883 else
884 dma_unmap_page(dev, src, len, DMA_TO_DEVICE);
885 }
886
887#ifdef FSL_DMA_LD_DEBUG
888 chan_dbg(chan, "LD %p free\n", desc);
889#endif
890 dma_pool_free(chan->desc_pool, desc, txd->phys);
Zhang Wei173acc72008-03-01 07:42:48 -0700891}
892
893/**
Ira Snyder9c3a50b2010-01-06 13:34:06 +0000894 * fsl_chan_xfer_ld_queue - transfer any pending transactions
Ira Snydera1c03312010-01-06 13:34:05 +0000895 * @chan : Freescale DMA channel
Ira Snyder9c3a50b2010-01-06 13:34:06 +0000896 *
Ira Snyderf04cd402011-03-03 07:54:58 +0000897 * HARDWARE STATE: idle
Ira Snyderdc8d4092011-03-03 07:55:00 +0000898 * LOCKING: must hold chan->desc_lock
Zhang Wei173acc72008-03-01 07:42:48 -0700899 */
Ira Snydera1c03312010-01-06 13:34:05 +0000900static void fsl_chan_xfer_ld_queue(struct fsldma_chan *chan)
Zhang Wei173acc72008-03-01 07:42:48 -0700901{
Ira Snyder9c3a50b2010-01-06 13:34:06 +0000902 struct fsl_desc_sw *desc;
Ira Snyder138ef012009-05-19 15:42:13 -0700903
Ira Snyder9c3a50b2010-01-06 13:34:06 +0000904 /*
905 * If the list of pending descriptors is empty, then we
906 * don't need to do any work at all
907 */
908 if (list_empty(&chan->ld_pending)) {
Ira Snyderb1584712011-03-03 07:54:55 +0000909 chan_dbg(chan, "no pending LDs\n");
Ira Snyderdc8d4092011-03-03 07:55:00 +0000910 return;
Ira Snyder9c3a50b2010-01-06 13:34:06 +0000911 }
Zhang Wei173acc72008-03-01 07:42:48 -0700912
Ira Snyder9c3a50b2010-01-06 13:34:06 +0000913 /*
Ira Snyderf04cd402011-03-03 07:54:58 +0000914 * The DMA controller is not idle, which means that the interrupt
915 * handler will start any queued transactions when it runs after
916 * this transaction finishes
Ira Snyder9c3a50b2010-01-06 13:34:06 +0000917 */
Ira Snyderf04cd402011-03-03 07:54:58 +0000918 if (!chan->idle) {
Ira Snyderb1584712011-03-03 07:54:55 +0000919 chan_dbg(chan, "DMA controller still busy\n");
Ira Snyderdc8d4092011-03-03 07:55:00 +0000920 return;
Ira Snyder9c3a50b2010-01-06 13:34:06 +0000921 }
922
923 /*
Ira Snyder9c3a50b2010-01-06 13:34:06 +0000924 * If there are some link descriptors which have not been
925 * transferred, we need to start the controller
Zhang Wei173acc72008-03-01 07:42:48 -0700926 */
Zhang Wei173acc72008-03-01 07:42:48 -0700927
Ira Snyder9c3a50b2010-01-06 13:34:06 +0000928 /*
929 * Move all elements from the queue of pending transactions
930 * onto the list of running transactions
931 */
Ira Snyderf04cd402011-03-03 07:54:58 +0000932 chan_dbg(chan, "idle, starting controller\n");
Ira Snyder9c3a50b2010-01-06 13:34:06 +0000933 desc = list_first_entry(&chan->ld_pending, struct fsl_desc_sw, node);
934 list_splice_tail_init(&chan->ld_pending, &chan->ld_running);
Zhang Wei173acc72008-03-01 07:42:48 -0700935
Ira Snyder9c3a50b2010-01-06 13:34:06 +0000936 /*
Ira Snyderf04cd402011-03-03 07:54:58 +0000937 * The 85xx DMA controller doesn't clear the channel start bit
938 * automatically at the end of a transfer. Therefore we must clear
939 * it in software before starting the transfer.
940 */
941 if ((chan->feature & FSL_DMA_IP_MASK) == FSL_DMA_IP_85XX) {
942 u32 mode;
943
944 mode = DMA_IN(chan, &chan->regs->mr, 32);
945 mode &= ~FSL_DMA_MR_CS;
946 DMA_OUT(chan, &chan->regs->mr, mode, 32);
947 }
948
949 /*
Ira Snyder9c3a50b2010-01-06 13:34:06 +0000950 * Program the descriptor's address into the DMA controller,
951 * then start the DMA transaction
952 */
953 set_cdar(chan, desc->async_tx.phys);
Ira Snyderf04cd402011-03-03 07:54:58 +0000954 get_cdar(chan);
Ira Snyder138ef012009-05-19 15:42:13 -0700955
Zhang Wei173acc72008-03-01 07:42:48 -0700956 dma_start(chan);
Ira Snyderf04cd402011-03-03 07:54:58 +0000957 chan->idle = false;
Zhang Wei173acc72008-03-01 07:42:48 -0700958}
959
960/**
961 * fsl_dma_memcpy_issue_pending - Issue the DMA start command
Ira Snydera1c03312010-01-06 13:34:05 +0000962 * @chan : Freescale DMA channel
Zhang Wei173acc72008-03-01 07:42:48 -0700963 */
Ira Snydera1c03312010-01-06 13:34:05 +0000964static void fsl_dma_memcpy_issue_pending(struct dma_chan *dchan)
Zhang Wei173acc72008-03-01 07:42:48 -0700965{
Ira Snydera1c03312010-01-06 13:34:05 +0000966 struct fsldma_chan *chan = to_fsl_chan(dchan);
Ira Snyderdc8d4092011-03-03 07:55:00 +0000967 unsigned long flags;
968
969 spin_lock_irqsave(&chan->desc_lock, flags);
Ira Snydera1c03312010-01-06 13:34:05 +0000970 fsl_chan_xfer_ld_queue(chan);
Ira Snyderdc8d4092011-03-03 07:55:00 +0000971 spin_unlock_irqrestore(&chan->desc_lock, flags);
Zhang Wei173acc72008-03-01 07:42:48 -0700972}
973
Zhang Wei173acc72008-03-01 07:42:48 -0700974/**
Linus Walleij07934482010-03-26 16:50:49 -0700975 * fsl_tx_status - Determine the DMA status
Ira Snydera1c03312010-01-06 13:34:05 +0000976 * @chan : Freescale DMA channel
Zhang Wei173acc72008-03-01 07:42:48 -0700977 */
Linus Walleij07934482010-03-26 16:50:49 -0700978static enum dma_status fsl_tx_status(struct dma_chan *dchan,
Zhang Wei173acc72008-03-01 07:42:48 -0700979 dma_cookie_t cookie,
Linus Walleij07934482010-03-26 16:50:49 -0700980 struct dma_tx_state *txstate)
Zhang Wei173acc72008-03-01 07:42:48 -0700981{
Ira Snydera1c03312010-01-06 13:34:05 +0000982 struct fsldma_chan *chan = to_fsl_chan(dchan);
Russell King - ARM Linux96a2af42012-03-06 22:35:27 +0000983 enum dma_status ret;
Ira Snyderf04cd402011-03-03 07:54:58 +0000984 unsigned long flags;
Zhang Wei173acc72008-03-01 07:42:48 -0700985
Ira Snyderf04cd402011-03-03 07:54:58 +0000986 spin_lock_irqsave(&chan->desc_lock, flags);
Russell King - ARM Linux96a2af42012-03-06 22:35:27 +0000987 ret = dma_cookie_status(dchan, cookie, txstate);
Ira Snyderf04cd402011-03-03 07:54:58 +0000988 spin_unlock_irqrestore(&chan->desc_lock, flags);
Zhang Wei173acc72008-03-01 07:42:48 -0700989
Russell King - ARM Linux96a2af42012-03-06 22:35:27 +0000990 return ret;
Zhang Wei173acc72008-03-01 07:42:48 -0700991}
992
Ira Snyderd3f620b2010-01-06 13:34:04 +0000993/*----------------------------------------------------------------------------*/
994/* Interrupt Handling */
995/*----------------------------------------------------------------------------*/
996
Ira Snydere7a29152010-01-06 13:34:03 +0000997static irqreturn_t fsldma_chan_irq(int irq, void *data)
Zhang Wei173acc72008-03-01 07:42:48 -0700998{
Ira Snydera1c03312010-01-06 13:34:05 +0000999 struct fsldma_chan *chan = data;
Ira Snydera1c03312010-01-06 13:34:05 +00001000 u32 stat;
Zhang Wei173acc72008-03-01 07:42:48 -07001001
Ira Snyder9c3a50b2010-01-06 13:34:06 +00001002 /* save and clear the status register */
Ira Snydera1c03312010-01-06 13:34:05 +00001003 stat = get_sr(chan);
Ira Snyder9c3a50b2010-01-06 13:34:06 +00001004 set_sr(chan, stat);
Ira Snyderb1584712011-03-03 07:54:55 +00001005 chan_dbg(chan, "irq: stat = 0x%x\n", stat);
Zhang Wei173acc72008-03-01 07:42:48 -07001006
Ira Snyderf04cd402011-03-03 07:54:58 +00001007 /* check that this was really our device */
Zhang Wei173acc72008-03-01 07:42:48 -07001008 stat &= ~(FSL_DMA_SR_CB | FSL_DMA_SR_CH);
1009 if (!stat)
1010 return IRQ_NONE;
1011
1012 if (stat & FSL_DMA_SR_TE)
Ira Snyderb1584712011-03-03 07:54:55 +00001013 chan_err(chan, "Transfer Error!\n");
Zhang Wei173acc72008-03-01 07:42:48 -07001014
Ira Snyder9c3a50b2010-01-06 13:34:06 +00001015 /*
1016 * Programming Error
Zhang Weif79abb62008-03-18 18:45:00 -07001017 * The DMA_INTERRUPT async_tx is a NULL transfer, which will
1018 * triger a PE interrupt.
1019 */
1020 if (stat & FSL_DMA_SR_PE) {
Ira Snyderb1584712011-03-03 07:54:55 +00001021 chan_dbg(chan, "irq: Programming Error INT\n");
Zhang Weif79abb62008-03-18 18:45:00 -07001022 stat &= ~FSL_DMA_SR_PE;
Ira Snyderf04cd402011-03-03 07:54:58 +00001023 if (get_bcr(chan) != 0)
1024 chan_err(chan, "Programming Error!\n");
Zhang Wei1c629792008-04-17 20:17:25 -07001025 }
1026
Ira Snyder9c3a50b2010-01-06 13:34:06 +00001027 /*
1028 * For MPC8349, EOCDI event need to update cookie
Zhang Wei1c629792008-04-17 20:17:25 -07001029 * and start the next transfer if it exist.
1030 */
1031 if (stat & FSL_DMA_SR_EOCDI) {
Ira Snyderb1584712011-03-03 07:54:55 +00001032 chan_dbg(chan, "irq: End-of-Chain link INT\n");
Zhang Wei1c629792008-04-17 20:17:25 -07001033 stat &= ~FSL_DMA_SR_EOCDI;
Zhang Wei173acc72008-03-01 07:42:48 -07001034 }
1035
Ira Snyder9c3a50b2010-01-06 13:34:06 +00001036 /*
1037 * If it current transfer is the end-of-transfer,
Zhang Wei173acc72008-03-01 07:42:48 -07001038 * we should clear the Channel Start bit for
1039 * prepare next transfer.
1040 */
Zhang Wei1c629792008-04-17 20:17:25 -07001041 if (stat & FSL_DMA_SR_EOLNI) {
Ira Snyderb1584712011-03-03 07:54:55 +00001042 chan_dbg(chan, "irq: End-of-link INT\n");
Zhang Wei173acc72008-03-01 07:42:48 -07001043 stat &= ~FSL_DMA_SR_EOLNI;
Zhang Wei173acc72008-03-01 07:42:48 -07001044 }
1045
Ira Snyderf04cd402011-03-03 07:54:58 +00001046 /* check that the DMA controller is really idle */
1047 if (!dma_is_idle(chan))
1048 chan_err(chan, "irq: controller not idle!\n");
Zhang Wei173acc72008-03-01 07:42:48 -07001049
Ira Snyderf04cd402011-03-03 07:54:58 +00001050 /* check that we handled all of the bits */
1051 if (stat)
1052 chan_err(chan, "irq: unhandled sr 0x%08x\n", stat);
1053
1054 /*
1055 * Schedule the tasklet to handle all cleanup of the current
1056 * transaction. It will start a new transaction if there is
1057 * one pending.
1058 */
Ira Snydera1c03312010-01-06 13:34:05 +00001059 tasklet_schedule(&chan->tasklet);
Ira Snyderf04cd402011-03-03 07:54:58 +00001060 chan_dbg(chan, "irq: Exit\n");
Zhang Wei173acc72008-03-01 07:42:48 -07001061 return IRQ_HANDLED;
1062}
1063
Zhang Wei173acc72008-03-01 07:42:48 -07001064static void dma_do_tasklet(unsigned long data)
1065{
Ira Snydera1c03312010-01-06 13:34:05 +00001066 struct fsldma_chan *chan = (struct fsldma_chan *)data;
Ira Snyderdc8d4092011-03-03 07:55:00 +00001067 struct fsl_desc_sw *desc, *_desc;
1068 LIST_HEAD(ld_cleanup);
Ira Snyderf04cd402011-03-03 07:54:58 +00001069 unsigned long flags;
1070
1071 chan_dbg(chan, "tasklet entry\n");
1072
Ira Snyderf04cd402011-03-03 07:54:58 +00001073 spin_lock_irqsave(&chan->desc_lock, flags);
Ira Snyderdc8d4092011-03-03 07:55:00 +00001074
1075 /* update the cookie if we have some descriptors to cleanup */
1076 if (!list_empty(&chan->ld_running)) {
1077 dma_cookie_t cookie;
1078
1079 desc = to_fsl_desc(chan->ld_running.prev);
1080 cookie = desc->async_tx.cookie;
Russell King - ARM Linuxf7fbce02012-03-06 22:35:07 +00001081 dma_cookie_complete(&desc->async_tx);
Ira Snyderdc8d4092011-03-03 07:55:00 +00001082
Ira Snyderdc8d4092011-03-03 07:55:00 +00001083 chan_dbg(chan, "completed_cookie=%d\n", cookie);
1084 }
1085
1086 /*
1087 * move the descriptors to a temporary list so we can drop the lock
1088 * during the entire cleanup operation
1089 */
1090 list_splice_tail_init(&chan->ld_running, &ld_cleanup);
1091
1092 /* the hardware is now idle and ready for more */
Ira Snyderf04cd402011-03-03 07:54:58 +00001093 chan->idle = true;
Ira Snyderdc8d4092011-03-03 07:55:00 +00001094
1095 /*
1096 * Start any pending transactions automatically
1097 *
1098 * In the ideal case, we keep the DMA controller busy while we go
1099 * ahead and free the descriptors below.
1100 */
1101 fsl_chan_xfer_ld_queue(chan);
Ira Snyderf04cd402011-03-03 07:54:58 +00001102 spin_unlock_irqrestore(&chan->desc_lock, flags);
1103
Ira Snyderdc8d4092011-03-03 07:55:00 +00001104 /* Run the callback for each descriptor, in order */
1105 list_for_each_entry_safe(desc, _desc, &ld_cleanup, node) {
1106
1107 /* Remove from the list of transactions */
1108 list_del(&desc->node);
1109
1110 /* Run all cleanup for this descriptor */
1111 fsldma_cleanup_descriptor(chan, desc);
1112 }
1113
Ira Snyderf04cd402011-03-03 07:54:58 +00001114 chan_dbg(chan, "tasklet exit\n");
Zhang Wei173acc72008-03-01 07:42:48 -07001115}
1116
Ira Snyderd3f620b2010-01-06 13:34:04 +00001117static irqreturn_t fsldma_ctrl_irq(int irq, void *data)
1118{
1119 struct fsldma_device *fdev = data;
1120 struct fsldma_chan *chan;
1121 unsigned int handled = 0;
1122 u32 gsr, mask;
1123 int i;
1124
1125 gsr = (fdev->feature & FSL_DMA_BIG_ENDIAN) ? in_be32(fdev->regs)
1126 : in_le32(fdev->regs);
1127 mask = 0xff000000;
1128 dev_dbg(fdev->dev, "IRQ: gsr 0x%.8x\n", gsr);
1129
1130 for (i = 0; i < FSL_DMA_MAX_CHANS_PER_DEVICE; i++) {
1131 chan = fdev->chan[i];
1132 if (!chan)
1133 continue;
1134
1135 if (gsr & mask) {
1136 dev_dbg(fdev->dev, "IRQ: chan %d\n", chan->id);
1137 fsldma_chan_irq(irq, chan);
1138 handled++;
1139 }
1140
1141 gsr &= ~mask;
1142 mask >>= 8;
1143 }
1144
1145 return IRQ_RETVAL(handled);
1146}
1147
1148static void fsldma_free_irqs(struct fsldma_device *fdev)
1149{
1150 struct fsldma_chan *chan;
1151 int i;
1152
1153 if (fdev->irq != NO_IRQ) {
1154 dev_dbg(fdev->dev, "free per-controller IRQ\n");
1155 free_irq(fdev->irq, fdev);
1156 return;
1157 }
1158
1159 for (i = 0; i < FSL_DMA_MAX_CHANS_PER_DEVICE; i++) {
1160 chan = fdev->chan[i];
1161 if (chan && chan->irq != NO_IRQ) {
Ira Snyderb1584712011-03-03 07:54:55 +00001162 chan_dbg(chan, "free per-channel IRQ\n");
Ira Snyderd3f620b2010-01-06 13:34:04 +00001163 free_irq(chan->irq, chan);
1164 }
1165 }
1166}
1167
1168static int fsldma_request_irqs(struct fsldma_device *fdev)
1169{
1170 struct fsldma_chan *chan;
1171 int ret;
1172 int i;
1173
1174 /* if we have a per-controller IRQ, use that */
1175 if (fdev->irq != NO_IRQ) {
1176 dev_dbg(fdev->dev, "request per-controller IRQ\n");
1177 ret = request_irq(fdev->irq, fsldma_ctrl_irq, IRQF_SHARED,
1178 "fsldma-controller", fdev);
1179 return ret;
1180 }
1181
1182 /* no per-controller IRQ, use the per-channel IRQs */
1183 for (i = 0; i < FSL_DMA_MAX_CHANS_PER_DEVICE; i++) {
1184 chan = fdev->chan[i];
1185 if (!chan)
1186 continue;
1187
1188 if (chan->irq == NO_IRQ) {
Ira Snyderb1584712011-03-03 07:54:55 +00001189 chan_err(chan, "interrupts property missing in device tree\n");
Ira Snyderd3f620b2010-01-06 13:34:04 +00001190 ret = -ENODEV;
1191 goto out_unwind;
1192 }
1193
Ira Snyderb1584712011-03-03 07:54:55 +00001194 chan_dbg(chan, "request per-channel IRQ\n");
Ira Snyderd3f620b2010-01-06 13:34:04 +00001195 ret = request_irq(chan->irq, fsldma_chan_irq, IRQF_SHARED,
1196 "fsldma-chan", chan);
1197 if (ret) {
Ira Snyderb1584712011-03-03 07:54:55 +00001198 chan_err(chan, "unable to request per-channel IRQ\n");
Ira Snyderd3f620b2010-01-06 13:34:04 +00001199 goto out_unwind;
1200 }
1201 }
1202
1203 return 0;
1204
1205out_unwind:
1206 for (/* none */; i >= 0; i--) {
1207 chan = fdev->chan[i];
1208 if (!chan)
1209 continue;
1210
1211 if (chan->irq == NO_IRQ)
1212 continue;
1213
1214 free_irq(chan->irq, chan);
1215 }
1216
1217 return ret;
1218}
1219
Ira Snydera4f56d42010-01-06 13:34:01 +00001220/*----------------------------------------------------------------------------*/
1221/* OpenFirmware Subsystem */
1222/*----------------------------------------------------------------------------*/
1223
1224static int __devinit fsl_dma_chan_probe(struct fsldma_device *fdev,
Timur Tabi77cd62e2008-09-26 17:00:11 -07001225 struct device_node *node, u32 feature, const char *compatible)
Zhang Wei173acc72008-03-01 07:42:48 -07001226{
Ira Snydera1c03312010-01-06 13:34:05 +00001227 struct fsldma_chan *chan;
Ira Snyder4ce0e952010-01-06 13:34:00 +00001228 struct resource res;
Zhang Wei173acc72008-03-01 07:42:48 -07001229 int err;
1230
Zhang Wei173acc72008-03-01 07:42:48 -07001231 /* alloc channel */
Ira Snydera1c03312010-01-06 13:34:05 +00001232 chan = kzalloc(sizeof(*chan), GFP_KERNEL);
1233 if (!chan) {
Ira Snydere7a29152010-01-06 13:34:03 +00001234 dev_err(fdev->dev, "no free memory for DMA channels!\n");
1235 err = -ENOMEM;
1236 goto out_return;
Zhang Wei173acc72008-03-01 07:42:48 -07001237 }
1238
Ira Snydere7a29152010-01-06 13:34:03 +00001239 /* ioremap registers for use */
Ira Snydera1c03312010-01-06 13:34:05 +00001240 chan->regs = of_iomap(node, 0);
1241 if (!chan->regs) {
Ira Snydere7a29152010-01-06 13:34:03 +00001242 dev_err(fdev->dev, "unable to ioremap registers\n");
1243 err = -ENOMEM;
Ira Snydera1c03312010-01-06 13:34:05 +00001244 goto out_free_chan;
Ira Snydere7a29152010-01-06 13:34:03 +00001245 }
1246
Ira Snyder4ce0e952010-01-06 13:34:00 +00001247 err = of_address_to_resource(node, 0, &res);
Zhang Wei173acc72008-03-01 07:42:48 -07001248 if (err) {
Ira Snydere7a29152010-01-06 13:34:03 +00001249 dev_err(fdev->dev, "unable to find 'reg' property\n");
1250 goto out_iounmap_regs;
Zhang Wei173acc72008-03-01 07:42:48 -07001251 }
1252
Ira Snydera1c03312010-01-06 13:34:05 +00001253 chan->feature = feature;
Zhang Wei173acc72008-03-01 07:42:48 -07001254 if (!fdev->feature)
Ira Snydera1c03312010-01-06 13:34:05 +00001255 fdev->feature = chan->feature;
Zhang Wei173acc72008-03-01 07:42:48 -07001256
Ira Snydere7a29152010-01-06 13:34:03 +00001257 /*
1258 * If the DMA device's feature is different than the feature
1259 * of its channels, report the bug
Zhang Wei173acc72008-03-01 07:42:48 -07001260 */
Ira Snydera1c03312010-01-06 13:34:05 +00001261 WARN_ON(fdev->feature != chan->feature);
Zhang Wei173acc72008-03-01 07:42:48 -07001262
Ira Snydera1c03312010-01-06 13:34:05 +00001263 chan->dev = fdev->dev;
1264 chan->id = ((res.start - 0x100) & 0xfff) >> 7;
1265 if (chan->id >= FSL_DMA_MAX_CHANS_PER_DEVICE) {
Ira Snydere7a29152010-01-06 13:34:03 +00001266 dev_err(fdev->dev, "too many channels for device\n");
Zhang Wei173acc72008-03-01 07:42:48 -07001267 err = -EINVAL;
Ira Snydere7a29152010-01-06 13:34:03 +00001268 goto out_iounmap_regs;
Zhang Wei173acc72008-03-01 07:42:48 -07001269 }
Zhang Wei173acc72008-03-01 07:42:48 -07001270
Ira Snydera1c03312010-01-06 13:34:05 +00001271 fdev->chan[chan->id] = chan;
1272 tasklet_init(&chan->tasklet, dma_do_tasklet, (unsigned long)chan);
Ira Snyderb1584712011-03-03 07:54:55 +00001273 snprintf(chan->name, sizeof(chan->name), "chan%d", chan->id);
Ira Snydere7a29152010-01-06 13:34:03 +00001274
1275 /* Initialize the channel */
Ira Snydera1c03312010-01-06 13:34:05 +00001276 dma_init(chan);
Zhang Wei173acc72008-03-01 07:42:48 -07001277
1278 /* Clear cdar registers */
Ira Snydera1c03312010-01-06 13:34:05 +00001279 set_cdar(chan, 0);
Zhang Wei173acc72008-03-01 07:42:48 -07001280
Ira Snydera1c03312010-01-06 13:34:05 +00001281 switch (chan->feature & FSL_DMA_IP_MASK) {
Zhang Wei173acc72008-03-01 07:42:48 -07001282 case FSL_DMA_IP_85XX:
Ira Snydera1c03312010-01-06 13:34:05 +00001283 chan->toggle_ext_pause = fsl_chan_toggle_ext_pause;
Zhang Wei173acc72008-03-01 07:42:48 -07001284 case FSL_DMA_IP_83XX:
Ira Snydera1c03312010-01-06 13:34:05 +00001285 chan->toggle_ext_start = fsl_chan_toggle_ext_start;
1286 chan->set_src_loop_size = fsl_chan_set_src_loop_size;
1287 chan->set_dst_loop_size = fsl_chan_set_dst_loop_size;
1288 chan->set_request_count = fsl_chan_set_request_count;
Zhang Wei173acc72008-03-01 07:42:48 -07001289 }
1290
Ira Snydera1c03312010-01-06 13:34:05 +00001291 spin_lock_init(&chan->desc_lock);
Ira Snyder9c3a50b2010-01-06 13:34:06 +00001292 INIT_LIST_HEAD(&chan->ld_pending);
1293 INIT_LIST_HEAD(&chan->ld_running);
Ira Snyderf04cd402011-03-03 07:54:58 +00001294 chan->idle = true;
Zhang Wei173acc72008-03-01 07:42:48 -07001295
Ira Snydera1c03312010-01-06 13:34:05 +00001296 chan->common.device = &fdev->common;
Russell King - ARM Linux8ac69542012-03-06 22:36:27 +00001297 dma_cookie_init(&chan->common);
Zhang Wei173acc72008-03-01 07:42:48 -07001298
Ira Snyderd3f620b2010-01-06 13:34:04 +00001299 /* find the IRQ line, if it exists in the device tree */
Ira Snydera1c03312010-01-06 13:34:05 +00001300 chan->irq = irq_of_parse_and_map(node, 0);
Ira Snyderd3f620b2010-01-06 13:34:04 +00001301
Zhang Wei173acc72008-03-01 07:42:48 -07001302 /* Add the channel to DMA device channel list */
Ira Snydera1c03312010-01-06 13:34:05 +00001303 list_add_tail(&chan->common.device_node, &fdev->common.channels);
Zhang Wei173acc72008-03-01 07:42:48 -07001304 fdev->common.chancnt++;
1305
Ira Snydera1c03312010-01-06 13:34:05 +00001306 dev_info(fdev->dev, "#%d (%s), irq %d\n", chan->id, compatible,
1307 chan->irq != NO_IRQ ? chan->irq : fdev->irq);
Zhang Wei173acc72008-03-01 07:42:48 -07001308
1309 return 0;
Li Yang51ee87f2008-05-29 23:25:45 -07001310
Ira Snydere7a29152010-01-06 13:34:03 +00001311out_iounmap_regs:
Ira Snydera1c03312010-01-06 13:34:05 +00001312 iounmap(chan->regs);
1313out_free_chan:
1314 kfree(chan);
Ira Snydere7a29152010-01-06 13:34:03 +00001315out_return:
Zhang Wei173acc72008-03-01 07:42:48 -07001316 return err;
1317}
1318
Ira Snydera1c03312010-01-06 13:34:05 +00001319static void fsl_dma_chan_remove(struct fsldma_chan *chan)
Zhang Wei173acc72008-03-01 07:42:48 -07001320{
Ira Snydera1c03312010-01-06 13:34:05 +00001321 irq_dispose_mapping(chan->irq);
1322 list_del(&chan->common.device_node);
1323 iounmap(chan->regs);
1324 kfree(chan);
Zhang Wei173acc72008-03-01 07:42:48 -07001325}
1326
Grant Likely00006122011-02-22 19:59:54 -07001327static int __devinit fsldma_of_probe(struct platform_device *op)
Zhang Wei173acc72008-03-01 07:42:48 -07001328{
Ira Snydera4f56d42010-01-06 13:34:01 +00001329 struct fsldma_device *fdev;
Timur Tabi77cd62e2008-09-26 17:00:11 -07001330 struct device_node *child;
Ira Snydere7a29152010-01-06 13:34:03 +00001331 int err;
Zhang Wei173acc72008-03-01 07:42:48 -07001332
Ira Snydera4f56d42010-01-06 13:34:01 +00001333 fdev = kzalloc(sizeof(*fdev), GFP_KERNEL);
Zhang Wei173acc72008-03-01 07:42:48 -07001334 if (!fdev) {
Ira Snydere7a29152010-01-06 13:34:03 +00001335 dev_err(&op->dev, "No enough memory for 'priv'\n");
1336 err = -ENOMEM;
1337 goto out_return;
Zhang Wei173acc72008-03-01 07:42:48 -07001338 }
Ira Snydere7a29152010-01-06 13:34:03 +00001339
1340 fdev->dev = &op->dev;
Zhang Wei173acc72008-03-01 07:42:48 -07001341 INIT_LIST_HEAD(&fdev->common.channels);
1342
Ira Snydere7a29152010-01-06 13:34:03 +00001343 /* ioremap the registers for use */
Grant Likely61c7a082010-04-13 16:12:29 -07001344 fdev->regs = of_iomap(op->dev.of_node, 0);
Ira Snydere7a29152010-01-06 13:34:03 +00001345 if (!fdev->regs) {
1346 dev_err(&op->dev, "unable to ioremap registers\n");
1347 err = -ENOMEM;
1348 goto out_free_fdev;
Zhang Wei173acc72008-03-01 07:42:48 -07001349 }
1350
Ira Snyderd3f620b2010-01-06 13:34:04 +00001351 /* map the channel IRQ if it exists, but don't hookup the handler yet */
Grant Likely61c7a082010-04-13 16:12:29 -07001352 fdev->irq = irq_of_parse_and_map(op->dev.of_node, 0);
Ira Snyderd3f620b2010-01-06 13:34:04 +00001353
Zhang Wei173acc72008-03-01 07:42:48 -07001354 dma_cap_set(DMA_MEMCPY, fdev->common.cap_mask);
1355 dma_cap_set(DMA_INTERRUPT, fdev->common.cap_mask);
Ira Snyderc14330412010-09-30 11:46:45 +00001356 dma_cap_set(DMA_SG, fdev->common.cap_mask);
Ira Snyderbbea0b62009-09-08 17:53:04 -07001357 dma_cap_set(DMA_SLAVE, fdev->common.cap_mask);
Zhang Wei173acc72008-03-01 07:42:48 -07001358 fdev->common.device_alloc_chan_resources = fsl_dma_alloc_chan_resources;
1359 fdev->common.device_free_chan_resources = fsl_dma_free_chan_resources;
Zhang Wei2187c262008-03-13 17:45:28 -07001360 fdev->common.device_prep_dma_interrupt = fsl_dma_prep_interrupt;
Zhang Wei173acc72008-03-01 07:42:48 -07001361 fdev->common.device_prep_dma_memcpy = fsl_dma_prep_memcpy;
Ira Snyderc14330412010-09-30 11:46:45 +00001362 fdev->common.device_prep_dma_sg = fsl_dma_prep_sg;
Linus Walleij07934482010-03-26 16:50:49 -07001363 fdev->common.device_tx_status = fsl_tx_status;
Zhang Wei173acc72008-03-01 07:42:48 -07001364 fdev->common.device_issue_pending = fsl_dma_memcpy_issue_pending;
Ira Snyderbbea0b62009-09-08 17:53:04 -07001365 fdev->common.device_prep_slave_sg = fsl_dma_prep_slave_sg;
Linus Walleijc3635c72010-03-26 16:44:01 -07001366 fdev->common.device_control = fsl_dma_device_control;
Ira Snydere7a29152010-01-06 13:34:03 +00001367 fdev->common.dev = &op->dev;
Zhang Wei173acc72008-03-01 07:42:48 -07001368
Li Yange2c8e4252010-11-11 20:16:29 +08001369 dma_set_mask(&(op->dev), DMA_BIT_MASK(36));
1370
Ira Snydere7a29152010-01-06 13:34:03 +00001371 dev_set_drvdata(&op->dev, fdev);
Timur Tabi77cd62e2008-09-26 17:00:11 -07001372
Ira Snydere7a29152010-01-06 13:34:03 +00001373 /*
1374 * We cannot use of_platform_bus_probe() because there is no
1375 * of_platform_bus_remove(). Instead, we manually instantiate every DMA
Timur Tabi77cd62e2008-09-26 17:00:11 -07001376 * channel object.
1377 */
Grant Likely61c7a082010-04-13 16:12:29 -07001378 for_each_child_of_node(op->dev.of_node, child) {
Ira Snydere7a29152010-01-06 13:34:03 +00001379 if (of_device_is_compatible(child, "fsl,eloplus-dma-channel")) {
Timur Tabi77cd62e2008-09-26 17:00:11 -07001380 fsl_dma_chan_probe(fdev, child,
1381 FSL_DMA_IP_85XX | FSL_DMA_BIG_ENDIAN,
1382 "fsl,eloplus-dma-channel");
Ira Snydere7a29152010-01-06 13:34:03 +00001383 }
1384
1385 if (of_device_is_compatible(child, "fsl,elo-dma-channel")) {
Timur Tabi77cd62e2008-09-26 17:00:11 -07001386 fsl_dma_chan_probe(fdev, child,
1387 FSL_DMA_IP_83XX | FSL_DMA_LITTLE_ENDIAN,
1388 "fsl,elo-dma-channel");
Ira Snydere7a29152010-01-06 13:34:03 +00001389 }
Timur Tabi77cd62e2008-09-26 17:00:11 -07001390 }
Zhang Wei173acc72008-03-01 07:42:48 -07001391
Ira Snyderd3f620b2010-01-06 13:34:04 +00001392 /*
1393 * Hookup the IRQ handler(s)
1394 *
1395 * If we have a per-controller interrupt, we prefer that to the
1396 * per-channel interrupts to reduce the number of shared interrupt
1397 * handlers on the same IRQ line
1398 */
1399 err = fsldma_request_irqs(fdev);
1400 if (err) {
1401 dev_err(fdev->dev, "unable to request IRQs\n");
1402 goto out_free_fdev;
1403 }
1404
Zhang Wei173acc72008-03-01 07:42:48 -07001405 dma_async_device_register(&fdev->common);
1406 return 0;
1407
Ira Snydere7a29152010-01-06 13:34:03 +00001408out_free_fdev:
Ira Snyderd3f620b2010-01-06 13:34:04 +00001409 irq_dispose_mapping(fdev->irq);
Zhang Wei173acc72008-03-01 07:42:48 -07001410 kfree(fdev);
Ira Snydere7a29152010-01-06 13:34:03 +00001411out_return:
Zhang Wei173acc72008-03-01 07:42:48 -07001412 return err;
1413}
1414
Grant Likely2dc11582010-08-06 09:25:50 -06001415static int fsldma_of_remove(struct platform_device *op)
Timur Tabi77cd62e2008-09-26 17:00:11 -07001416{
Ira Snydera4f56d42010-01-06 13:34:01 +00001417 struct fsldma_device *fdev;
Timur Tabi77cd62e2008-09-26 17:00:11 -07001418 unsigned int i;
1419
Ira Snydere7a29152010-01-06 13:34:03 +00001420 fdev = dev_get_drvdata(&op->dev);
Timur Tabi77cd62e2008-09-26 17:00:11 -07001421 dma_async_device_unregister(&fdev->common);
1422
Ira Snyderd3f620b2010-01-06 13:34:04 +00001423 fsldma_free_irqs(fdev);
1424
Ira Snydere7a29152010-01-06 13:34:03 +00001425 for (i = 0; i < FSL_DMA_MAX_CHANS_PER_DEVICE; i++) {
Timur Tabi77cd62e2008-09-26 17:00:11 -07001426 if (fdev->chan[i])
1427 fsl_dma_chan_remove(fdev->chan[i]);
Ira Snydere7a29152010-01-06 13:34:03 +00001428 }
Timur Tabi77cd62e2008-09-26 17:00:11 -07001429
Ira Snydere7a29152010-01-06 13:34:03 +00001430 iounmap(fdev->regs);
1431 dev_set_drvdata(&op->dev, NULL);
Timur Tabi77cd62e2008-09-26 17:00:11 -07001432 kfree(fdev);
Timur Tabi77cd62e2008-09-26 17:00:11 -07001433
1434 return 0;
1435}
1436
Márton Németh4b1cf1f2010-02-02 23:41:06 -07001437static const struct of_device_id fsldma_of_ids[] = {
Kumar Gala049c9d42008-03-31 11:13:21 -05001438 { .compatible = "fsl,eloplus-dma", },
1439 { .compatible = "fsl,elo-dma", },
Zhang Wei173acc72008-03-01 07:42:48 -07001440 {}
1441};
1442
Ira W. Snyder8faa7cf2011-04-07 10:33:03 -07001443static struct platform_driver fsldma_of_driver = {
Grant Likely40182942010-04-13 16:13:02 -07001444 .driver = {
1445 .name = "fsl-elo-dma",
1446 .owner = THIS_MODULE,
1447 .of_match_table = fsldma_of_ids,
1448 },
1449 .probe = fsldma_of_probe,
1450 .remove = fsldma_of_remove,
Zhang Wei173acc72008-03-01 07:42:48 -07001451};
1452
Ira Snydera4f56d42010-01-06 13:34:01 +00001453/*----------------------------------------------------------------------------*/
1454/* Module Init / Exit */
1455/*----------------------------------------------------------------------------*/
1456
1457static __init int fsldma_init(void)
Zhang Wei173acc72008-03-01 07:42:48 -07001458{
Timur Tabi77cd62e2008-09-26 17:00:11 -07001459 pr_info("Freescale Elo / Elo Plus DMA driver\n");
Grant Likely00006122011-02-22 19:59:54 -07001460 return platform_driver_register(&fsldma_of_driver);
Zhang Wei173acc72008-03-01 07:42:48 -07001461}
1462
Ira Snydera4f56d42010-01-06 13:34:01 +00001463static void __exit fsldma_exit(void)
Timur Tabi77cd62e2008-09-26 17:00:11 -07001464{
Grant Likely00006122011-02-22 19:59:54 -07001465 platform_driver_unregister(&fsldma_of_driver);
Timur Tabi77cd62e2008-09-26 17:00:11 -07001466}
1467
Ira Snydera4f56d42010-01-06 13:34:01 +00001468subsys_initcall(fsldma_init);
1469module_exit(fsldma_exit);
Timur Tabi77cd62e2008-09-26 17:00:11 -07001470
1471MODULE_DESCRIPTION("Freescale Elo / Elo Plus DMA driver");
1472MODULE_LICENSE("GPL");