blob: 5f80312e636b25f05bd3732760d3536c24425242 [file] [log] [blame]
Sergei Shtylyov60e7a822007-05-05 22:03:49 +02001/*
Linus Torvalds1da177e2005-04-16 15:20:36 -07002 * cmd64x.c: Enable interrupts at initialization time on Ultra/PCI machines.
Linus Torvalds1da177e2005-04-16 15:20:36 -07003 * Due to massive hardware bugs, UltraDMA is only supported
4 * on the 646U2 and not on the 646U.
5 *
6 * Copyright (C) 1998 Eddie C. Dost (ecd@skynet.be)
7 * Copyright (C) 1998 David S. Miller (davem@redhat.com)
8 *
9 * Copyright (C) 1999-2002 Andre Hedrick <andre@linux-ide.org>
Bartlomiej Zolnierkiewicz60349ab2010-01-18 07:18:26 +000010 * Copyright (C) 2007-2010 Bartlomiej Zolnierkiewicz
Sergei Shtylyov30e5ffc2009-06-15 18:52:56 +020011 * Copyright (C) 2007,2009 MontaVista Software, Inc. <source@mvista.com>
Linus Torvalds1da177e2005-04-16 15:20:36 -070012 */
13
Linus Torvalds1da177e2005-04-16 15:20:36 -070014#include <linux/module.h>
15#include <linux/types.h>
16#include <linux/pci.h>
Linus Torvalds1da177e2005-04-16 15:20:36 -070017#include <linux/ide.h>
18#include <linux/init.h>
19
20#include <asm/io.h>
21
Bartlomiej Zolnierkiewiczced3ec82008-07-24 22:53:32 +020022#define DRV_NAME "cmd64x"
23
Linus Torvalds1da177e2005-04-16 15:20:36 -070024/*
25 * CMD64x specific registers definition.
26 */
27#define CFR 0x50
Sergei Shtylyove51e2522007-05-05 22:03:49 +020028#define CFR_INTR_CH0 0x04
Linus Torvalds1da177e2005-04-16 15:20:36 -070029
30#define CMDTIM 0x52
31#define ARTTIM0 0x53
32#define DRWTIM0 0x54
33#define ARTTIM1 0x55
34#define DRWTIM1 0x56
35#define ARTTIM23 0x57
36#define ARTTIM23_DIS_RA2 0x04
37#define ARTTIM23_DIS_RA3 0x08
38#define ARTTIM23_INTR_CH1 0x10
Linus Torvalds1da177e2005-04-16 15:20:36 -070039#define DRWTIM2 0x58
40#define BRST 0x59
41#define DRWTIM3 0x5b
42
43#define BMIDECR0 0x70
44#define MRDMODE 0x71
45#define MRDMODE_INTR_CH0 0x04
46#define MRDMODE_INTR_CH1 0x08
Linus Torvalds1da177e2005-04-16 15:20:36 -070047#define UDIDETCR0 0x73
48#define DTPR0 0x74
49#define BMIDECR1 0x78
50#define BMIDECSR 0x79
Linus Torvalds1da177e2005-04-16 15:20:36 -070051#define UDIDETCR1 0x7B
52#define DTPR1 0x7C
53
Bartlomiej Zolnierkiewicz60349ab2010-01-18 07:18:26 +000054static void cmd64x_program_timings(ide_drive_t *drive, u8 mode)
Sergei Shtylyove277a1a2007-03-17 21:57:24 +010055{
Bartlomiej Zolnierkiewicz60349ab2010-01-18 07:18:26 +000056 ide_hwif_t *hwif = drive->hwif;
Bartlomiej Zolnierkiewiczebae41a2008-04-27 15:38:29 +020057 struct pci_dev *dev = to_pci_dev(drive->hwif->dev);
Bartlomiej Zolnierkiewicz60349ab2010-01-18 07:18:26 +000058 int bus_speed = ide_pci_clk ? ide_pci_clk : 33;
59 const unsigned long T = 1000000 / bus_speed;
Sergei Shtylyov60e7a822007-05-05 22:03:49 +020060 static const u8 recovery_values[] =
Linus Torvalds1da177e2005-04-16 15:20:36 -070061 {15, 15, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 0};
Bartlomiej Zolnierkiewicz60349ab2010-01-18 07:18:26 +000062 static const u8 setup_values[] = {0x40, 0x40, 0x40, 0x80, 0, 0xc0};
63 static const u8 arttim_regs[4] = {ARTTIM0, ARTTIM1, ARTTIM23, ARTTIM23};
Sergei Shtylyov60e7a822007-05-05 22:03:49 +020064 static const u8 drwtim_regs[4] = {DRWTIM0, DRWTIM1, DRWTIM2, DRWTIM3};
Bartlomiej Zolnierkiewicz60349ab2010-01-18 07:18:26 +000065 struct ide_timing t;
66 u8 arttim = 0;
Linus Torvalds1da177e2005-04-16 15:20:36 -070067
Bartlomiej Zolnierkiewicz60349ab2010-01-18 07:18:26 +000068 ide_timing_compute(drive, mode, &t, T, 0);
Linus Torvalds1da177e2005-04-16 15:20:36 -070069
70 /*
Sergei Shtylyov60e7a822007-05-05 22:03:49 +020071 * In case we've got too long recovery phase, try to lengthen
72 * the active phase
Linus Torvalds1da177e2005-04-16 15:20:36 -070073 */
Bartlomiej Zolnierkiewicz60349ab2010-01-18 07:18:26 +000074 if (t.recover > 16) {
75 t.active += t.recover - 16;
76 t.recover = 16;
Linus Torvalds1da177e2005-04-16 15:20:36 -070077 }
Bartlomiej Zolnierkiewicz60349ab2010-01-18 07:18:26 +000078 if (t.active > 16) /* shouldn't actually happen... */
79 t.active = 16;
Linus Torvalds1da177e2005-04-16 15:20:36 -070080
Sergei Shtylyov60e7a822007-05-05 22:03:49 +020081 /*
82 * Convert values to internal chipset representation
83 */
Bartlomiej Zolnierkiewicz60349ab2010-01-18 07:18:26 +000084 t.recover = recovery_values[t.recover];
85 t.active &= 0x0f;
Sergei Shtylyov60e7a822007-05-05 22:03:49 +020086
87 /* Program the active/recovery counts into the DRWTIM register */
Bartlomiej Zolnierkiewicz60349ab2010-01-18 07:18:26 +000088 pci_write_config_byte(dev, drwtim_regs[drive->dn],
89 (t.active << 4) | t.recover);
Sergei Shtylyov60e7a822007-05-05 22:03:49 +020090
Sergei Shtylyov60e7a822007-05-05 22:03:49 +020091 /*
92 * The primary channel has individual address setup timing registers
93 * for each drive and the hardware selects the slowest timing itself.
94 * The secondary channel has one common register and we have to select
95 * the slowest address setup timing ourselves.
96 */
97 if (hwif->channel) {
Bartlomiej Zolnierkiewicz5d44a152009-01-06 17:20:55 +010098 ide_drive_t *pair = ide_get_pair_dev(drive);
Sergei Shtylyov60e7a822007-05-05 22:03:49 +020099
Bartlomiej Zolnierkiewicz23d87402010-01-18 07:21:41 +0000100 if (pair) {
101 struct ide_timing tp;
Bartlomiej Zolnierkiewicz5d44a152009-01-06 17:20:55 +0100102
Bartlomiej Zolnierkiewicz23d87402010-01-18 07:21:41 +0000103 ide_timing_compute(pair, pair->pio_mode, &tp, T, 0);
104 ide_timing_merge(&t, &tp, &t, IDE_TIMING_SETUP);
105 if (pair->dma_mode) {
106 ide_timing_compute(pair, pair->dma_mode,
107 &tp, T, 0);
108 ide_timing_merge(&tp, &t, &t, IDE_TIMING_SETUP);
109 }
110 }
Sergei Shtylyov60e7a822007-05-05 22:03:49 +0200111 }
112
Bartlomiej Zolnierkiewicz60349ab2010-01-18 07:18:26 +0000113 if (t.setup > 5) /* shouldn't actually happen... */
114 t.setup = 5;
Sergei Shtylyov60e7a822007-05-05 22:03:49 +0200115
116 /*
117 * Program the address setup clocks into the ARTTIM registers.
118 * Avoid clearing the secondary channel's interrupt bit.
119 */
120 (void) pci_read_config_byte (dev, arttim_regs[drive->dn], &arttim);
121 if (hwif->channel)
122 arttim &= ~ARTTIM23_INTR_CH1;
123 arttim &= ~0xc0;
Bartlomiej Zolnierkiewicz60349ab2010-01-18 07:18:26 +0000124 arttim |= setup_values[t.setup];
Sergei Shtylyov60e7a822007-05-05 22:03:49 +0200125 (void) pci_write_config_byte(dev, arttim_regs[drive->dn], arttim);
Sergei Shtylyovf92d50e2007-03-03 17:48:53 +0100126}
127
128/*
129 * Attempts to set drive's PIO mode.
Bartlomiej Zolnierkiewicz26bcb872007-10-11 23:54:00 +0200130 * Special cases are 8: prefetch off, 9: prefetch on (both never worked)
Sergei Shtylyovf92d50e2007-03-03 17:48:53 +0100131 */
Bartlomiej Zolnierkiewicz26bcb872007-10-11 23:54:00 +0200132
Bartlomiej Zolnierkiewicze085b3c2010-01-19 01:44:41 -0800133static void cmd64x_set_pio_mode(ide_hwif_t *hwif, ide_drive_t *drive)
Sergei Shtylyovf92d50e2007-03-03 17:48:53 +0100134{
Bartlomiej Zolnierkiewicze085b3c2010-01-19 01:44:41 -0800135 const u8 pio = drive->pio_mode - XFER_PIO_0;
136
Sergei Shtylyovf92d50e2007-03-03 17:48:53 +0100137 /*
138 * Filter out the prefetch control values
139 * to prevent PIO5 from being programmed
140 */
141 if (pio == 8 || pio == 9)
142 return;
143
Bartlomiej Zolnierkiewicz60349ab2010-01-18 07:18:26 +0000144 cmd64x_program_timings(drive, XFER_PIO_0 + pio);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700145}
146
Bartlomiej Zolnierkiewicz87761682010-01-19 01:45:29 -0800147static void cmd64x_set_dma_mode(ide_hwif_t *hwif, ide_drive_t *drive)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700148{
Bartlomiej Zolnierkiewicz36501652008-02-01 23:09:31 +0100149 struct pci_dev *dev = to_pci_dev(hwif->dev);
Sergei Shtylyov60e7a822007-05-05 22:03:49 +0200150 u8 unit = drive->dn & 0x01;
151 u8 regU = 0, pciU = hwif->channel ? UDIDETCR1 : UDIDETCR0;
Bartlomiej Zolnierkiewicz87761682010-01-19 01:45:29 -0800152 const u8 speed = drive->dma_mode;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700153
Bartlomiej Zolnierkiewicz22cabc22010-01-18 07:18:38 +0000154 pci_read_config_byte(dev, pciU, &regU);
155 regU &= ~(unit ? 0xCA : 0x35);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700156
157 switch(speed) {
Sergei Shtylyov60e7a822007-05-05 22:03:49 +0200158 case XFER_UDMA_5:
159 regU |= unit ? 0x0A : 0x05;
160 break;
161 case XFER_UDMA_4:
162 regU |= unit ? 0x4A : 0x15;
163 break;
164 case XFER_UDMA_3:
165 regU |= unit ? 0x8A : 0x25;
166 break;
167 case XFER_UDMA_2:
168 regU |= unit ? 0x42 : 0x11;
169 break;
170 case XFER_UDMA_1:
171 regU |= unit ? 0x82 : 0x21;
172 break;
173 case XFER_UDMA_0:
174 regU |= unit ? 0xC2 : 0x31;
175 break;
176 case XFER_MW_DMA_2:
Sergei Shtylyov60e7a822007-05-05 22:03:49 +0200177 case XFER_MW_DMA_1:
Sergei Shtylyov60e7a822007-05-05 22:03:49 +0200178 case XFER_MW_DMA_0:
Bartlomiej Zolnierkiewicz60349ab2010-01-18 07:18:26 +0000179 cmd64x_program_timings(drive, speed);
Sergei Shtylyov60e7a822007-05-05 22:03:49 +0200180 break;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700181 }
182
Bartlomiej Zolnierkiewicz22cabc22010-01-18 07:18:38 +0000183 pci_write_config_byte(dev, pciU, regU);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700184}
185
Sergei Shtylyov30e5ffc2009-06-15 18:52:56 +0200186static void cmd648_clear_irq(ide_drive_t *drive)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700187{
Bartlomiej Zolnierkiewicz898ec222009-01-06 17:20:52 +0100188 ide_hwif_t *hwif = drive->hwif;
Sergei Shtylyov30e5ffc2009-06-15 18:52:56 +0200189 struct pci_dev *dev = to_pci_dev(hwif->dev);
190 unsigned long base = pci_resource_start(dev, 4);
Sergei Shtylyov66602c82007-05-05 22:03:50 +0200191 u8 irq_mask = hwif->channel ? MRDMODE_INTR_CH1 :
192 MRDMODE_INTR_CH0;
Bartlomiej Zolnierkiewicz1c029fd2008-01-25 22:17:05 +0100193 u8 mrdmode = inb(base + 1);
Sergei Shtylyov66602c82007-05-05 22:03:50 +0200194
195 /* clear the interrupt bit */
Sergei Shtylyov61832892007-11-13 22:09:14 +0100196 outb((mrdmode & ~(MRDMODE_INTR_CH0 | MRDMODE_INTR_CH1)) | irq_mask,
Bartlomiej Zolnierkiewicz1c029fd2008-01-25 22:17:05 +0100197 base + 1);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700198}
199
Sergei Shtylyov30e5ffc2009-06-15 18:52:56 +0200200static void cmd64x_clear_irq(ide_drive_t *drive)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700201{
Bartlomiej Zolnierkiewicz898ec222009-01-06 17:20:52 +0100202 ide_hwif_t *hwif = drive->hwif;
Bartlomiej Zolnierkiewicz36501652008-02-01 23:09:31 +0100203 struct pci_dev *dev = to_pci_dev(hwif->dev);
Sergei Shtylyov66602c82007-05-05 22:03:50 +0200204 int irq_reg = hwif->channel ? ARTTIM23 : CFR;
205 u8 irq_mask = hwif->channel ? ARTTIM23_INTR_CH1 :
206 CFR_INTR_CH0;
207 u8 irq_stat = 0;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700208
Sergei Shtylyov66602c82007-05-05 22:03:50 +0200209 (void) pci_read_config_byte(dev, irq_reg, &irq_stat);
210 /* clear the interrupt bit */
211 (void) pci_write_config_byte(dev, irq_reg, irq_stat | irq_mask);
Sergei Shtylyov66602c82007-05-05 22:03:50 +0200212}
213
Sergei Shtylyov628df2f2009-06-15 18:52:59 +0200214static int cmd648_test_irq(ide_hwif_t *hwif)
Sergei Shtylyov66602c82007-05-05 22:03:50 +0200215{
Sergei Shtylyov628df2f2009-06-15 18:52:59 +0200216 struct pci_dev *dev = to_pci_dev(hwif->dev);
217 unsigned long base = pci_resource_start(dev, 4);
Sergei Shtylyov66602c82007-05-05 22:03:50 +0200218 u8 irq_mask = hwif->channel ? MRDMODE_INTR_CH1 :
219 MRDMODE_INTR_CH0;
Bartlomiej Zolnierkiewicz1c029fd2008-01-25 22:17:05 +0100220 u8 mrdmode = inb(base + 1);
Sergei Shtylyov66602c82007-05-05 22:03:50 +0200221
Sergei Shtylyov628df2f2009-06-15 18:52:59 +0200222 pr_debug("%s: mrdmode: 0x%02x irq_mask: 0x%02x\n",
223 hwif->name, mrdmode, irq_mask);
Sergei Shtylyov66602c82007-05-05 22:03:50 +0200224
Sergei Shtylyov628df2f2009-06-15 18:52:59 +0200225 return (mrdmode & irq_mask) ? 1 : 0;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700226}
227
Sergei Shtylyov628df2f2009-06-15 18:52:59 +0200228static int cmd64x_test_irq(ide_hwif_t *hwif)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700229{
Bartlomiej Zolnierkiewicz36501652008-02-01 23:09:31 +0100230 struct pci_dev *dev = to_pci_dev(hwif->dev);
Sergei Shtylyov66602c82007-05-05 22:03:50 +0200231 int irq_reg = hwif->channel ? ARTTIM23 : CFR;
232 u8 irq_mask = hwif->channel ? ARTTIM23_INTR_CH1 :
233 CFR_INTR_CH0;
Sergei Shtylyov66602c82007-05-05 22:03:50 +0200234 u8 irq_stat = 0;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700235
Sergei Shtylyove51e2522007-05-05 22:03:49 +0200236 (void) pci_read_config_byte(dev, irq_reg, &irq_stat);
237
Sergei Shtylyov628df2f2009-06-15 18:52:59 +0200238 pr_debug("%s: irq_stat: 0x%02x irq_mask: 0x%02x\n",
239 hwif->name, irq_stat, irq_mask);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700240
Sergei Shtylyov628df2f2009-06-15 18:52:59 +0200241 return (irq_stat & irq_mask) ? 1 : 0;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700242}
243
244/*
245 * ASUS P55T2P4D with CMD646 chipset revision 0x01 requires the old
246 * event order for DMA transfers.
247 */
248
Bartlomiej Zolnierkiewicz5e37bdc2008-04-26 22:25:24 +0200249static int cmd646_1_dma_end(ide_drive_t *drive)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700250{
Bartlomiej Zolnierkiewicz898ec222009-01-06 17:20:52 +0100251 ide_hwif_t *hwif = drive->hwif;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700252 u8 dma_stat = 0, dma_cmd = 0;
253
Linus Torvalds1da177e2005-04-16 15:20:36 -0700254 /* get DMA status */
Bartlomiej Zolnierkiewiczcab7f8e2008-07-23 19:55:51 +0200255 dma_stat = inb(hwif->dma_base + ATA_DMA_STATUS);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700256 /* read DMA command state */
Bartlomiej Zolnierkiewiczcab7f8e2008-07-23 19:55:51 +0200257 dma_cmd = inb(hwif->dma_base + ATA_DMA_CMD);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700258 /* stop DMA */
Bartlomiej Zolnierkiewiczcab7f8e2008-07-23 19:55:51 +0200259 outb(dma_cmd & ~1, hwif->dma_base + ATA_DMA_CMD);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700260 /* clear the INTR & ERROR bits */
Bartlomiej Zolnierkiewiczcab7f8e2008-07-23 19:55:51 +0200261 outb(dma_stat | 6, hwif->dma_base + ATA_DMA_STATUS);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700262 /* verify good DMA status */
263 return (dma_stat & 7) != 4;
264}
265
Bartlomiej Zolnierkiewicz2ed0ef52009-03-24 23:22:53 +0100266static int init_chipset_cmd64x(struct pci_dev *dev)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700267{
Linus Torvalds1da177e2005-04-16 15:20:36 -0700268 u8 mrdmode = 0;
269
Linus Torvalds1da177e2005-04-16 15:20:36 -0700270 /* Set a good latency timer and cache line size value. */
271 (void) pci_write_config_byte(dev, PCI_LATENCY_TIMER, 64);
272 /* FIXME: pci_set_master() to ensure a good latency timer value */
273
Sergei Shtylyov83a6d4a2007-07-09 23:17:55 +0200274 /*
275 * Enable interrupts, select MEMORY READ LINE for reads.
276 *
277 * NOTE: although not mentioned in the PCI0646U specs,
278 * bits 0-1 are write only and won't be read back as
279 * set or not -- PCI0646U2 specs clarify this point.
Linus Torvalds1da177e2005-04-16 15:20:36 -0700280 */
Sergei Shtylyov83a6d4a2007-07-09 23:17:55 +0200281 (void) pci_read_config_byte (dev, MRDMODE, &mrdmode);
282 mrdmode &= ~0x30;
283 (void) pci_write_config_byte(dev, MRDMODE, (mrdmode | 0x02));
Linus Torvalds1da177e2005-04-16 15:20:36 -0700284
Linus Torvalds1da177e2005-04-16 15:20:36 -0700285 return 0;
286}
287
Bartlomiej Zolnierkiewiczf454cbe2008-08-05 18:17:04 +0200288static u8 cmd64x_cable_detect(ide_hwif_t *hwif)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700289{
Bartlomiej Zolnierkiewicz36501652008-02-01 23:09:31 +0100290 struct pci_dev *dev = to_pci_dev(hwif->dev);
Sergei Shtylyov83a6d4a2007-07-09 23:17:55 +0200291 u8 bmidecsr = 0, mask = hwif->channel ? 0x02 : 0x01;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700292
Sergei Shtylyov83a6d4a2007-07-09 23:17:55 +0200293 switch (dev->device) {
294 case PCI_DEVICE_ID_CMD_648:
295 case PCI_DEVICE_ID_CMD_649:
296 pci_read_config_byte(dev, BMIDECSR, &bmidecsr);
Bartlomiej Zolnierkiewicz49521f92007-07-09 23:17:58 +0200297 return (bmidecsr & mask) ? ATA_CBL_PATA80 : ATA_CBL_PATA40;
Sergei Shtylyov83a6d4a2007-07-09 23:17:55 +0200298 default:
Bartlomiej Zolnierkiewicz49521f92007-07-09 23:17:58 +0200299 return ATA_CBL_PATA40;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700300 }
Linus Torvalds1da177e2005-04-16 15:20:36 -0700301}
302
Bartlomiej Zolnierkiewiczac95bee2008-04-26 22:25:14 +0200303static const struct ide_port_ops cmd64x_port_ops = {
304 .set_pio_mode = cmd64x_set_pio_mode,
305 .set_dma_mode = cmd64x_set_dma_mode,
Sergei Shtylyov30e5ffc2009-06-15 18:52:56 +0200306 .clear_irq = cmd64x_clear_irq,
Sergei Shtylyov628df2f2009-06-15 18:52:59 +0200307 .test_irq = cmd64x_test_irq,
Sergei Shtylyov30e5ffc2009-06-15 18:52:56 +0200308 .cable_detect = cmd64x_cable_detect,
309};
310
311static const struct ide_port_ops cmd648_port_ops = {
312 .set_pio_mode = cmd64x_set_pio_mode,
313 .set_dma_mode = cmd64x_set_dma_mode,
314 .clear_irq = cmd648_clear_irq,
Sergei Shtylyov628df2f2009-06-15 18:52:59 +0200315 .test_irq = cmd648_test_irq,
Bartlomiej Zolnierkiewiczac95bee2008-04-26 22:25:14 +0200316 .cable_detect = cmd64x_cable_detect,
317};
318
Bartlomiej Zolnierkiewiczf37afda2008-04-26 22:25:24 +0200319static const struct ide_dma_ops cmd646_rev1_dma_ops = {
320 .dma_host_set = ide_dma_host_set,
321 .dma_setup = ide_dma_setup,
Bartlomiej Zolnierkiewiczf37afda2008-04-26 22:25:24 +0200322 .dma_start = ide_dma_start,
Bartlomiej Zolnierkiewicz5e37bdc2008-04-26 22:25:24 +0200323 .dma_end = cmd646_1_dma_end,
Bartlomiej Zolnierkiewiczf37afda2008-04-26 22:25:24 +0200324 .dma_test_irq = ide_dma_test_irq,
325 .dma_lost_irq = ide_dma_lost_irq,
Bartlomiej Zolnierkiewicz22117d62009-03-27 12:46:47 +0100326 .dma_timer_expiry = ide_dma_sff_timer_expiry,
Sergei Shtylyov592b5312009-01-06 17:21:02 +0100327 .dma_sff_read_status = ide_dma_sff_read_status,
Bartlomiej Zolnierkiewicz5e37bdc2008-04-26 22:25:24 +0200328};
329
Bartlomiej Zolnierkiewicz85620432007-10-20 00:32:34 +0200330static const struct ide_port_info cmd64x_chipsets[] __devinitdata = {
Bartlomiej Zolnierkiewiczced3ec82008-07-24 22:53:32 +0200331 { /* 0: CMD643 */
332 .name = DRV_NAME,
Linus Torvalds1da177e2005-04-16 15:20:36 -0700333 .init_chipset = init_chipset_cmd64x,
Sergei Shtylyov7accbff2007-05-05 22:03:49 +0200334 .enablebits = {{0x00,0x00,0x00}, {0x51,0x08,0x08}},
Bartlomiej Zolnierkiewiczac95bee2008-04-26 22:25:14 +0200335 .port_ops = &cmd64x_port_ops,
Bartlomiej Zolnierkiewicz8ac2b422008-02-01 23:09:30 +0100336 .host_flags = IDE_HFLAG_CLEAR_SIMPLEX |
Mikulas Patocka9bd74962009-10-21 08:55:28 +0000337 IDE_HFLAG_ABUSE_PREFETCH |
338 IDE_HFLAG_SERIALIZE,
Bartlomiej Zolnierkiewicz4099d142007-07-20 01:11:59 +0200339 .pio_mask = ATA_PIO5,
Bartlomiej Zolnierkiewicz5f8b6c32007-10-19 00:30:07 +0200340 .mwdma_mask = ATA_MWDMA2,
Bartlomiej Zolnierkiewicz18137202007-05-10 00:01:07 +0200341 .udma_mask = 0x00, /* no udma */
Bartlomiej Zolnierkiewiczced3ec82008-07-24 22:53:32 +0200342 },
343 { /* 1: CMD646 */
344 .name = DRV_NAME,
Linus Torvalds1da177e2005-04-16 15:20:36 -0700345 .init_chipset = init_chipset_cmd64x,
Sergei Shtylyov7accbff2007-05-05 22:03:49 +0200346 .enablebits = {{0x51,0x04,0x04}, {0x51,0x08,0x08}},
Sergei Shtylyov30e5ffc2009-06-15 18:52:56 +0200347 .port_ops = &cmd648_port_ops,
Mikulas Patocka9bd74962009-10-21 08:55:28 +0000348 .host_flags = IDE_HFLAG_ABUSE_PREFETCH |
349 IDE_HFLAG_SERIALIZE,
Bartlomiej Zolnierkiewicz4099d142007-07-20 01:11:59 +0200350 .pio_mask = ATA_PIO5,
Bartlomiej Zolnierkiewicz5f8b6c32007-10-19 00:30:07 +0200351 .mwdma_mask = ATA_MWDMA2,
352 .udma_mask = ATA_UDMA2,
Bartlomiej Zolnierkiewiczced3ec82008-07-24 22:53:32 +0200353 },
354 { /* 2: CMD648 */
355 .name = DRV_NAME,
Linus Torvalds1da177e2005-04-16 15:20:36 -0700356 .init_chipset = init_chipset_cmd64x,
Sergei Shtylyov7accbff2007-05-05 22:03:49 +0200357 .enablebits = {{0x51,0x04,0x04}, {0x51,0x08,0x08}},
Sergei Shtylyov30e5ffc2009-06-15 18:52:56 +0200358 .port_ops = &cmd648_port_ops,
Bartlomiej Zolnierkiewicz5e71d9c2008-04-26 17:36:35 +0200359 .host_flags = IDE_HFLAG_ABUSE_PREFETCH,
Bartlomiej Zolnierkiewicz4099d142007-07-20 01:11:59 +0200360 .pio_mask = ATA_PIO5,
Bartlomiej Zolnierkiewicz5f8b6c32007-10-19 00:30:07 +0200361 .mwdma_mask = ATA_MWDMA2,
362 .udma_mask = ATA_UDMA4,
Bartlomiej Zolnierkiewiczced3ec82008-07-24 22:53:32 +0200363 },
364 { /* 3: CMD649 */
365 .name = DRV_NAME,
Linus Torvalds1da177e2005-04-16 15:20:36 -0700366 .init_chipset = init_chipset_cmd64x,
Sergei Shtylyov7accbff2007-05-05 22:03:49 +0200367 .enablebits = {{0x51,0x04,0x04}, {0x51,0x08,0x08}},
Sergei Shtylyov30e5ffc2009-06-15 18:52:56 +0200368 .port_ops = &cmd648_port_ops,
Bartlomiej Zolnierkiewicz5e71d9c2008-04-26 17:36:35 +0200369 .host_flags = IDE_HFLAG_ABUSE_PREFETCH,
Bartlomiej Zolnierkiewicz4099d142007-07-20 01:11:59 +0200370 .pio_mask = ATA_PIO5,
Bartlomiej Zolnierkiewicz5f8b6c32007-10-19 00:30:07 +0200371 .mwdma_mask = ATA_MWDMA2,
372 .udma_mask = ATA_UDMA5,
Linus Torvalds1da177e2005-04-16 15:20:36 -0700373 }
374};
375
376static int __devinit cmd64x_init_one(struct pci_dev *dev, const struct pci_device_id *id)
377{
Bartlomiej Zolnierkiewicz039788e2007-10-20 00:32:34 +0200378 struct ide_port_info d;
Bartlomiej Zolnierkiewiczbfd314a2007-10-19 00:30:09 +0200379 u8 idx = id->driver_data;
Sergei Shtylyov7accbff2007-05-05 22:03:49 +0200380
Bartlomiej Zolnierkiewiczbfd314a2007-10-19 00:30:09 +0200381 d = cmd64x_chipsets[idx];
382
Bartlomiej Zolnierkiewicz5e37bdc2008-04-26 22:25:24 +0200383 if (idx == 1) {
384 /*
385 * UltraDMA only supported on PCI646U and PCI646U2, which
386 * correspond to revisions 0x03, 0x05 and 0x07 respectively.
387 * Actually, although the CMD tech support people won't
388 * tell me the details, the 0x03 revision cannot support
389 * UDMA correctly without hardware modifications, and even
390 * then it only works with Quantum disks due to some
391 * hold time assumptions in the 646U part which are fixed
392 * in the 646U2.
393 *
394 * So we only do UltraDMA on revision 0x05 and 0x07 chipsets.
395 */
396 if (dev->revision < 5) {
397 d.udma_mask = 0x00;
398 /*
399 * The original PCI0646 didn't have the primary
400 * channel enable bit, it appeared starting with
401 * PCI0646U (i.e. revision ID 3).
402 */
403 if (dev->revision < 3) {
404 d.enablebits[0].reg = 0;
Sergei Shtylyov30e5ffc2009-06-15 18:52:56 +0200405 d.port_ops = &cmd64x_port_ops;
Bartlomiej Zolnierkiewicz5e37bdc2008-04-26 22:25:24 +0200406 if (dev->revision == 1)
407 d.dma_ops = &cmd646_rev1_dma_ops;
Bartlomiej Zolnierkiewicz5e37bdc2008-04-26 22:25:24 +0200408 }
409 }
410 }
Bartlomiej Zolnierkiewiczbfd314a2007-10-19 00:30:09 +0200411
Bartlomiej Zolnierkiewicz6cdf6eb2008-07-24 22:53:14 +0200412 return ide_pci_init_one(dev, &d, NULL);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700413}
414
Bartlomiej Zolnierkiewicz9cbcc5e2007-10-16 22:29:56 +0200415static const struct pci_device_id cmd64x_pci_tbl[] = {
416 { PCI_VDEVICE(CMD, PCI_DEVICE_ID_CMD_643), 0 },
417 { PCI_VDEVICE(CMD, PCI_DEVICE_ID_CMD_646), 1 },
418 { PCI_VDEVICE(CMD, PCI_DEVICE_ID_CMD_648), 2 },
419 { PCI_VDEVICE(CMD, PCI_DEVICE_ID_CMD_649), 3 },
Linus Torvalds1da177e2005-04-16 15:20:36 -0700420 { 0, },
421};
422MODULE_DEVICE_TABLE(pci, cmd64x_pci_tbl);
423
Bartlomiej Zolnierkiewicza9ab09e2008-10-13 21:39:41 +0200424static struct pci_driver cmd64x_pci_driver = {
Linus Torvalds1da177e2005-04-16 15:20:36 -0700425 .name = "CMD64x_IDE",
426 .id_table = cmd64x_pci_tbl,
427 .probe = cmd64x_init_one,
Bartlomiej Zolnierkiewicze2b15b42008-07-24 22:53:20 +0200428 .remove = ide_pci_remove,
Bartlomiej Zolnierkiewiczfeb22b72008-10-10 22:39:32 +0200429 .suspend = ide_pci_suspend,
430 .resume = ide_pci_resume,
Linus Torvalds1da177e2005-04-16 15:20:36 -0700431};
432
Bartlomiej Zolnierkiewicz82ab1ee2007-01-27 13:46:56 +0100433static int __init cmd64x_ide_init(void)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700434{
Bartlomiej Zolnierkiewicza9ab09e2008-10-13 21:39:41 +0200435 return ide_pci_register_driver(&cmd64x_pci_driver);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700436}
437
Bartlomiej Zolnierkiewicze2b15b42008-07-24 22:53:20 +0200438static void __exit cmd64x_ide_exit(void)
439{
Bartlomiej Zolnierkiewicza9ab09e2008-10-13 21:39:41 +0200440 pci_unregister_driver(&cmd64x_pci_driver);
Bartlomiej Zolnierkiewicze2b15b42008-07-24 22:53:20 +0200441}
442
Linus Torvalds1da177e2005-04-16 15:20:36 -0700443module_init(cmd64x_ide_init);
Bartlomiej Zolnierkiewicze2b15b42008-07-24 22:53:20 +0200444module_exit(cmd64x_ide_exit);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700445
Bartlomiej Zolnierkiewicz60349ab2010-01-18 07:18:26 +0000446MODULE_AUTHOR("Eddie Dost, David Miller, Andre Hedrick, Bartlomiej Zolnierkiewicz");
Linus Torvalds1da177e2005-04-16 15:20:36 -0700447MODULE_DESCRIPTION("PCI driver module for CMD64x IDE");
448MODULE_LICENSE("GPL");