Tianyi Gou | 2520b6e | 2012-10-29 19:13:53 -0700 | [diff] [blame] | 1 | /* |
Matt Wagantall | f9a4d32 | 2013-01-14 18:01:24 -0800 | [diff] [blame] | 2 | * Copyright (c) 2011-2013, The Linux Foundation. All rights reserved. |
Tianyi Gou | 2520b6e | 2012-10-29 19:13:53 -0700 | [diff] [blame] | 3 | * |
| 4 | * This program is free software; you can redistribute it and/or modify |
| 5 | * it under the terms of the GNU General Public License version 2 and |
| 6 | * only version 2 as published by the Free Software Foundation. |
| 7 | * |
| 8 | * This program is distributed in the hope that it will be useful, |
| 9 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 10 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 11 | * GNU General Public License for more details. |
| 12 | */ |
| 13 | |
| 14 | #include <linux/kernel.h> |
| 15 | #include <linux/module.h> |
| 16 | #include <linux/platform_device.h> |
| 17 | #include <mach/rpm-regulator.h> |
| 18 | #include <mach/msm_bus_board.h> |
| 19 | #include <mach/msm_bus.h> |
| 20 | |
| 21 | #include "acpuclock.h" |
| 22 | #include "acpuclock-krait.h" |
| 23 | |
| 24 | /* Corner type vreg VDD values */ |
| 25 | #define LVL_NONE RPM_VREG_CORNER_NONE |
| 26 | #define LVL_LOW RPM_VREG_CORNER_LOW |
| 27 | #define LVL_NOM RPM_VREG_CORNER_NOMINAL |
| 28 | #define LVL_HIGH RPM_VREG_CORNER_HIGH |
| 29 | |
| 30 | static struct hfpll_data hfpll_data __initdata = { |
| 31 | .mode_offset = 0x00, |
| 32 | .l_offset = 0x08, |
| 33 | .m_offset = 0x0C, |
| 34 | .n_offset = 0x10, |
| 35 | .config_offset = 0x04, |
| 36 | .config_val = 0x7845C665, |
| 37 | .has_droop_ctl = true, |
| 38 | .droop_offset = 0x14, |
| 39 | .droop_val = 0x0108C000, |
| 40 | .low_vdd_l_max = 37, |
| 41 | .nom_vdd_l_max = 74, |
| 42 | .vdd[HFPLL_VDD_NONE] = LVL_NONE, |
| 43 | .vdd[HFPLL_VDD_LOW] = LVL_LOW, |
| 44 | .vdd[HFPLL_VDD_NOM] = LVL_NOM, |
| 45 | .vdd[HFPLL_VDD_HIGH] = LVL_HIGH, |
| 46 | }; |
| 47 | |
| 48 | static struct scalable scalable_pm8917[] __initdata = { |
| 49 | [CPU0] = { |
| 50 | .hfpll_phys_base = 0x00903200, |
| 51 | .aux_clk_sel_phys = 0x02088014, |
| 52 | .aux_clk_sel = 3, |
| 53 | .sec_clk_sel = 2, |
| 54 | .l2cpmr_iaddr = 0x4501, |
| 55 | .vreg[VREG_CORE] = { "krait0", 1300000 }, |
| 56 | .vreg[VREG_MEM] = { "krait0_mem", 1150000 }, |
Tianyi Gou | d86fa82 | 2012-12-20 14:36:30 -0800 | [diff] [blame] | 57 | .vreg[VREG_DIG] = { "krait0_dig", LVL_HIGH}, |
Tianyi Gou | 2520b6e | 2012-10-29 19:13:53 -0700 | [diff] [blame] | 58 | .vreg[VREG_HFPLL_A] = { "krait0_s8", 2050000 }, |
| 59 | .vreg[VREG_HFPLL_B] = { "krait0_l23", 1800000 }, |
| 60 | }, |
| 61 | [CPU1] = { |
| 62 | .hfpll_phys_base = 0x00903300, |
| 63 | .aux_clk_sel_phys = 0x02098014, |
| 64 | .aux_clk_sel = 3, |
| 65 | .sec_clk_sel = 2, |
| 66 | .l2cpmr_iaddr = 0x5501, |
| 67 | .vreg[VREG_CORE] = { "krait1", 1300000 }, |
| 68 | .vreg[VREG_MEM] = { "krait1_mem", 1150000 }, |
Tianyi Gou | d86fa82 | 2012-12-20 14:36:30 -0800 | [diff] [blame] | 69 | .vreg[VREG_DIG] = { "krait1_dig", LVL_HIGH}, |
Tianyi Gou | 2520b6e | 2012-10-29 19:13:53 -0700 | [diff] [blame] | 70 | .vreg[VREG_HFPLL_A] = { "krait1_s8", 2050000 }, |
| 71 | .vreg[VREG_HFPLL_B] = { "krait1_l23", 1800000 }, |
| 72 | }, |
| 73 | [L2] = { |
| 74 | .hfpll_phys_base = 0x00903400, |
| 75 | .aux_clk_sel_phys = 0x02011028, |
| 76 | .aux_clk_sel = 3, |
| 77 | .sec_clk_sel = 2, |
| 78 | .l2cpmr_iaddr = 0x0500, |
| 79 | .vreg[VREG_HFPLL_A] = { "l2_s8", 2050000 }, |
| 80 | .vreg[VREG_HFPLL_B] = { "l2_l23", 1800000 }, |
| 81 | }, |
| 82 | }; |
| 83 | |
| 84 | static struct scalable scalable[] __initdata = { |
| 85 | [CPU0] = { |
| 86 | .hfpll_phys_base = 0x00903200, |
| 87 | .aux_clk_sel_phys = 0x02088014, |
| 88 | .aux_clk_sel = 3, |
| 89 | .sec_clk_sel = 2, |
| 90 | .l2cpmr_iaddr = 0x4501, |
| 91 | .vreg[VREG_CORE] = { "krait0", 1300000 }, |
| 92 | .vreg[VREG_MEM] = { "krait0_mem", 1150000 }, |
Tianyi Gou | d86fa82 | 2012-12-20 14:36:30 -0800 | [diff] [blame] | 93 | .vreg[VREG_DIG] = { "krait0_dig", LVL_HIGH}, |
Tianyi Gou | 2520b6e | 2012-10-29 19:13:53 -0700 | [diff] [blame] | 94 | .vreg[VREG_HFPLL_A] = { "krait0_hfpll", 1800000 }, |
| 95 | }, |
| 96 | [CPU1] = { |
| 97 | .hfpll_phys_base = 0x00903300, |
| 98 | .aux_clk_sel_phys = 0x02098014, |
| 99 | .aux_clk_sel = 3, |
| 100 | .sec_clk_sel = 2, |
| 101 | .l2cpmr_iaddr = 0x5501, |
| 102 | .vreg[VREG_CORE] = { "krait1", 1300000 }, |
| 103 | .vreg[VREG_MEM] = { "krait1_mem", 1150000 }, |
Tianyi Gou | d86fa82 | 2012-12-20 14:36:30 -0800 | [diff] [blame] | 104 | .vreg[VREG_DIG] = { "krait1_dig", LVL_HIGH}, |
Tianyi Gou | 2520b6e | 2012-10-29 19:13:53 -0700 | [diff] [blame] | 105 | .vreg[VREG_HFPLL_A] = { "krait1_hfpll", 1800000 }, |
| 106 | }, |
| 107 | [L2] = { |
| 108 | .hfpll_phys_base = 0x00903400, |
| 109 | .aux_clk_sel_phys = 0x02011028, |
| 110 | .aux_clk_sel = 3, |
| 111 | .sec_clk_sel = 2, |
| 112 | .l2cpmr_iaddr = 0x0500, |
| 113 | .vreg[VREG_HFPLL_A] = { "l2_hfpll", 1800000 }, |
| 114 | }, |
| 115 | }; |
| 116 | |
| 117 | static struct msm_bus_paths bw_level_tbl[] __initdata = { |
| 118 | [0] = BW_MBPS(640), /* At least 80 MHz on bus. */ |
| 119 | [1] = BW_MBPS(1064), /* At least 133 MHz on bus. */ |
| 120 | [2] = BW_MBPS(1600), /* At least 200 MHz on bus. */ |
| 121 | [3] = BW_MBPS(2128), /* At least 266 MHz on bus. */ |
| 122 | [4] = BW_MBPS(3200), /* At least 400 MHz on bus. */ |
| 123 | [5] = BW_MBPS(4800), /* At least 600 MHz on bus. */ |
| 124 | }; |
| 125 | |
| 126 | static struct msm_bus_scale_pdata bus_scale_data __initdata = { |
| 127 | .usecase = bw_level_tbl, |
| 128 | .num_usecases = ARRAY_SIZE(bw_level_tbl), |
| 129 | .active_only = 1, |
| 130 | .name = "acpuclk-8930ab", |
| 131 | }; |
| 132 | |
Tianyi Gou | 2520b6e | 2012-10-29 19:13:53 -0700 | [diff] [blame] | 133 | static struct l2_level l2_freq_tbl[] __initdata = { |
Tianyi Gou | f684b38 | 2013-02-05 18:27:32 -0800 | [diff] [blame] | 134 | [0] = { { 384000, PLL_8, 0, 0x00 }, LVL_LOW, 1050000, 1 }, |
Tianyi Gou | 2520b6e | 2012-10-29 19:13:53 -0700 | [diff] [blame] | 135 | [1] = { { 432000, HFPLL, 2, 0x20 }, LVL_NOM, 1050000, 2 }, |
| 136 | [2] = { { 486000, HFPLL, 2, 0x24 }, LVL_NOM, 1050000, 2 }, |
| 137 | [3] = { { 540000, HFPLL, 2, 0x28 }, LVL_NOM, 1050000, 2 }, |
| 138 | [4] = { { 594000, HFPLL, 1, 0x16 }, LVL_NOM, 1050000, 2 }, |
| 139 | [5] = { { 648000, HFPLL, 1, 0x18 }, LVL_NOM, 1050000, 4 }, |
| 140 | [6] = { { 702000, HFPLL, 1, 0x1A }, LVL_NOM, 1050000, 4 }, |
| 141 | [7] = { { 756000, HFPLL, 1, 0x1C }, LVL_HIGH, 1150000, 4 }, |
| 142 | [8] = { { 810000, HFPLL, 1, 0x1E }, LVL_HIGH, 1150000, 4 }, |
| 143 | [9] = { { 864000, HFPLL, 1, 0x20 }, LVL_HIGH, 1150000, 4 }, |
| 144 | [10] = { { 918000, HFPLL, 1, 0x22 }, LVL_HIGH, 1150000, 5 }, |
| 145 | [11] = { { 972000, HFPLL, 1, 0x24 }, LVL_HIGH, 1150000, 5 }, |
| 146 | [12] = { { 1026000, HFPLL, 1, 0x26 }, LVL_HIGH, 1150000, 5 }, |
| 147 | [13] = { { 1080000, HFPLL, 1, 0x28 }, LVL_HIGH, 1150000, 5 }, |
| 148 | [14] = { { 1134000, HFPLL, 1, 0x2A }, LVL_HIGH, 1150000, 5 }, |
| 149 | [15] = { { 1188000, HFPLL, 1, 0x2C }, LVL_HIGH, 1150000, 5 }, |
| 150 | { } |
| 151 | }; |
| 152 | |
Uma Maheshwari Bhiram | 8368fda | 2013-01-24 19:31:27 -0800 | [diff] [blame] | 153 | static struct acpu_level tbl_PVS0_1700MHz[] __initdata = { |
| 154 | { 1, { 384000, PLL_8, 0, 0x00 }, L2(0), 1000000 }, |
| 155 | { 1, { 486000, HFPLL, 2, 0x24 }, L2(5), 1000000 }, |
Tianyi Gou | 2520b6e | 2012-10-29 19:13:53 -0700 | [diff] [blame] | 156 | { 1, { 594000, HFPLL, 1, 0x16 }, L2(5), 1000000 }, |
Tianyi Gou | 2520b6e | 2012-10-29 19:13:53 -0700 | [diff] [blame] | 157 | { 1, { 702000, HFPLL, 1, 0x1A }, L2(5), 1025000 }, |
Uma Maheshwari Bhiram | 8368fda | 2013-01-24 19:31:27 -0800 | [diff] [blame] | 158 | { 1, { 810000, HFPLL, 1, 0x1E }, L2(10), 1050000 }, |
| 159 | { 1, { 918000, HFPLL, 1, 0x22 }, L2(10), 1075000 }, |
| 160 | { 1, { 1026000, HFPLL, 1, 0x26 }, L2(10), 1100000 }, |
| 161 | { 1, { 1134000, HFPLL, 1, 0x2A }, L2(15), 1125000 }, |
| 162 | { 1, { 1242000, HFPLL, 1, 0x2E }, L2(15), 1150000 }, |
| 163 | { 1, { 1350000, HFPLL, 1, 0x32 }, L2(15), 1175000 }, |
| 164 | { 1, { 1458000, HFPLL, 1, 0x36 }, L2(15), 1200000 }, |
| 165 | { 1, { 1566000, HFPLL, 1, 0x3A }, L2(15), 1225000 }, |
| 166 | { 1, { 1674000, HFPLL, 1, 0x3E }, L2(15), 1250000 }, |
| 167 | { 1, { 1728000, HFPLL, 1, 0x40 }, L2(15), 1275000 }, |
Tianyi Gou | 2520b6e | 2012-10-29 19:13:53 -0700 | [diff] [blame] | 168 | { 0, { 0 } } |
| 169 | }; |
| 170 | |
Uma Maheshwari Bhiram | 8368fda | 2013-01-24 19:31:27 -0800 | [diff] [blame] | 171 | static struct acpu_level tbl_PVS1_1700MHz[] __initdata = { |
| 172 | { 1, { 384000, PLL_8, 0, 0x00 }, L2(0), 975000 }, |
Tianyi Gou | 2520b6e | 2012-10-29 19:13:53 -0700 | [diff] [blame] | 173 | { 1, { 486000, HFPLL, 2, 0x24 }, L2(5), 975000 }, |
Tianyi Gou | 2520b6e | 2012-10-29 19:13:53 -0700 | [diff] [blame] | 174 | { 1, { 594000, HFPLL, 1, 0x16 }, L2(5), 1000000 }, |
Uma Maheshwari Bhiram | 8368fda | 2013-01-24 19:31:27 -0800 | [diff] [blame] | 175 | { 1, { 702000, HFPLL, 1, 0x1A }, L2(5), 1000000 }, |
| 176 | { 1, { 810000, HFPLL, 1, 0x1E }, L2(10), 1025000 }, |
| 177 | { 1, { 918000, HFPLL, 1, 0x22 }, L2(10), 1050000 }, |
| 178 | { 1, { 1026000, HFPLL, 1, 0x26 }, L2(10), 1075000 }, |
| 179 | { 1, { 1134000, HFPLL, 1, 0x2A }, L2(15), 1100000 }, |
| 180 | { 1, { 1242000, HFPLL, 1, 0x2E }, L2(15), 1125000 }, |
| 181 | { 1, { 1350000, HFPLL, 1, 0x32 }, L2(15), 1150000 }, |
| 182 | { 1, { 1458000, HFPLL, 1, 0x36 }, L2(15), 1175000 }, |
| 183 | { 1, { 1566000, HFPLL, 1, 0x3A }, L2(15), 1200000 }, |
| 184 | { 1, { 1674000, HFPLL, 1, 0x3E }, L2(15), 1225000 }, |
| 185 | { 1, { 1728000, HFPLL, 1, 0x40 }, L2(15), 1250000 }, |
Tianyi Gou | 2520b6e | 2012-10-29 19:13:53 -0700 | [diff] [blame] | 186 | { 0, { 0 } } |
| 187 | }; |
| 188 | |
Uma Maheshwari Bhiram | 8368fda | 2013-01-24 19:31:27 -0800 | [diff] [blame] | 189 | static struct acpu_level tbl_PVS2_1700MHz[] __initdata = { |
Tianyi Gou | 2520b6e | 2012-10-29 19:13:53 -0700 | [diff] [blame] | 190 | { 1, { 384000, PLL_8, 0, 0x00 }, L2(0), 950000 }, |
Uma Maheshwari Bhiram | 8368fda | 2013-01-24 19:31:27 -0800 | [diff] [blame] | 191 | { 1, { 486000, HFPLL, 2, 0x24 }, L2(5), 950000 }, |
| 192 | { 1, { 594000, HFPLL, 1, 0x16 }, L2(5), 950000 }, |
| 193 | { 1, { 702000, HFPLL, 1, 0x1A }, L2(5), 975000 }, |
| 194 | { 1, { 810000, HFPLL, 1, 0x1E }, L2(10), 1000000 }, |
| 195 | { 1, { 918000, HFPLL, 1, 0x22 }, L2(10), 1025000 }, |
| 196 | { 1, { 1026000, HFPLL, 1, 0x26 }, L2(10), 1050000 }, |
| 197 | { 1, { 1134000, HFPLL, 1, 0x2A }, L2(15), 1075000 }, |
| 198 | { 1, { 1242000, HFPLL, 1, 0x2E }, L2(15), 1100000 }, |
| 199 | { 1, { 1350000, HFPLL, 1, 0x32 }, L2(15), 1125000 }, |
| 200 | { 1, { 1458000, HFPLL, 1, 0x36 }, L2(15), 1150000 }, |
| 201 | { 1, { 1566000, HFPLL, 1, 0x3A }, L2(15), 1175000 }, |
| 202 | { 1, { 1674000, HFPLL, 1, 0x3E }, L2(15), 1200000 }, |
| 203 | { 1, { 1728000, HFPLL, 1, 0x40 }, L2(15), 1225000 }, |
Tianyi Gou | 2520b6e | 2012-10-29 19:13:53 -0700 | [diff] [blame] | 204 | { 0, { 0 } } |
| 205 | }; |
| 206 | |
Uma Maheshwari Bhiram | 8368fda | 2013-01-24 19:31:27 -0800 | [diff] [blame] | 207 | static struct acpu_level tbl_PVS3_1700MHz[] __initdata = { |
| 208 | { 1, { 384000, PLL_8, 0, 0x00 }, L2(0), 925000 }, |
| 209 | { 1, { 486000, HFPLL, 2, 0x24 }, L2(5), 925000 }, |
| 210 | { 1, { 594000, HFPLL, 1, 0x16 }, L2(5), 925000 }, |
| 211 | { 1, { 702000, HFPLL, 1, 0x1A }, L2(5), 950000 }, |
| 212 | { 1, { 810000, HFPLL, 1, 0x1E }, L2(10), 975000 }, |
| 213 | { 1, { 918000, HFPLL, 1, 0x22 }, L2(10), 1000000 }, |
| 214 | { 1, { 1026000, HFPLL, 1, 0x26 }, L2(10), 1025000 }, |
| 215 | { 1, { 1134000, HFPLL, 1, 0x2A }, L2(15), 1050000 }, |
| 216 | { 1, { 1242000, HFPLL, 1, 0x2E }, L2(15), 1075000 }, |
| 217 | { 1, { 1350000, HFPLL, 1, 0x32 }, L2(15), 1100000 }, |
| 218 | { 1, { 1458000, HFPLL, 1, 0x36 }, L2(15), 1125000 }, |
| 219 | { 1, { 1566000, HFPLL, 1, 0x3A }, L2(15), 1150000 }, |
| 220 | { 1, { 1674000, HFPLL, 1, 0x3E }, L2(15), 1175000 }, |
| 221 | { 1, { 1728000, HFPLL, 1, 0x40 }, L2(15), 1200000 }, |
| 222 | { 0, { 0 } } |
| 223 | }; |
| 224 | |
| 225 | static struct acpu_level tbl_PVS4_1700MHz[] __initdata = { |
| 226 | { 1, { 384000, PLL_8, 0, 0x00 }, L2(0), 925000 }, |
| 227 | { 1, { 486000, HFPLL, 2, 0x24 }, L2(5), 925000 }, |
| 228 | { 1, { 594000, HFPLL, 1, 0x16 }, L2(5), 925000 }, |
| 229 | { 1, { 702000, HFPLL, 1, 0x1A }, L2(5), 925000 }, |
| 230 | { 1, { 810000, HFPLL, 1, 0x1E }, L2(10), 950000 }, |
| 231 | { 1, { 918000, HFPLL, 1, 0x22 }, L2(10), 975000 }, |
| 232 | { 1, { 1026000, HFPLL, 1, 0x26 }, L2(10), 1000000 }, |
| 233 | { 1, { 1134000, HFPLL, 1, 0x2A }, L2(15), 1025000 }, |
| 234 | { 1, { 1242000, HFPLL, 1, 0x2E }, L2(15), 1050000 }, |
| 235 | { 1, { 1350000, HFPLL, 1, 0x32 }, L2(15), 1075000 }, |
| 236 | { 1, { 1458000, HFPLL, 1, 0x36 }, L2(15), 1100000 }, |
| 237 | { 1, { 1566000, HFPLL, 1, 0x3A }, L2(15), 1125000 }, |
| 238 | { 1, { 1674000, HFPLL, 1, 0x3E }, L2(15), 1150000 }, |
| 239 | { 1, { 1728000, HFPLL, 1, 0x40 }, L2(15), 1175000 }, |
| 240 | { 0, { 0 } } |
| 241 | }; |
| 242 | |
| 243 | static struct acpu_level tbl_PVS5_1700MHz[] __initdata = { |
| 244 | { 1, { 384000, PLL_8, 0, 0x00 }, L2(0), 900000 }, |
| 245 | { 1, { 486000, HFPLL, 2, 0x24 }, L2(5), 900000 }, |
| 246 | { 1, { 594000, HFPLL, 1, 0x16 }, L2(5), 900000 }, |
| 247 | { 1, { 702000, HFPLL, 1, 0x1A }, L2(5), 900000 }, |
| 248 | { 1, { 810000, HFPLL, 1, 0x1E }, L2(10), 925000 }, |
| 249 | { 1, { 918000, HFPLL, 1, 0x22 }, L2(10), 950000 }, |
| 250 | { 1, { 1026000, HFPLL, 1, 0x26 }, L2(10), 975000 }, |
| 251 | { 1, { 1134000, HFPLL, 1, 0x2A }, L2(15), 1000000 }, |
| 252 | { 1, { 1242000, HFPLL, 1, 0x2E }, L2(15), 1025000 }, |
| 253 | { 1, { 1350000, HFPLL, 1, 0x32 }, L2(15), 1050000 }, |
| 254 | { 1, { 1458000, HFPLL, 1, 0x36 }, L2(15), 1075000 }, |
| 255 | { 1, { 1566000, HFPLL, 1, 0x3A }, L2(15), 1100000 }, |
| 256 | { 1, { 1674000, HFPLL, 1, 0x3E }, L2(15), 1125000 }, |
| 257 | { 1, { 1728000, HFPLL, 1, 0x40 }, L2(15), 1150000 }, |
| 258 | { 0, { 0 } } |
| 259 | }; |
| 260 | |
| 261 | static struct acpu_level tbl_PVS6_1700MHz[] __initdata = { |
| 262 | { 1, { 384000, PLL_8, 0, 0x00 }, L2(0), 875000 }, |
| 263 | { 1, { 486000, HFPLL, 2, 0x24 }, L2(5), 875000 }, |
| 264 | { 1, { 594000, HFPLL, 1, 0x16 }, L2(5), 875000 }, |
| 265 | { 1, { 702000, HFPLL, 1, 0x1A }, L2(5), 875000 }, |
| 266 | { 1, { 810000, HFPLL, 1, 0x1E }, L2(10), 900000 }, |
| 267 | { 1, { 918000, HFPLL, 1, 0x22 }, L2(10), 925000 }, |
| 268 | { 1, { 1026000, HFPLL, 1, 0x26 }, L2(10), 950000 }, |
| 269 | { 1, { 1134000, HFPLL, 1, 0x2A }, L2(15), 975000 }, |
| 270 | { 1, { 1242000, HFPLL, 1, 0x2E }, L2(15), 1000000 }, |
| 271 | { 1, { 1350000, HFPLL, 1, 0x32 }, L2(15), 1025000 }, |
| 272 | { 1, { 1458000, HFPLL, 1, 0x36 }, L2(15), 1050000 }, |
| 273 | { 1, { 1566000, HFPLL, 1, 0x3A }, L2(15), 1075000 }, |
| 274 | { 1, { 1674000, HFPLL, 1, 0x3E }, L2(15), 1100000 }, |
| 275 | { 1, { 1728000, HFPLL, 1, 0x40 }, L2(15), 1125000 }, |
| 276 | { 0, { 0 } } |
| 277 | }; |
| 278 | |
Tianyi Gou | 2520b6e | 2012-10-29 19:13:53 -0700 | [diff] [blame] | 279 | static struct pvs_table pvs_tables[NUM_SPEED_BINS][NUM_PVS] __initdata = { |
Uma Maheshwari Bhiram | 8368fda | 2013-01-24 19:31:27 -0800 | [diff] [blame] | 280 | [0][0] = { tbl_PVS0_1700MHz, sizeof(tbl_PVS0_1700MHz), 0 }, |
| 281 | [0][1] = { tbl_PVS1_1700MHz, sizeof(tbl_PVS1_1700MHz), 25000 }, |
| 282 | [0][2] = { tbl_PVS2_1700MHz, sizeof(tbl_PVS2_1700MHz), 25000 }, |
| 283 | [0][3] = { tbl_PVS3_1700MHz, sizeof(tbl_PVS3_1700MHz), 25000 }, |
| 284 | [0][4] = { tbl_PVS4_1700MHz, sizeof(tbl_PVS4_1700MHz), 25000 }, |
| 285 | [0][5] = { tbl_PVS5_1700MHz, sizeof(tbl_PVS5_1700MHz), 25000 }, |
| 286 | [0][6] = { tbl_PVS6_1700MHz, sizeof(tbl_PVS6_1700MHz), 25000 }, |
Tianyi Gou | 2520b6e | 2012-10-29 19:13:53 -0700 | [diff] [blame] | 287 | }; |
| 288 | |
| 289 | static struct acpuclk_krait_params acpuclk_8930ab_params __initdata = { |
| 290 | .scalable = scalable, |
| 291 | .scalable_size = sizeof(scalable), |
| 292 | .hfpll_data = &hfpll_data, |
| 293 | .pvs_tables = pvs_tables, |
| 294 | .l2_freq_tbl = l2_freq_tbl, |
| 295 | .l2_freq_tbl_size = sizeof(l2_freq_tbl), |
| 296 | .bus_scale = &bus_scale_data, |
| 297 | .pte_efuse_phys = 0x007000C0, |
Matt Wagantall | f9a4d32 | 2013-01-14 18:01:24 -0800 | [diff] [blame] | 298 | .get_bin_info = get_krait_bin_format_a, |
Tianyi Gou | 2520b6e | 2012-10-29 19:13:53 -0700 | [diff] [blame] | 299 | .stby_khz = 384000, |
| 300 | }; |
| 301 | |
| 302 | static int __init acpuclk_8930ab_probe(struct platform_device *pdev) |
| 303 | { |
| 304 | struct acpuclk_platform_data *pdata = pdev->dev.platform_data; |
| 305 | if (pdata && pdata->uses_pm8917) |
| 306 | acpuclk_8930ab_params.scalable = scalable_pm8917; |
| 307 | |
| 308 | return acpuclk_krait_init(&pdev->dev, &acpuclk_8930ab_params); |
| 309 | } |
| 310 | |
| 311 | static struct platform_driver acpuclk_8930ab_driver = { |
| 312 | .driver = { |
| 313 | .name = "acpuclk-8930ab", |
| 314 | .owner = THIS_MODULE, |
| 315 | }, |
| 316 | }; |
| 317 | |
| 318 | static int __init acpuclk_8930ab_init(void) |
| 319 | { |
| 320 | return platform_driver_probe(&acpuclk_8930ab_driver, |
| 321 | acpuclk_8930ab_probe); |
| 322 | } |
| 323 | device_initcall(acpuclk_8930ab_init); |