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gerrit-public.fairphone.software / kernel / msm / 7541ef78c3b83e906b580f005207000545cf770a / . / arch / powerpc / boot / dts / p1020rdb.dts
blob: 49848c545d86d4a35fda99c21c5fd75768754a10 [file] [log] [blame]
Poonam Aggrwal52dffd72009-09-25 09:50:28 +0530[diff] [blame]1/*
2 * P1020 RDB Device Tree Source
3 *
4 * Copyright 2009 Freescale Semiconductor Inc.
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License as published by the
8 * Free Software Foundation; either version 2 of the License, or (at your
9 * option) any later version.
10 */
11
12/dts-v1/;
13/ {
14 model = "fsl,P1020";
15 compatible = "fsl,P1020RDB";
16 #address-cells = <2>;
17 #size-cells = <2>;
18
19 aliases {
20 serial0 = &serial0;
21 serial1 = &serial1;
Anton Vorontsov7541ef72010-04-15 22:36:31 +0400[diff] [blame^]22 ethernet0 = &enet0;
23 ethernet1 = &enet1;
24 ethernet2 = &enet2;
Poonam Aggrwal52dffd72009-09-25 09:50:28 +0530[diff] [blame]25 pci0 = &pci0;
26 pci1 = &pci1;
27 };
28
29 cpus {
30 #address-cells = <1>;
31 #size-cells = <0>;
32
33 PowerPC,P1020@0 {
34 device_type = "cpu";
35 reg = <0x0>;
36 next-level-cache = <&L2>;
37 };
38
39 PowerPC,P1020@1 {
40 device_type = "cpu";
41 reg = <0x1>;
42 next-level-cache = <&L2>;
43 };
44 };
45
46 memory {
47 device_type = "memory";
48 };
49
50 localbus@ffe05000 {
51 #address-cells = <2>;
52 #size-cells = <1>;
53 compatible = "fsl,p1020-elbc", "fsl,elbc", "simple-bus";
54 reg = <0 0xffe05000 0 0x1000>;
55 interrupts = <19 2>;
56 interrupt-parent = <&mpic>;
57
58 /* NOR, NAND Flashes and Vitesse 5 port L2 switch */
59 ranges = <0x0 0x0 0x0 0xef000000 0x01000000
60 0x1 0x0 0x0 0xffa00000 0x00040000
61 0x2 0x0 0x0 0xffb00000 0x00020000>;
62
63 nor@0,0 {
64 #address-cells = <1>;
65 #size-cells = <1>;
66 compatible = "cfi-flash";
67 reg = <0x0 0x0 0x1000000>;
68 bank-width = <2>;
69 device-width = <1>;
70
71 partition@0 {
72 /* This location must not be altered */
73 /* 256KB for Vitesse 7385 Switch firmware */
74 reg = <0x0 0x00040000>;
75 label = "NOR (RO) Vitesse-7385 Firmware";
76 read-only;
77 };
78
79 partition@40000 {
80 /* 256KB for DTB Image */
81 reg = <0x00040000 0x00040000>;
82 label = "NOR (RO) DTB Image";
83 read-only;
84 };
85
86 partition@80000 {
87 /* 3.5 MB for Linux Kernel Image */
88 reg = <0x00080000 0x00380000>;
89 label = "NOR (RO) Linux Kernel Image";
90 read-only;
91 };
92
93 partition@400000 {
94 /* 11MB for JFFS2 based Root file System */
95 reg = <0x00400000 0x00b00000>;
96 label = "NOR (RW) JFFS2 Root File System";
97 };
98
99 partition@f00000 {
100 /* This location must not be altered */
101 /* 512KB for u-boot Bootloader Image */
102 /* 512KB for u-boot Environment Variables */
103 reg = <0x00f00000 0x00100000>;
104 label = "NOR (RO) U-Boot Image";
105 read-only;
106 };
107 };
108
109 nand@1,0 {
110 #address-cells = <1>;
111 #size-cells = <1>;
112 compatible = "fsl,p1020-fcm-nand",
113 "fsl,elbc-fcm-nand";
114 reg = <0x1 0x0 0x40000>;
115
116 partition@0 {
117 /* This location must not be altered */
118 /* 1MB for u-boot Bootloader Image */
119 reg = <0x0 0x00100000>;
120 label = "NAND (RO) U-Boot Image";
121 read-only;
122 };
123
124 partition@100000 {
125 /* 1MB for DTB Image */
126 reg = <0x00100000 0x00100000>;
127 label = "NAND (RO) DTB Image";
128 read-only;
129 };
130
131 partition@200000 {
132 /* 4MB for Linux Kernel Image */
133 reg = <0x00200000 0x00400000>;
134 label = "NAND (RO) Linux Kernel Image";
135 read-only;
136 };
137
138 partition@600000 {
139 /* 4MB for Compressed Root file System Image */
140 reg = <0x00600000 0x00400000>;
141 label = "NAND (RO) Compressed RFS Image";
142 read-only;
143 };
144
145 partition@a00000 {
146 /* 7MB for JFFS2 based Root file System */
147 reg = <0x00a00000 0x00700000>;
148 label = "NAND (RW) JFFS2 Root File System";
149 };
150
151 partition@1100000 {
152 /* 15MB for JFFS2 based Root file System */
153 reg = <0x01100000 0x00f00000>;
154 label = "NAND (RW) Writable User area";
155 };
156 };
157
158 L2switch@2,0 {
159 #address-cells = <1>;
160 #size-cells = <1>;
161 compatible = "vitesse-7385";
162 reg = <0x2 0x0 0x20000>;
163 };
164
165 };
166
167 soc@ffe00000 {
168 #address-cells = <1>;
169 #size-cells = <1>;
170 device_type = "soc";
171 compatible = "fsl,p1020-immr", "simple-bus";
172 ranges = <0x0 0x0 0xffe00000 0x100000>;
173 bus-frequency = <0>; // Filled out by uboot.
174
175 ecm-law@0 {
176 compatible = "fsl,ecm-law";
177 reg = <0x0 0x1000>;
178 fsl,num-laws = <12>;
179 };
180
181 ecm@1000 {
182 compatible = "fsl,p1020-ecm", "fsl,ecm";
183 reg = <0x1000 0x1000>;
184 interrupts = <16 2>;
185 interrupt-parent = <&mpic>;
186 };
187
188 memory-controller@2000 {
189 compatible = "fsl,p1020-memory-controller";
190 reg = <0x2000 0x1000>;
191 interrupt-parent = <&mpic>;
192 interrupts = <16 2>;
193 };
194
195 i2c@3000 {
196 #address-cells = <1>;
197 #size-cells = <0>;
198 cell-index = <0>;
199 compatible = "fsl-i2c";
200 reg = <0x3000 0x100>;
201 interrupts = <43 2>;
202 interrupt-parent = <&mpic>;
203 dfsrr;
204 rtc@68 {
205 compatible = "dallas,ds1339";
206 reg = <0x68>;
207 };
208 };
209
210 i2c@3100 {
211 #address-cells = <1>;
212 #size-cells = <0>;
213 cell-index = <1>;
214 compatible = "fsl-i2c";
215 reg = <0x3100 0x100>;
216 interrupts = <43 2>;
217 interrupt-parent = <&mpic>;
218 dfsrr;
219 };
220
221 serial0: serial@4500 {
222 cell-index = <0>;
223 device_type = "serial";
224 compatible = "ns16550";
225 reg = <0x4500 0x100>;
226 clock-frequency = <0>;
227 interrupts = <42 2>;
228 interrupt-parent = <&mpic>;
229 };
230
231 serial1: serial@4600 {
232 cell-index = <1>;
233 device_type = "serial";
234 compatible = "ns16550";
235 reg = <0x4600 0x100>;
236 clock-frequency = <0>;
237 interrupts = <42 2>;
238 interrupt-parent = <&mpic>;
239 };
240
241 spi@7000 {
242 cell-index = <0>;
243 #address-cells = <1>;
244 #size-cells = <0>;
245 compatible = "fsl,espi";
246 reg = <0x7000 0x1000>;
247 interrupts = <59 0x2>;
248 interrupt-parent = <&mpic>;
249 mode = "cpu";
250
251 fsl_m25p80@0 {
252 #address-cells = <1>;
253 #size-cells = <1>;
254 compatible = "fsl,espi-flash";
255 reg = <0>;
256 linux,modalias = "fsl_m25p80";
257 modal = "s25sl128b";
258 spi-max-frequency = <50000000>;
259 mode = <0>;
260
261 partition@0 {
262 /* 512KB for u-boot Bootloader Image */
263 reg = <0x0 0x00080000>;
264 label = "SPI (RO) U-Boot Image";
265 read-only;
266 };
267
268 partition@80000 {
269 /* 512KB for DTB Image */
270 reg = <0x00080000 0x00080000>;
271 label = "SPI (RO) DTB Image";
272 read-only;
273 };
274
275 partition@100000 {
276 /* 4MB for Linux Kernel Image */
277 reg = <0x00100000 0x00400000>;
278 label = "SPI (RO) Linux Kernel Image";
279 read-only;
280 };
281
282 partition@500000 {
283 /* 4MB for Compressed RFS Image */
284 reg = <0x00500000 0x00400000>;
285 label = "SPI (RO) Compressed RFS Image";
286 read-only;
287 };
288
289 partition@900000 {
290 /* 7MB for JFFS2 based RFS */
291 reg = <0x00900000 0x00700000>;
292 label = "SPI (RW) JFFS2 RFS";
293 };
294 };
295 };
296
297 gpio: gpio-controller@f000 {
298 #gpio-cells = <2>;
299 compatible = "fsl,mpc8572-gpio";
300 reg = <0xf000 0x100>;
301 interrupts = <47 0x2>;
302 interrupt-parent = <&mpic>;
303 gpio-controller;
304 };
305
306 L2: l2-cache-controller@20000 {
307 compatible = "fsl,p1020-l2-cache-controller";
308 reg = <0x20000 0x1000>;
309 cache-line-size = <32>; // 32 bytes
310 cache-size = <0x40000>; // L2,256K
311 interrupt-parent = <&mpic>;
312 interrupts = <16 2>;
313 };
314
315 dma@21300 {
316 #address-cells = <1>;
317 #size-cells = <1>;
318 compatible = "fsl,eloplus-dma";
319 reg = <0x21300 0x4>;
320 ranges = <0x0 0x21100 0x200>;
321 cell-index = <0>;
322 dma-channel@0 {
323 compatible = "fsl,eloplus-dma-channel";
324 reg = <0x0 0x80>;
325 cell-index = <0>;
326 interrupt-parent = <&mpic>;
327 interrupts = <20 2>;
328 };
329 dma-channel@80 {
330 compatible = "fsl,eloplus-dma-channel";
331 reg = <0x80 0x80>;
332 cell-index = <1>;
333 interrupt-parent = <&mpic>;
334 interrupts = <21 2>;
335 };
336 dma-channel@100 {
337 compatible = "fsl,eloplus-dma-channel";
338 reg = <0x100 0x80>;
339 cell-index = <2>;
340 interrupt-parent = <&mpic>;
341 interrupts = <22 2>;
342 };
343 dma-channel@180 {
344 compatible = "fsl,eloplus-dma-channel";
345 reg = <0x180 0x80>;
346 cell-index = <3>;
347 interrupt-parent = <&mpic>;
348 interrupts = <23 2>;
349 };
350 };
351
Anton Vorontsov7541ef72010-04-15 22:36:31 +0400[diff] [blame^]352 mdio@24000 {
353 #address-cells = <1>;
354 #size-cells = <0>;
355 compatible = "fsl,etsec2-mdio";
356 reg = <0x24000 0x1000 0xb0030 0x4>;
357
358 phy0: ethernet-phy@0 {
359 interrupt-parent = <&mpic>;
360 interrupts = <3 1>;
361 reg = <0x0>;
362 };
363
364 phy1: ethernet-phy@1 {
365 interrupt-parent = <&mpic>;
366 interrupts = <2 1>;
367 reg = <0x1>;
368 };
369 };
370
371 mdio@25000 {
372 #address-cells = <1>;
373 #size-cells = <0>;
374 compatible = "fsl,etsec2-tbi";
375 reg = <0x25000 0x1000 0xb1030 0x4>;
376
377 tbi0: tbi-phy@11 {
378 reg = <0x11>;
379 device_type = "tbi-phy";
380 };
381 };
382
383 enet0: ethernet@b0000 {
384 #address-cells = <1>;
385 #size-cells = <1>;
386 device_type = "network";
387 model = "eTSEC";
388 compatible = "fsl,etsec2";
389 fsl,num_rx_queues = <0x8>;
390 fsl,num_tx_queues = <0x8>;
391 local-mac-address = [ 00 00 00 00 00 00 ];
392 interrupt-parent = <&mpic>;
393 fixed-link = <1 1 1000 0 0>;
394 phy-connection-type = "rgmii-id";
395
396 queue-group@0 {
397 #address-cells = <1>;
398 #size-cells = <1>;
399 reg = <0xb0000 0x1000>;
400 interrupts = <29 2 30 2 34 2>;
401 };
402
403 queue-group@1 {
404 #address-cells = <1>;
405 #size-cells = <1>;
406 reg = <0xb4000 0x1000>;
407 interrupts = <17 2 18 2 24 2>;
408 };
409 };
410
411 enet1: ethernet@b1000 {
412 #address-cells = <1>;
413 #size-cells = <1>;
414 device_type = "network";
415 model = "eTSEC";
416 compatible = "fsl,etsec2";
417 fsl,num_rx_queues = <0x8>;
418 fsl,num_tx_queues = <0x8>;
419 local-mac-address = [ 00 00 00 00 00 00 ];
420 interrupt-parent = <&mpic>;
421 phy-handle = <&phy0>;
422 tbi-handle = <&tbi0>;
423 phy-connection-type = "sgmii";
424
425 queue-group@0 {
426 #address-cells = <1>;
427 #size-cells = <1>;
428 reg = <0xb1000 0x1000>;
429 interrupts = <35 2 36 2 40 2>;
430 };
431
432 queue-group@1 {
433 #address-cells = <1>;
434 #size-cells = <1>;
435 reg = <0xb5000 0x1000>;
436 interrupts = <51 2 52 2 67 2>;
437 };
438 };
439
440 enet2: ethernet@b2000 {
441 #address-cells = <1>;
442 #size-cells = <1>;
443 device_type = "network";
444 model = "eTSEC";
445 compatible = "fsl,etsec2";
446 fsl,num_rx_queues = <0x8>;
447 fsl,num_tx_queues = <0x8>;
448 local-mac-address = [ 00 00 00 00 00 00 ];
449 interrupt-parent = <&mpic>;
450 phy-handle = <&phy1>;
451 phy-connection-type = "rgmii-id";
452
453 queue-group@0 {
454 #address-cells = <1>;
455 #size-cells = <1>;
456 reg = <0xb2000 0x1000>;
457 interrupts = <31 2 32 2 33 2>;
458 };
459
460 queue-group@1 {
461 #address-cells = <1>;
462 #size-cells = <1>;
463 reg = <0xb6000 0x1000>;
464 interrupts = <25 2 26 2 27 2>;
465 };
466 };
467
Poonam Aggrwal52dffd72009-09-25 09:50:28 +0530[diff] [blame]468 usb@22000 {
469 #address-cells = <1>;
470 #size-cells = <0>;
471 compatible = "fsl-usb2-dr";
472 reg = <0x22000 0x1000>;
473 interrupt-parent = <&mpic>;
474 interrupts = <28 0x2>;
475 phy_type = "ulpi";
476 };
477
478 usb@23000 {
479 #address-cells = <1>;
480 #size-cells = <0>;
481 compatible = "fsl-usb2-dr";
482 reg = <0x23000 0x1000>;
483 interrupt-parent = <&mpic>;
484 interrupts = <46 0x2>;
485 phy_type = "ulpi";
486 };
487
488 sdhci@2e000 {
489 compatible = "fsl,p1020-esdhc", "fsl,esdhc";
490 reg = <0x2e000 0x1000>;
491 interrupts = <72 0x2>;
492 interrupt-parent = <&mpic>;
493 /* Filled in by U-Boot */
494 clock-frequency = <0>;
495 };
496
497 crypto@30000 {
498 compatible = "fsl,sec3.1", "fsl,sec3.0", "fsl,sec2.4",
499 "fsl,sec2.2", "fsl,sec2.1", "fsl,sec2.0";
500 reg = <0x30000 0x10000>;
501 interrupts = <45 2 58 2>;
502 interrupt-parent = <&mpic>;
503 fsl,num-channels = <4>;
504 fsl,channel-fifo-len = <24>;
505 fsl,exec-units-mask = <0xbfe>;
506 fsl,descriptor-types-mask = <0x3ab0ebf>;
507 };
508
509 mpic: pic@40000 {
510 interrupt-controller;
511 #address-cells = <0>;
512 #interrupt-cells = <2>;
513 reg = <0x40000 0x40000>;
514 compatible = "chrp,open-pic";
515 device_type = "open-pic";
516 };
517
518 msi@41600 {
519 compatible = "fsl,p1020-msi", "fsl,mpic-msi";
520 reg = <0x41600 0x80>;
521 msi-available-ranges = <0 0x100>;
522 interrupts = <
523 0xe0 0
524 0xe1 0
525 0xe2 0
526 0xe3 0
527 0xe4 0
528 0xe5 0
529 0xe6 0
530 0xe7 0>;
531 interrupt-parent = <&mpic>;
532 };
533
534 global-utilities@e0000 { //global utilities block
535 compatible = "fsl,p1020-guts";
536 reg = <0xe0000 0x1000>;
537 fsl,has-rstcr;
538 };
539 };
540
541 pci0: pcie@ffe09000 {
542 compatible = "fsl,mpc8548-pcie";
543 device_type = "pci";
544 #interrupt-cells = <1>;
545 #size-cells = <2>;
546 #address-cells = <3>;
547 reg = <0 0xffe09000 0 0x1000>;
548 bus-range = <0 255>;
549 ranges = <0x2000000 0x0 0xa0000000 0 0xa0000000 0x0 0x20000000
550 0x1000000 0x0 0x00000000 0 0xffc30000 0x0 0x10000>;
551 clock-frequency = <33333333>;
552 interrupt-parent = <&mpic>;
553 interrupts = <16 2>;
554 pcie@0 {
555 reg = <0x0 0x0 0x0 0x0 0x0>;
556 #size-cells = <2>;
557 #address-cells = <3>;
558 device_type = "pci";
559 ranges = <0x2000000 0x0 0xa0000000
560 0x2000000 0x0 0xa0000000
561 0x0 0x20000000
562
563 0x1000000 0x0 0x0
564 0x1000000 0x0 0x0
565 0x0 0x100000>;
566 };
567 };
568
569 pci1: pcie@ffe0a000 {
570 compatible = "fsl,mpc8548-pcie";
571 device_type = "pci";
572 #interrupt-cells = <1>;
573 #size-cells = <2>;
574 #address-cells = <3>;
575 reg = <0 0xffe0a000 0 0x1000>;
576 bus-range = <0 255>;
577 ranges = <0x2000000 0x0 0xc0000000 0 0xc0000000 0x0 0x20000000
578 0x1000000 0x0 0x00000000 0 0xffc20000 0x0 0x10000>;
579 clock-frequency = <33333333>;
580 interrupt-parent = <&mpic>;
581 interrupts = <16 2>;
582 pcie@0 {
583 reg = <0x0 0x0 0x0 0x0 0x0>;
584 #size-cells = <2>;
585 #address-cells = <3>;
586 device_type = "pci";
587 ranges = <0x2000000 0x0 0xc0000000
588 0x2000000 0x0 0xc0000000
589 0x0 0x20000000
590
591 0x1000000 0x0 0x0
592 0x1000000 0x0 0x0
593 0x0 0x100000>;
594 };
595 };
596};