Nicolas Pitre | 6b5cdf0 | 2008-06-27 18:56:22 -0400 | [diff] [blame] | 1 | /* |
| 2 | * arch/arm/mach-orion5x/rd88f5181l-fxo-setup.c |
| 3 | * |
| 4 | * Marvell Orion-VoIP FXO Reference Design Setup |
| 5 | * |
| 6 | * This file is licensed under the terms of the GNU General Public |
| 7 | * License version 2. This program is licensed "as is" without any |
| 8 | * warranty of any kind, whether express or implied. |
| 9 | */ |
Russell King | 2f8163b | 2011-07-26 10:53:52 +0100 | [diff] [blame] | 10 | #include <linux/gpio.h> |
Nicolas Pitre | 6b5cdf0 | 2008-06-27 18:56:22 -0400 | [diff] [blame] | 11 | #include <linux/kernel.h> |
| 12 | #include <linux/init.h> |
| 13 | #include <linux/platform_device.h> |
| 14 | #include <linux/pci.h> |
| 15 | #include <linux/irq.h> |
| 16 | #include <linux/mtd/physmap.h> |
| 17 | #include <linux/mv643xx_eth.h> |
Lennert Buytenhek | 81600eea9 | 2008-07-14 14:29:40 +0200 | [diff] [blame] | 18 | #include <linux/ethtool.h> |
Lennert Buytenhek | dcf1cec | 2008-09-25 16:23:48 +0200 | [diff] [blame] | 19 | #include <net/dsa.h> |
Nicolas Pitre | 6b5cdf0 | 2008-06-27 18:56:22 -0400 | [diff] [blame] | 20 | #include <asm/mach-types.h> |
Nicolas Pitre | 6b5cdf0 | 2008-06-27 18:56:22 -0400 | [diff] [blame] | 21 | #include <asm/leds.h> |
| 22 | #include <asm/mach/arch.h> |
| 23 | #include <asm/mach/pci.h> |
Russell King | a09e64f | 2008-08-05 16:14:15 +0100 | [diff] [blame] | 24 | #include <mach/orion5x.h> |
Nicolas Pitre | 6b5cdf0 | 2008-06-27 18:56:22 -0400 | [diff] [blame] | 25 | #include "common.h" |
| 26 | #include "mpp.h" |
| 27 | |
| 28 | /***************************************************************************** |
| 29 | * RD-88F5181L FXO Info |
| 30 | ****************************************************************************/ |
| 31 | /* |
| 32 | * 8M NOR flash Device bus boot chip select |
| 33 | */ |
| 34 | #define RD88F5181L_FXO_NOR_BOOT_BASE 0xff800000 |
| 35 | #define RD88F5181L_FXO_NOR_BOOT_SIZE SZ_8M |
| 36 | |
| 37 | |
| 38 | /***************************************************************************** |
| 39 | * 8M NOR Flash on Device bus Boot chip select |
| 40 | ****************************************************************************/ |
| 41 | static struct physmap_flash_data rd88f5181l_fxo_nor_boot_flash_data = { |
| 42 | .width = 1, |
| 43 | }; |
| 44 | |
| 45 | static struct resource rd88f5181l_fxo_nor_boot_flash_resource = { |
| 46 | .flags = IORESOURCE_MEM, |
| 47 | .start = RD88F5181L_FXO_NOR_BOOT_BASE, |
| 48 | .end = RD88F5181L_FXO_NOR_BOOT_BASE + |
| 49 | RD88F5181L_FXO_NOR_BOOT_SIZE - 1, |
| 50 | }; |
| 51 | |
| 52 | static struct platform_device rd88f5181l_fxo_nor_boot_flash = { |
| 53 | .name = "physmap-flash", |
| 54 | .id = 0, |
| 55 | .dev = { |
| 56 | .platform_data = &rd88f5181l_fxo_nor_boot_flash_data, |
| 57 | }, |
| 58 | .num_resources = 1, |
| 59 | .resource = &rd88f5181l_fxo_nor_boot_flash_resource, |
| 60 | }; |
| 61 | |
| 62 | |
| 63 | /***************************************************************************** |
| 64 | * General Setup |
| 65 | ****************************************************************************/ |
Andrew Lunn | 554cdae | 2011-05-15 13:32:53 +0200 | [diff] [blame] | 66 | static unsigned int rd88f5181l_fxo_mpp_modes[] __initdata = { |
| 67 | MPP0_GPIO, /* LED1 CardBus LED (front panel) */ |
| 68 | MPP1_GPIO, /* PCI_intA */ |
| 69 | MPP2_GPIO, /* Hard Reset / Factory Init*/ |
| 70 | MPP3_GPIO, /* FXS or DAA select */ |
| 71 | MPP4_GPIO, /* LED6 - phone LED (front panel) */ |
| 72 | MPP5_GPIO, /* LED5 - phone LED (front panel) */ |
| 73 | MPP6_PCI_CLK, /* CPU PCI refclk */ |
| 74 | MPP7_PCI_CLK, /* PCI/PCIe refclk */ |
| 75 | MPP8_GPIO, /* CardBus reset */ |
| 76 | MPP9_GPIO, /* GE_RXERR */ |
| 77 | MPP10_GPIO, /* LED2 MiniPCI LED (front panel) */ |
| 78 | MPP11_GPIO, /* Lifeline control */ |
| 79 | MPP12_GIGE, /* GE_TXD[4] */ |
| 80 | MPP13_GIGE, /* GE_TXD[5] */ |
| 81 | MPP14_GIGE, /* GE_TXD[6] */ |
| 82 | MPP15_GIGE, /* GE_TXD[7] */ |
| 83 | MPP16_GIGE, /* GE_RXD[4] */ |
| 84 | MPP17_GIGE, /* GE_RXD[5] */ |
| 85 | MPP18_GIGE, /* GE_RXD[6] */ |
| 86 | MPP19_GIGE, /* GE_RXD[7] */ |
| 87 | 0, |
Nicolas Pitre | 6b5cdf0 | 2008-06-27 18:56:22 -0400 | [diff] [blame] | 88 | }; |
| 89 | |
| 90 | static struct mv643xx_eth_platform_data rd88f5181l_fxo_eth_data = { |
Lennert Buytenhek | ac84060 | 2008-08-26 14:06:47 +0200 | [diff] [blame] | 91 | .phy_addr = MV643XX_ETH_PHY_NONE, |
Lennert Buytenhek | 81600eea9 | 2008-07-14 14:29:40 +0200 | [diff] [blame] | 92 | .speed = SPEED_1000, |
| 93 | .duplex = DUPLEX_FULL, |
Nicolas Pitre | 6b5cdf0 | 2008-06-27 18:56:22 -0400 | [diff] [blame] | 94 | }; |
| 95 | |
Lennert Buytenhek | e84665c | 2009-03-20 09:52:09 +0000 | [diff] [blame] | 96 | static struct dsa_chip_data rd88f5181l_fxo_switch_chip_data = { |
Lennert Buytenhek | dcf1cec | 2008-09-25 16:23:48 +0200 | [diff] [blame] | 97 | .port_names[0] = "lan2", |
| 98 | .port_names[1] = "lan1", |
| 99 | .port_names[2] = "wan", |
| 100 | .port_names[3] = "cpu", |
| 101 | .port_names[5] = "lan4", |
| 102 | .port_names[7] = "lan3", |
| 103 | }; |
| 104 | |
Lennert Buytenhek | e84665c | 2009-03-20 09:52:09 +0000 | [diff] [blame] | 105 | static struct dsa_platform_data rd88f5181l_fxo_switch_plat_data = { |
| 106 | .nr_chips = 1, |
| 107 | .chip = &rd88f5181l_fxo_switch_chip_data, |
| 108 | }; |
| 109 | |
Nicolas Pitre | 6b5cdf0 | 2008-06-27 18:56:22 -0400 | [diff] [blame] | 110 | static void __init rd88f5181l_fxo_init(void) |
| 111 | { |
| 112 | /* |
| 113 | * Setup basic Orion functions. Need to be called early. |
| 114 | */ |
| 115 | orion5x_init(); |
| 116 | |
| 117 | orion5x_mpp_conf(rd88f5181l_fxo_mpp_modes); |
| 118 | |
| 119 | /* |
| 120 | * Configure peripherals. |
| 121 | */ |
| 122 | orion5x_ehci0_init(); |
| 123 | orion5x_eth_init(&rd88f5181l_fxo_eth_data); |
Lennert Buytenhek | e84665c | 2009-03-20 09:52:09 +0000 | [diff] [blame] | 124 | orion5x_eth_switch_init(&rd88f5181l_fxo_switch_plat_data, NO_IRQ); |
Nicolas Pitre | 6b5cdf0 | 2008-06-27 18:56:22 -0400 | [diff] [blame] | 125 | orion5x_uart0_init(); |
| 126 | |
| 127 | orion5x_setup_dev_boot_win(RD88F5181L_FXO_NOR_BOOT_BASE, |
| 128 | RD88F5181L_FXO_NOR_BOOT_SIZE); |
| 129 | platform_device_register(&rd88f5181l_fxo_nor_boot_flash); |
| 130 | } |
| 131 | |
| 132 | static int __init |
Ralf Baechle | d534194 | 2011-06-10 15:30:21 +0100 | [diff] [blame] | 133 | rd88f5181l_fxo_pci_map_irq(const struct pci_dev *dev, u8 slot, u8 pin) |
Nicolas Pitre | 6b5cdf0 | 2008-06-27 18:56:22 -0400 | [diff] [blame] | 134 | { |
| 135 | int irq; |
| 136 | |
| 137 | /* |
| 138 | * Check for devices with hard-wired IRQs. |
| 139 | */ |
| 140 | irq = orion5x_pci_map_irq(dev, slot, pin); |
| 141 | if (irq != -1) |
| 142 | return irq; |
| 143 | |
| 144 | /* |
| 145 | * Mini-PCI / Cardbus slot. |
| 146 | */ |
| 147 | return gpio_to_irq(1); |
| 148 | } |
| 149 | |
| 150 | static struct hw_pci rd88f5181l_fxo_pci __initdata = { |
| 151 | .nr_controllers = 2, |
| 152 | .swizzle = pci_std_swizzle, |
| 153 | .setup = orion5x_pci_sys_setup, |
| 154 | .scan = orion5x_pci_sys_scan_bus, |
| 155 | .map_irq = rd88f5181l_fxo_pci_map_irq, |
| 156 | }; |
| 157 | |
| 158 | static int __init rd88f5181l_fxo_pci_init(void) |
| 159 | { |
| 160 | if (machine_is_rd88f5181l_fxo()) { |
| 161 | orion5x_pci_set_cardbus_mode(); |
| 162 | pci_common_init(&rd88f5181l_fxo_pci); |
| 163 | } |
| 164 | |
| 165 | return 0; |
| 166 | } |
| 167 | subsys_initcall(rd88f5181l_fxo_pci_init); |
| 168 | |
| 169 | MACHINE_START(RD88F5181L_FXO, "Marvell Orion-VoIP FXO Reference Design") |
| 170 | /* Maintainer: Nicolas Pitre <nico@marvell.com> */ |
Nicolas Pitre | 65aa1b1 | 2011-07-05 22:38:15 -0400 | [diff] [blame] | 171 | .atag_offset = 0x100, |
Nicolas Pitre | 6b5cdf0 | 2008-06-27 18:56:22 -0400 | [diff] [blame] | 172 | .init_machine = rd88f5181l_fxo_init, |
| 173 | .map_io = orion5x_map_io, |
Lennert Buytenhek | 4ee1f6b | 2010-10-15 16:50:26 +0200 | [diff] [blame] | 174 | .init_early = orion5x_init_early, |
Nicolas Pitre | 6b5cdf0 | 2008-06-27 18:56:22 -0400 | [diff] [blame] | 175 | .init_irq = orion5x_init_irq, |
| 176 | .timer = &orion5x_timer, |
| 177 | .fixup = tag_fixup_mem32, |
| 178 | MACHINE_END |