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gerrit-public.fairphone.software / kernel / msm / 792dd90f114a48c210c566f3642b26f699702cb7 / . / drivers / net / niu.c
blob: babb1ef37e3426d1693ab749804d3bc228a6ff4f [file] [log] [blame]
David S. Millera3138df2007-10-09 01:54:01 -0700[diff] [blame]1/* niu.c: Neptune ethernet driver.
2 *
3 * Copyright (C) 2007 David S. Miller (davem@davemloft.net)
4 */
5
6#include <linux/module.h>
7#include <linux/init.h>
8#include <linux/pci.h>
9#include <linux/dma-mapping.h>
10#include <linux/netdevice.h>
11#include <linux/ethtool.h>
12#include <linux/etherdevice.h>
13#include <linux/platform_device.h>
14#include <linux/delay.h>
15#include <linux/bitops.h>
16#include <linux/mii.h>
17#include <linux/if_ether.h>
18#include <linux/if_vlan.h>
19#include <linux/ip.h>
20#include <linux/in.h>
21#include <linux/ipv6.h>
22#include <linux/log2.h>
23#include <linux/jiffies.h>
24#include <linux/crc32.h>
25
26#include <linux/io.h>
27
28#ifdef CONFIG_SPARC64
29#include <linux/of_device.h>
30#endif
31
32#include "niu.h"
33
34#define DRV_MODULE_NAME "niu"
35#define PFX DRV_MODULE_NAME ": "
36#define DRV_MODULE_VERSION "0.5"
37#define DRV_MODULE_RELDATE "October 5, 2007"
38
39static char version[] __devinitdata =
40 DRV_MODULE_NAME ".c:v" DRV_MODULE_VERSION " (" DRV_MODULE_RELDATE ")\n";
41
42MODULE_AUTHOR("David S. Miller (davem@davemloft.net)");
43MODULE_DESCRIPTION("NIU ethernet driver");
44MODULE_LICENSE("GPL");
45MODULE_VERSION(DRV_MODULE_VERSION);
46
47#ifndef DMA_44BIT_MASK
48#define DMA_44BIT_MASK 0x00000fffffffffffULL
49#endif
50
51#ifndef readq
52static u64 readq(void __iomem *reg)
53{
54 return (((u64)readl(reg + 0x4UL) << 32) |
55 (u64)readl(reg));
56}
57
58static void writeq(u64 val, void __iomem *reg)
59{
60 writel(val & 0xffffffff, reg);
61 writel(val >> 32, reg + 0x4UL);
62}
63#endif
64
65static struct pci_device_id niu_pci_tbl[] = {
66 {PCI_DEVICE(PCI_VENDOR_ID_SUN, 0xabcd)},
67 {}
68};
69
70MODULE_DEVICE_TABLE(pci, niu_pci_tbl);
71
72#define NIU_TX_TIMEOUT (5 * HZ)
73
74#define nr64(reg) readq(np->regs + (reg))
75#define nw64(reg, val) writeq((val), np->regs + (reg))
76
77#define nr64_mac(reg) readq(np->mac_regs + (reg))
78#define nw64_mac(reg, val) writeq((val), np->mac_regs + (reg))
79
80#define nr64_ipp(reg) readq(np->regs + np->ipp_off + (reg))
81#define nw64_ipp(reg, val) writeq((val), np->regs + np->ipp_off + (reg))
82
83#define nr64_pcs(reg) readq(np->regs + np->pcs_off + (reg))
84#define nw64_pcs(reg, val) writeq((val), np->regs + np->pcs_off + (reg))
85
86#define nr64_xpcs(reg) readq(np->regs + np->xpcs_off + (reg))
87#define nw64_xpcs(reg, val) writeq((val), np->regs + np->xpcs_off + (reg))
88
89#define NIU_MSG_DEFAULT (NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_LINK)
90
91static int niu_debug;
92static int debug = -1;
93module_param(debug, int, 0);
94MODULE_PARM_DESC(debug, "NIU debug level");
95
96#define niudbg(TYPE, f, a...) \
97do { if ((np)->msg_enable & NETIF_MSG_##TYPE) \
98 printk(KERN_DEBUG PFX f, ## a); \
99} while (0)
100
101#define niuinfo(TYPE, f, a...) \
102do { if ((np)->msg_enable & NETIF_MSG_##TYPE) \
103 printk(KERN_INFO PFX f, ## a); \
104} while (0)
105
106#define niuwarn(TYPE, f, a...) \
107do { if ((np)->msg_enable & NETIF_MSG_##TYPE) \
108 printk(KERN_WARNING PFX f, ## a); \
109} while (0)
110
111#define niu_lock_parent(np, flags) \
112 spin_lock_irqsave(&np->parent->lock, flags)
113#define niu_unlock_parent(np, flags) \
114 spin_unlock_irqrestore(&np->parent->lock, flags)
115
116static int __niu_wait_bits_clear_mac(struct niu *np, unsigned long reg,
117 u64 bits, int limit, int delay)
118{
119 while (--limit >= 0) {
120 u64 val = nr64_mac(reg);
121
122 if (!(val & bits))
123 break;
124 udelay(delay);
125 }
126 if (limit < 0)
127 return -ENODEV;
128 return 0;
129}
130
131static int __niu_set_and_wait_clear_mac(struct niu *np, unsigned long reg,
132 u64 bits, int limit, int delay,
133 const char *reg_name)
134{
135 int err;
136
137 nw64_mac(reg, bits);
138 err = __niu_wait_bits_clear_mac(np, reg, bits, limit, delay);
139 if (err)
140 dev_err(np->device, PFX "%s: bits (%llx) of register %s "
141 "would not clear, val[%llx]\n",
142 np->dev->name, (unsigned long long) bits, reg_name,
143 (unsigned long long) nr64_mac(reg));
144 return err;
145}
146
147#define niu_set_and_wait_clear_mac(NP, REG, BITS, LIMIT, DELAY, REG_NAME) \
148({ BUILD_BUG_ON(LIMIT <= 0 || DELAY < 0); \
149 __niu_set_and_wait_clear_mac(NP, REG, BITS, LIMIT, DELAY, REG_NAME); \
150})
151
152static int __niu_wait_bits_clear_ipp(struct niu *np, unsigned long reg,
153 u64 bits, int limit, int delay)
154{
155 while (--limit >= 0) {
156 u64 val = nr64_ipp(reg);
157
158 if (!(val & bits))
159 break;
160 udelay(delay);
161 }
162 if (limit < 0)
163 return -ENODEV;
164 return 0;
165}
166
167static int __niu_set_and_wait_clear_ipp(struct niu *np, unsigned long reg,
168 u64 bits, int limit, int delay,
169 const char *reg_name)
170{
171 int err;
172 u64 val;
173
174 val = nr64_ipp(reg);
175 val |= bits;
176 nw64_ipp(reg, val);
177
178 err = __niu_wait_bits_clear_ipp(np, reg, bits, limit, delay);
179 if (err)
180 dev_err(np->device, PFX "%s: bits (%llx) of register %s "
181 "would not clear, val[%llx]\n",
182 np->dev->name, (unsigned long long) bits, reg_name,
183 (unsigned long long) nr64_ipp(reg));
184 return err;
185}
186
187#define niu_set_and_wait_clear_ipp(NP, REG, BITS, LIMIT, DELAY, REG_NAME) \
188({ BUILD_BUG_ON(LIMIT <= 0 || DELAY < 0); \
189 __niu_set_and_wait_clear_ipp(NP, REG, BITS, LIMIT, DELAY, REG_NAME); \
190})
191
192static int __niu_wait_bits_clear(struct niu *np, unsigned long reg,
193 u64 bits, int limit, int delay)
194{
195 while (--limit >= 0) {
196 u64 val = nr64(reg);
197
198 if (!(val & bits))
199 break;
200 udelay(delay);
201 }
202 if (limit < 0)
203 return -ENODEV;
204 return 0;
205}
206
207#define niu_wait_bits_clear(NP, REG, BITS, LIMIT, DELAY) \
208({ BUILD_BUG_ON(LIMIT <= 0 || DELAY < 0); \
209 __niu_wait_bits_clear(NP, REG, BITS, LIMIT, DELAY); \
210})
211
212static int __niu_set_and_wait_clear(struct niu *np, unsigned long reg,
213 u64 bits, int limit, int delay,
214 const char *reg_name)
215{
216 int err;
217
218 nw64(reg, bits);
219 err = __niu_wait_bits_clear(np, reg, bits, limit, delay);
220 if (err)
221 dev_err(np->device, PFX "%s: bits (%llx) of register %s "
222 "would not clear, val[%llx]\n",
223 np->dev->name, (unsigned long long) bits, reg_name,
224 (unsigned long long) nr64(reg));
225 return err;
226}
227
228#define niu_set_and_wait_clear(NP, REG, BITS, LIMIT, DELAY, REG_NAME) \
229({ BUILD_BUG_ON(LIMIT <= 0 || DELAY < 0); \
230 __niu_set_and_wait_clear(NP, REG, BITS, LIMIT, DELAY, REG_NAME); \
231})
232
233static void niu_ldg_rearm(struct niu *np, struct niu_ldg *lp, int on)
234{
235 u64 val = (u64) lp->timer;
236
237 if (on)
238 val |= LDG_IMGMT_ARM;
239
240 nw64(LDG_IMGMT(lp->ldg_num), val);
241}
242
243static int niu_ldn_irq_enable(struct niu *np, int ldn, int on)
244{
245 unsigned long mask_reg, bits;
246 u64 val;
247
248 if (ldn < 0 || ldn > LDN_MAX)
249 return -EINVAL;
250
251 if (ldn < 64) {
252 mask_reg = LD_IM0(ldn);
253 bits = LD_IM0_MASK;
254 } else {
255 mask_reg = LD_IM1(ldn - 64);
256 bits = LD_IM1_MASK;
257 }
258
259 val = nr64(mask_reg);
260 if (on)
261 val &= ~bits;
262 else
263 val |= bits;
264 nw64(mask_reg, val);
265
266 return 0;
267}
268
269static int niu_enable_ldn_in_ldg(struct niu *np, struct niu_ldg *lp, int on)
270{
271 struct niu_parent *parent = np->parent;
272 int i;
273
274 for (i = 0; i <= LDN_MAX; i++) {
275 int err;
276
277 if (parent->ldg_map[i] != lp->ldg_num)
278 continue;
279
280 err = niu_ldn_irq_enable(np, i, on);
281 if (err)
282 return err;
283 }
284 return 0;
285}
286
287static int niu_enable_interrupts(struct niu *np, int on)
288{
289 int i;
290
291 for (i = 0; i < np->num_ldg; i++) {
292 struct niu_ldg *lp = &np->ldg[i];
293 int err;
294
295 err = niu_enable_ldn_in_ldg(np, lp, on);
296 if (err)
297 return err;
298 }
299 for (i = 0; i < np->num_ldg; i++)
300 niu_ldg_rearm(np, &np->ldg[i], on);
301
302 return 0;
303}
304
305static u32 phy_encode(u32 type, int port)
306{
307 return (type << (port * 2));
308}
309
310static u32 phy_decode(u32 val, int port)
311{
312 return (val >> (port * 2)) & PORT_TYPE_MASK;
313}
314
315static int mdio_wait(struct niu *np)
316{
317 int limit = 1000;
318 u64 val;
319
320 while (--limit > 0) {
321 val = nr64(MIF_FRAME_OUTPUT);
322 if ((val >> MIF_FRAME_OUTPUT_TA_SHIFT) & 0x1)
323 return val & MIF_FRAME_OUTPUT_DATA;
324
325 udelay(10);
326 }
327
328 return -ENODEV;
329}
330
331static int mdio_read(struct niu *np, int port, int dev, int reg)
332{
333 int err;
334
335 nw64(MIF_FRAME_OUTPUT, MDIO_ADDR_OP(port, dev, reg));
336 err = mdio_wait(np);
337 if (err < 0)
338 return err;
339
340 nw64(MIF_FRAME_OUTPUT, MDIO_READ_OP(port, dev));
341 return mdio_wait(np);
342}
343
344static int mdio_write(struct niu *np, int port, int dev, int reg, int data)
345{
346 int err;
347
348 nw64(MIF_FRAME_OUTPUT, MDIO_ADDR_OP(port, dev, reg));
349 err = mdio_wait(np);
350 if (err < 0)
351 return err;
352
353 nw64(MIF_FRAME_OUTPUT, MDIO_WRITE_OP(port, dev, data));
354 err = mdio_wait(np);
355 if (err < 0)
356 return err;
357
358 return 0;
359}
360
361static int mii_read(struct niu *np, int port, int reg)
362{
363 nw64(MIF_FRAME_OUTPUT, MII_READ_OP(port, reg));
364 return mdio_wait(np);
365}
366
367static int mii_write(struct niu *np, int port, int reg, int data)
368{
369 int err;
370
371 nw64(MIF_FRAME_OUTPUT, MII_WRITE_OP(port, reg, data));
372 err = mdio_wait(np);
373 if (err < 0)
374 return err;
375
376 return 0;
377}
378
379static int esr2_set_tx_cfg(struct niu *np, unsigned long channel, u32 val)
380{
381 int err;
382
383 err = mdio_write(np, np->port, NIU_ESR2_DEV_ADDR,
384 ESR2_TI_PLL_TX_CFG_L(channel),
385 val & 0xffff);
386 if (!err)
387 err = mdio_write(np, np->port, NIU_ESR2_DEV_ADDR,
388 ESR2_TI_PLL_TX_CFG_H(channel),
389 val >> 16);
390 return err;
391}
392
393static int esr2_set_rx_cfg(struct niu *np, unsigned long channel, u32 val)
394{
395 int err;
396
397 err = mdio_write(np, np->port, NIU_ESR2_DEV_ADDR,
398 ESR2_TI_PLL_RX_CFG_L(channel),
399 val & 0xffff);
400 if (!err)
401 err = mdio_write(np, np->port, NIU_ESR2_DEV_ADDR,
402 ESR2_TI_PLL_RX_CFG_H(channel),
403 val >> 16);
404 return err;
405}
406
407/* Mode is always 10G fiber. */
408static int serdes_init_niu(struct niu *np)
409{
410 struct niu_link_config *lp = &np->link_config;
411 u32 tx_cfg, rx_cfg;
412 unsigned long i;
413
414 tx_cfg = (PLL_TX_CFG_ENTX | PLL_TX_CFG_SWING_1375MV);
415 rx_cfg = (PLL_RX_CFG_ENRX | PLL_RX_CFG_TERM_0P8VDDT |
416 PLL_RX_CFG_ALIGN_ENA | PLL_RX_CFG_LOS_LTHRESH |
417 PLL_RX_CFG_EQ_LP_ADAPTIVE);
418
419 if (lp->loopback_mode == LOOPBACK_PHY) {
420 u16 test_cfg = PLL_TEST_CFG_LOOPBACK_CML_DIS;
421
422 mdio_write(np, np->port, NIU_ESR2_DEV_ADDR,
423 ESR2_TI_PLL_TEST_CFG_L, test_cfg);
424
425 tx_cfg |= PLL_TX_CFG_ENTEST;
426 rx_cfg |= PLL_RX_CFG_ENTEST;
427 }
428
429 /* Initialize all 4 lanes of the SERDES. */
430 for (i = 0; i < 4; i++) {
431 int err = esr2_set_tx_cfg(np, i, tx_cfg);
432 if (err)
433 return err;
434 }
435
436 for (i = 0; i < 4; i++) {
437 int err = esr2_set_rx_cfg(np, i, rx_cfg);
438 if (err)
439 return err;
440 }
441
442 return 0;
443}
444
445static int esr_read_rxtx_ctrl(struct niu *np, unsigned long chan, u32 *val)
446{
447 int err;
448
449 err = mdio_read(np, np->port, NIU_ESR_DEV_ADDR, ESR_RXTX_CTRL_L(chan));
450 if (err >= 0) {
451 *val = (err & 0xffff);
452 err = mdio_read(np, np->port, NIU_ESR_DEV_ADDR,
453 ESR_RXTX_CTRL_H(chan));
454 if (err >= 0)
455 *val |= ((err & 0xffff) << 16);
456 err = 0;
457 }
458 return err;
459}
460
461static int esr_read_glue0(struct niu *np, unsigned long chan, u32 *val)
462{
463 int err;
464
465 err = mdio_read(np, np->port, NIU_ESR_DEV_ADDR,
466 ESR_GLUE_CTRL0_L(chan));
467 if (err >= 0) {
468 *val = (err & 0xffff);
469 err = mdio_read(np, np->port, NIU_ESR_DEV_ADDR,
470 ESR_GLUE_CTRL0_H(chan));
471 if (err >= 0) {
472 *val |= ((err & 0xffff) << 16);
473 err = 0;
474 }
475 }
476 return err;
477}
478
479static int esr_read_reset(struct niu *np, u32 *val)
480{
481 int err;
482
483 err = mdio_read(np, np->port, NIU_ESR_DEV_ADDR,
484 ESR_RXTX_RESET_CTRL_L);
485 if (err >= 0) {
486 *val = (err & 0xffff);
487 err = mdio_read(np, np->port, NIU_ESR_DEV_ADDR,
488 ESR_RXTX_RESET_CTRL_H);
489 if (err >= 0) {
490 *val |= ((err & 0xffff) << 16);
491 err = 0;
492 }
493 }
494 return err;
495}
496
497static int esr_write_rxtx_ctrl(struct niu *np, unsigned long chan, u32 val)
498{
499 int err;
500
501 err = mdio_write(np, np->port, NIU_ESR_DEV_ADDR,
502 ESR_RXTX_CTRL_L(chan), val & 0xffff);
503 if (!err)
504 err = mdio_write(np, np->port, NIU_ESR_DEV_ADDR,
505 ESR_RXTX_CTRL_H(chan), (val >> 16));
506 return err;
507}
508
509static int esr_write_glue0(struct niu *np, unsigned long chan, u32 val)
510{
511 int err;
512
513 err = mdio_write(np, np->port, NIU_ESR_DEV_ADDR,
514 ESR_GLUE_CTRL0_L(chan), val & 0xffff);
515 if (!err)
516 err = mdio_write(np, np->port, NIU_ESR_DEV_ADDR,
517 ESR_GLUE_CTRL0_H(chan), (val >> 16));
518 return err;
519}
520
521static int esr_reset(struct niu *np)
522{
523 u32 reset;
524 int err;
525
526 err = mdio_write(np, np->port, NIU_ESR_DEV_ADDR,
527 ESR_RXTX_RESET_CTRL_L, 0x0000);
528 if (err)
529 return err;
530 err = mdio_write(np, np->port, NIU_ESR_DEV_ADDR,
531 ESR_RXTX_RESET_CTRL_H, 0xffff);
532 if (err)
533 return err;
534 udelay(200);
535
536 err = mdio_write(np, np->port, NIU_ESR_DEV_ADDR,
537 ESR_RXTX_RESET_CTRL_L, 0xffff);
538 if (err)
539 return err;
540 udelay(200);
541
542 err = mdio_write(np, np->port, NIU_ESR_DEV_ADDR,
543 ESR_RXTX_RESET_CTRL_H, 0x0000);
544 if (err)
545 return err;
546 udelay(200);
547
548 err = esr_read_reset(np, &reset);
549 if (err)
550 return err;
551 if (reset != 0) {
552 dev_err(np->device, PFX "Port %u ESR_RESET "
553 "did not clear [%08x]\n",
554 np->port, reset);
555 return -ENODEV;
556 }
557
558 return 0;
559}
560
561static int serdes_init_10g(struct niu *np)
562{
563 struct niu_link_config *lp = &np->link_config;
564 unsigned long ctrl_reg, test_cfg_reg, i;
565 u64 ctrl_val, test_cfg_val, sig, mask, val;
566 int err;
567
568 switch (np->port) {
569 case 0:
570 ctrl_reg = ENET_SERDES_0_CTRL_CFG;
571 test_cfg_reg = ENET_SERDES_0_TEST_CFG;
572 break;
573 case 1:
574 ctrl_reg = ENET_SERDES_1_CTRL_CFG;
575 test_cfg_reg = ENET_SERDES_1_TEST_CFG;
576 break;
577
578 default:
579 return -EINVAL;
580 }
581 ctrl_val = (ENET_SERDES_CTRL_SDET_0 |
582 ENET_SERDES_CTRL_SDET_1 |
583 ENET_SERDES_CTRL_SDET_2 |
584 ENET_SERDES_CTRL_SDET_3 |
585 (0x5 << ENET_SERDES_CTRL_EMPH_0_SHIFT) |
586 (0x5 << ENET_SERDES_CTRL_EMPH_1_SHIFT) |
587 (0x5 << ENET_SERDES_CTRL_EMPH_2_SHIFT) |
588 (0x5 << ENET_SERDES_CTRL_EMPH_3_SHIFT) |
589 (0x1 << ENET_SERDES_CTRL_LADJ_0_SHIFT) |
590 (0x1 << ENET_SERDES_CTRL_LADJ_1_SHIFT) |
591 (0x1 << ENET_SERDES_CTRL_LADJ_2_SHIFT) |
592 (0x1 << ENET_SERDES_CTRL_LADJ_3_SHIFT));
593 test_cfg_val = 0;
594
595 if (lp->loopback_mode == LOOPBACK_PHY) {
596 test_cfg_val |= ((ENET_TEST_MD_PAD_LOOPBACK <<
597 ENET_SERDES_TEST_MD_0_SHIFT) |
598 (ENET_TEST_MD_PAD_LOOPBACK <<
599 ENET_SERDES_TEST_MD_1_SHIFT) |
600 (ENET_TEST_MD_PAD_LOOPBACK <<
601 ENET_SERDES_TEST_MD_2_SHIFT) |
602 (ENET_TEST_MD_PAD_LOOPBACK <<
603 ENET_SERDES_TEST_MD_3_SHIFT));
604 }
605
606 nw64(ctrl_reg, ctrl_val);
607 nw64(test_cfg_reg, test_cfg_val);
608
609 /* Initialize all 4 lanes of the SERDES. */
610 for (i = 0; i < 4; i++) {
611 u32 rxtx_ctrl, glue0;
612
613 err = esr_read_rxtx_ctrl(np, i, &rxtx_ctrl);
614 if (err)
615 return err;
616 err = esr_read_glue0(np, i, &glue0);
617 if (err)
618 return err;
619
620 rxtx_ctrl &= ~(ESR_RXTX_CTRL_VMUXLO);
621 rxtx_ctrl |= (ESR_RXTX_CTRL_ENSTRETCH |
622 (2 << ESR_RXTX_CTRL_VMUXLO_SHIFT));
623
624 glue0 &= ~(ESR_GLUE_CTRL0_SRATE |
625 ESR_GLUE_CTRL0_THCNT |
626 ESR_GLUE_CTRL0_BLTIME);
627 glue0 |= (ESR_GLUE_CTRL0_RXLOSENAB |
628 (0xf << ESR_GLUE_CTRL0_SRATE_SHIFT) |
629 (0xff << ESR_GLUE_CTRL0_THCNT_SHIFT) |
630 (BLTIME_300_CYCLES <<
631 ESR_GLUE_CTRL0_BLTIME_SHIFT));
632
633 err = esr_write_rxtx_ctrl(np, i, rxtx_ctrl);
634 if (err)
635 return err;
636 err = esr_write_glue0(np, i, glue0);
637 if (err)
638 return err;
639 }
640
641 err = esr_reset(np);
642 if (err)
643 return err;
644
645 sig = nr64(ESR_INT_SIGNALS);
646 switch (np->port) {
647 case 0:
648 mask = ESR_INT_SIGNALS_P0_BITS;
649 val = (ESR_INT_SRDY0_P0 |
650 ESR_INT_DET0_P0 |
651 ESR_INT_XSRDY_P0 |
652 ESR_INT_XDP_P0_CH3 |
653 ESR_INT_XDP_P0_CH2 |
654 ESR_INT_XDP_P0_CH1 |
655 ESR_INT_XDP_P0_CH0);
656 break;
657
658 case 1:
659 mask = ESR_INT_SIGNALS_P1_BITS;
660 val = (ESR_INT_SRDY0_P1 |
661 ESR_INT_DET0_P1 |
662 ESR_INT_XSRDY_P1 |
663 ESR_INT_XDP_P1_CH3 |
664 ESR_INT_XDP_P1_CH2 |
665 ESR_INT_XDP_P1_CH1 |
666 ESR_INT_XDP_P1_CH0);
667 break;
668
669 default:
670 return -EINVAL;
671 }
672
673 if ((sig & mask) != val) {
674 dev_err(np->device, PFX "Port %u signal bits [%08x] are not "
675 "[%08x]\n", np->port, (int) (sig & mask), (int) val);
676 return -ENODEV;
677 }
678
679 return 0;
680}
681
682static int serdes_init_1g(struct niu *np)
683{
684 u64 val;
685
686 val = nr64(ENET_SERDES_1_PLL_CFG);
687 val &= ~ENET_SERDES_PLL_FBDIV2;
688 switch (np->port) {
689 case 0:
690 val |= ENET_SERDES_PLL_HRATE0;
691 break;
692 case 1:
693 val |= ENET_SERDES_PLL_HRATE1;
694 break;
695 case 2:
696 val |= ENET_SERDES_PLL_HRATE2;
697 break;
698 case 3:
699 val |= ENET_SERDES_PLL_HRATE3;
700 break;
701 default:
702 return -EINVAL;
703 }
704 nw64(ENET_SERDES_1_PLL_CFG, val);
705
706 return 0;
707}
708
709static int bcm8704_reset(struct niu *np)
710{
711 int err, limit;
712
713 err = mdio_read(np, np->phy_addr,
714 BCM8704_PHYXS_DEV_ADDR, MII_BMCR);
715 if (err < 0)
716 return err;
717 err |= BMCR_RESET;
718 err = mdio_write(np, np->phy_addr, BCM8704_PHYXS_DEV_ADDR,
719 MII_BMCR, err);
720 if (err)
721 return err;
722
723 limit = 1000;
724 while (--limit >= 0) {
725 err = mdio_read(np, np->phy_addr,
726 BCM8704_PHYXS_DEV_ADDR, MII_BMCR);
727 if (err < 0)
728 return err;
729 if (!(err & BMCR_RESET))
730 break;
731 }
732 if (limit < 0) {
733 dev_err(np->device, PFX "Port %u PHY will not reset "
734 "(bmcr=%04x)\n", np->port, (err & 0xffff));
735 return -ENODEV;
736 }
737 return 0;
738}
739
740/* When written, certain PHY registers need to be read back twice
741 * in order for the bits to settle properly.
742 */
743static int bcm8704_user_dev3_readback(struct niu *np, int reg)
744{
745 int err = mdio_read(np, np->phy_addr, BCM8704_USER_DEV3_ADDR, reg);
746 if (err < 0)
747 return err;
748 err = mdio_read(np, np->phy_addr, BCM8704_USER_DEV3_ADDR, reg);
749 if (err < 0)
750 return err;
751 return 0;
752}
753
754static int bcm8704_init_user_dev3(struct niu *np)
755{
756 int err;
757
758 err = mdio_write(np, np->phy_addr,
759 BCM8704_USER_DEV3_ADDR, BCM8704_USER_CONTROL,
760 (USER_CONTROL_OPTXRST_LVL |
761 USER_CONTROL_OPBIASFLT_LVL |
762 USER_CONTROL_OBTMPFLT_LVL |
763 USER_CONTROL_OPPRFLT_LVL |
764 USER_CONTROL_OPTXFLT_LVL |
765 USER_CONTROL_OPRXLOS_LVL |
766 USER_CONTROL_OPRXFLT_LVL |
767 USER_CONTROL_OPTXON_LVL |
768 (0x3f << USER_CONTROL_RES1_SHIFT)));
769 if (err)
770 return err;
771
772 err = mdio_write(np, np->phy_addr,
773 BCM8704_USER_DEV3_ADDR, BCM8704_USER_PMD_TX_CONTROL,
774 (USER_PMD_TX_CTL_XFP_CLKEN |
775 (1 << USER_PMD_TX_CTL_TX_DAC_TXD_SH) |
776 (2 << USER_PMD_TX_CTL_TX_DAC_TXCK_SH) |
777 USER_PMD_TX_CTL_TSCK_LPWREN));
778 if (err)
779 return err;
780
781 err = bcm8704_user_dev3_readback(np, BCM8704_USER_CONTROL);
782 if (err)
783 return err;
784 err = bcm8704_user_dev3_readback(np, BCM8704_USER_PMD_TX_CONTROL);
785 if (err)
786 return err;
787
788 err = mdio_read(np, np->phy_addr, BCM8704_USER_DEV3_ADDR,
789 BCM8704_USER_OPT_DIGITAL_CTRL);
790 if (err < 0)
791 return err;
792 err &= ~USER_ODIG_CTRL_GPIOS;
793 err |= (0x3 << USER_ODIG_CTRL_GPIOS_SHIFT);
794 err = mdio_write(np, np->phy_addr, BCM8704_USER_DEV3_ADDR,
795 BCM8704_USER_OPT_DIGITAL_CTRL, err);
796 if (err)
797 return err;
798
799 mdelay(1000);
800
801 return 0;
802}
803
804static int xcvr_init_10g(struct niu *np)
805{
806 struct niu_link_config *lp = &np->link_config;
807 u16 analog_stat0, tx_alarm_status;
808 int err;
809 u64 val;
810
811 val = nr64_mac(XMAC_CONFIG);
812 val &= ~XMAC_CONFIG_LED_POLARITY;
813 val |= XMAC_CONFIG_FORCE_LED_ON;
814 nw64_mac(XMAC_CONFIG, val);
815
816 /* XXX shared resource, lock parent XXX */
817 val = nr64(MIF_CONFIG);
818 val |= MIF_CONFIG_INDIRECT_MODE;
819 nw64(MIF_CONFIG, val);
820
821 err = bcm8704_reset(np);
822 if (err)
823 return err;
824
825 err = bcm8704_init_user_dev3(np);
826 if (err)
827 return err;
828
829 err = mdio_read(np, np->phy_addr, BCM8704_PCS_DEV_ADDR,
830 MII_BMCR);
831 if (err < 0)
832 return err;
833 err &= ~BMCR_LOOPBACK;
834
835 if (lp->loopback_mode == LOOPBACK_MAC)
836 err |= BMCR_LOOPBACK;
837
838 err = mdio_write(np, np->phy_addr, BCM8704_PCS_DEV_ADDR,
839 MII_BMCR, err);
840 if (err)
841 return err;
842
843#if 1
844 err = mdio_read(np, np->phy_addr, BCM8704_PMA_PMD_DEV_ADDR,
845 MII_STAT1000);
846 if (err < 0)
847 return err;
848 pr_info(PFX "Port %u PMA_PMD(MII_STAT1000) [%04x]\n",
849 np->port, err);
850
851 err = mdio_read(np, np->phy_addr, BCM8704_USER_DEV3_ADDR, 0x20);
852 if (err < 0)
853 return err;
854 pr_info(PFX "Port %u USER_DEV3(0x20) [%04x]\n",
855 np->port, err);
856
857 err = mdio_read(np, np->phy_addr, BCM8704_PHYXS_DEV_ADDR,
858 MII_NWAYTEST);
859 if (err < 0)
860 return err;
861 pr_info(PFX "Port %u PHYXS(MII_NWAYTEST) [%04x]\n",
862 np->port, err);
863#endif
864
865 /* XXX dig this out it might not be so useful XXX */
866 err = mdio_read(np, np->phy_addr, BCM8704_USER_DEV3_ADDR,
867 BCM8704_USER_ANALOG_STATUS0);
868 if (err < 0)
869 return err;
870 err = mdio_read(np, np->phy_addr, BCM8704_USER_DEV3_ADDR,
871 BCM8704_USER_ANALOG_STATUS0);
872 if (err < 0)
873 return err;
874 analog_stat0 = err;
875
876 err = mdio_read(np, np->phy_addr, BCM8704_USER_DEV3_ADDR,
877 BCM8704_USER_TX_ALARM_STATUS);
878 if (err < 0)
879 return err;
880 err = mdio_read(np, np->phy_addr, BCM8704_USER_DEV3_ADDR,
881 BCM8704_USER_TX_ALARM_STATUS);
882 if (err < 0)
883 return err;
884 tx_alarm_status = err;
885
886 if (analog_stat0 != 0x03fc) {
887 if ((analog_stat0 == 0x43bc) && (tx_alarm_status != 0)) {
888 pr_info(PFX "Port %u cable not connected "
889 "or bad cable.\n", np->port);
890 } else if (analog_stat0 == 0x639c) {
891 pr_info(PFX "Port %u optical module is bad "
892 "or missing.\n", np->port);
893 }
894 }
895
896 return 0;
897}
898
899static int mii_reset(struct niu *np)
900{
901 int limit, err;
902
903 err = mii_write(np, np->phy_addr, MII_BMCR, BMCR_RESET);
904 if (err)
905 return err;
906
907 limit = 1000;
908 while (--limit >= 0) {
909 udelay(500);
910 err = mii_read(np, np->phy_addr, MII_BMCR);
911 if (err < 0)
912 return err;
913 if (!(err & BMCR_RESET))
914 break;
915 }
916 if (limit < 0) {
917 dev_err(np->device, PFX "Port %u MII would not reset, "
918 "bmcr[%04x]\n", np->port, err);
919 return -ENODEV;
920 }
921
922 return 0;
923}
924
925static int mii_init_common(struct niu *np)
926{
927 struct niu_link_config *lp = &np->link_config;
928 u16 bmcr, bmsr, adv, estat;
929 int err;
930
931 err = mii_reset(np);
932 if (err)
933 return err;
934
935 err = mii_read(np, np->phy_addr, MII_BMSR);
936 if (err < 0)
937 return err;
938 bmsr = err;
939
940 estat = 0;
941 if (bmsr & BMSR_ESTATEN) {
942 err = mii_read(np, np->phy_addr, MII_ESTATUS);
943 if (err < 0)
944 return err;
945 estat = err;
946 }
947
948 bmcr = 0;
949 err = mii_write(np, np->phy_addr, MII_BMCR, bmcr);
950 if (err)
951 return err;
952
953 if (lp->loopback_mode == LOOPBACK_MAC) {
954 bmcr |= BMCR_LOOPBACK;
955 if (lp->active_speed == SPEED_1000)
956 bmcr |= BMCR_SPEED1000;
957 if (lp->active_duplex == DUPLEX_FULL)
958 bmcr |= BMCR_FULLDPLX;
959 }
960
961 if (lp->loopback_mode == LOOPBACK_PHY) {
962 u16 aux;
963
964 aux = (BCM5464R_AUX_CTL_EXT_LB |
965 BCM5464R_AUX_CTL_WRITE_1);
966 err = mii_write(np, np->phy_addr, BCM5464R_AUX_CTL, aux);
967 if (err)
968 return err;
969 }
970
971 /* XXX configurable XXX */
972 /* XXX for now don't advertise half-duplex or asym pause... XXX */
973 adv = ADVERTISE_CSMA | ADVERTISE_PAUSE_CAP;
974 if (bmsr & BMSR_10FULL)
975 adv |= ADVERTISE_10FULL;
976 if (bmsr & BMSR_100FULL)
977 adv |= ADVERTISE_100FULL;
978 err = mii_write(np, np->phy_addr, MII_ADVERTISE, adv);
979 if (err)
980 return err;
981
982 if (bmsr & BMSR_ESTATEN) {
983 u16 ctrl1000 = 0;
984
985 if (estat & ESTATUS_1000_TFULL)
986 ctrl1000 |= ADVERTISE_1000FULL;
987 err = mii_write(np, np->phy_addr, MII_CTRL1000, ctrl1000);
988 if (err)
989 return err;
990 }
991 bmcr |= (BMCR_ANENABLE | BMCR_ANRESTART);
992
993 err = mii_write(np, np->phy_addr, MII_BMCR, bmcr);
994 if (err)
995 return err;
996
997 err = mii_read(np, np->phy_addr, MII_BMCR);
998 if (err < 0)
999 return err;
1000 err = mii_read(np, np->phy_addr, MII_BMSR);
1001 if (err < 0)
1002 return err;
1003#if 0
1004 pr_info(PFX "Port %u after MII init bmcr[%04x] bmsr[%04x]\n",
1005 np->port, bmcr, bmsr);
1006#endif
1007
1008 return 0;
1009}
1010
1011static int xcvr_init_1g(struct niu *np)
1012{
1013 u64 val;
1014
1015 /* XXX shared resource, lock parent XXX */
1016 val = nr64(MIF_CONFIG);
1017 val &= ~MIF_CONFIG_INDIRECT_MODE;
1018 nw64(MIF_CONFIG, val);
1019
1020 return mii_init_common(np);
1021}
1022
1023static int niu_xcvr_init(struct niu *np)
1024{
1025 const struct niu_phy_ops *ops = np->phy_ops;
1026 int err;
1027
1028 err = 0;
1029 if (ops->xcvr_init)
1030 err = ops->xcvr_init(np);
1031
1032 return err;
1033}
1034
1035static int niu_serdes_init(struct niu *np)
1036{
1037 const struct niu_phy_ops *ops = np->phy_ops;
1038 int err;
1039
1040 err = 0;
1041 if (ops->serdes_init)
1042 err = ops->serdes_init(np);
1043
1044 return err;
1045}
1046
1047static void niu_init_xif(struct niu *);
Mirko Lindner0c3b0912007-12-05 21:10:02 -0800[diff] [blame]1048static void niu_handle_led(struct niu *, int status);
David S. Millera3138df2007-10-09 01:54:01 -0700[diff] [blame]1049
1050static int niu_link_status_common(struct niu *np, int link_up)
1051{
1052 struct niu_link_config *lp = &np->link_config;
1053 struct net_device *dev = np->dev;
1054 unsigned long flags;
1055
1056 if (!netif_carrier_ok(dev) && link_up) {
1057 niuinfo(LINK, "%s: Link is up at %s, %s duplex\n",
1058 dev->name,
1059 (lp->active_speed == SPEED_10000 ?
1060 "10Gb/sec" :
1061 (lp->active_speed == SPEED_1000 ?
1062 "1Gb/sec" :
1063 (lp->active_speed == SPEED_100 ?
1064 "100Mbit/sec" : "10Mbit/sec"))),
1065 (lp->active_duplex == DUPLEX_FULL ?
1066 "full" : "half"));
1067
1068 spin_lock_irqsave(&np->lock, flags);
1069 niu_init_xif(np);
Mirko Lindner0c3b0912007-12-05 21:10:02 -0800[diff] [blame]1070 niu_handle_led(np, 1);
David S. Millera3138df2007-10-09 01:54:01 -0700[diff] [blame]1071 spin_unlock_irqrestore(&np->lock, flags);
1072
1073 netif_carrier_on(dev);
1074 } else if (netif_carrier_ok(dev) && !link_up) {
1075 niuwarn(LINK, "%s: Link is down\n", dev->name);
Mirko Lindner0c3b0912007-12-05 21:10:02 -0800[diff] [blame]1076 spin_lock_irqsave(&np->lock, flags);
1077 niu_handle_led(np, 0);
1078 spin_unlock_irqrestore(&np->lock, flags);
David S. Millera3138df2007-10-09 01:54:01 -0700[diff] [blame]1079 netif_carrier_off(dev);
1080 }
1081
1082 return 0;
1083}
1084
1085static int link_status_10g(struct niu *np, int *link_up_p)
1086{
1087 unsigned long flags;
1088 int err, link_up;
1089
1090 link_up = 0;
1091
1092 spin_lock_irqsave(&np->lock, flags);
1093
1094 err = -EINVAL;
1095 if (np->link_config.loopback_mode != LOOPBACK_DISABLED)
1096 goto out;
1097
1098 err = mdio_read(np, np->phy_addr, BCM8704_PMA_PMD_DEV_ADDR,
1099 BCM8704_PMD_RCV_SIGDET);
1100 if (err < 0)
1101 goto out;
1102 if (!(err & PMD_RCV_SIGDET_GLOBAL)) {
1103 err = 0;
1104 goto out;
1105 }
1106
1107 err = mdio_read(np, np->phy_addr, BCM8704_PCS_DEV_ADDR,
1108 BCM8704_PCS_10G_R_STATUS);
1109 if (err < 0)
1110 goto out;
1111 if (!(err & PCS_10G_R_STATUS_BLK_LOCK)) {
1112 err = 0;
1113 goto out;
1114 }
1115
1116 err = mdio_read(np, np->phy_addr, BCM8704_PHYXS_DEV_ADDR,
1117 BCM8704_PHYXS_XGXS_LANE_STAT);
1118 if (err < 0)
1119 goto out;
1120
1121 if (err != (PHYXS_XGXS_LANE_STAT_ALINGED |
1122 PHYXS_XGXS_LANE_STAT_MAGIC |
1123 PHYXS_XGXS_LANE_STAT_LANE3 |
1124 PHYXS_XGXS_LANE_STAT_LANE2 |
1125 PHYXS_XGXS_LANE_STAT_LANE1 |
1126 PHYXS_XGXS_LANE_STAT_LANE0)) {
1127 err = 0;
1128 goto out;
1129 }
1130
1131 link_up = 1;
1132 np->link_config.active_speed = SPEED_10000;
1133 np->link_config.active_duplex = DUPLEX_FULL;
1134 err = 0;
1135
1136out:
1137 spin_unlock_irqrestore(&np->lock, flags);
1138
1139 *link_up_p = link_up;
1140 return err;
1141}
1142
1143static int link_status_1g(struct niu *np, int *link_up_p)
1144{
1145 u16 current_speed, bmsr;
1146 unsigned long flags;
1147 u8 current_duplex;
1148 int err, link_up;
1149
1150 link_up = 0;
1151 current_speed = SPEED_INVALID;
1152 current_duplex = DUPLEX_INVALID;
1153
1154 spin_lock_irqsave(&np->lock, flags);
1155
1156 err = -EINVAL;
1157 if (np->link_config.loopback_mode != LOOPBACK_DISABLED)
1158 goto out;
1159
1160 err = mii_read(np, np->phy_addr, MII_BMSR);
1161 if (err < 0)
1162 goto out;
1163
1164 bmsr = err;
1165 if (bmsr & BMSR_LSTATUS) {
1166 u16 adv, lpa, common, estat;
1167
1168 err = mii_read(np, np->phy_addr, MII_ADVERTISE);
1169 if (err < 0)
1170 goto out;
1171 adv = err;
1172
1173 err = mii_read(np, np->phy_addr, MII_LPA);
1174 if (err < 0)
1175 goto out;
1176 lpa = err;
1177
1178 common = adv & lpa;
1179
1180 err = mii_read(np, np->phy_addr, MII_ESTATUS);
1181 if (err < 0)
1182 goto out;
1183 estat = err;
1184
1185 link_up = 1;
1186 if (estat & (ESTATUS_1000_TFULL | ESTATUS_1000_THALF)) {
1187 current_speed = SPEED_1000;
1188 if (estat & ESTATUS_1000_TFULL)
1189 current_duplex = DUPLEX_FULL;
1190 else
1191 current_duplex = DUPLEX_HALF;
1192 } else {
1193 if (common & ADVERTISE_100BASE4) {
1194 current_speed = SPEED_100;
1195 current_duplex = DUPLEX_HALF;
1196 } else if (common & ADVERTISE_100FULL) {
1197 current_speed = SPEED_100;
1198 current_duplex = DUPLEX_FULL;
1199 } else if (common & ADVERTISE_100HALF) {
1200 current_speed = SPEED_100;
1201 current_duplex = DUPLEX_HALF;
1202 } else if (common & ADVERTISE_10FULL) {
1203 current_speed = SPEED_10;
1204 current_duplex = DUPLEX_FULL;
1205 } else if (common & ADVERTISE_10HALF) {
1206 current_speed = SPEED_10;
1207 current_duplex = DUPLEX_HALF;
1208 } else
1209 link_up = 0;
1210 }
1211 }
1212 err = 0;
1213
1214out:
1215 spin_unlock_irqrestore(&np->lock, flags);
1216
1217 *link_up_p = link_up;
1218 return err;
1219}
1220
1221static int niu_link_status(struct niu *np, int *link_up_p)
1222{
1223 const struct niu_phy_ops *ops = np->phy_ops;
1224 int err;
1225
1226 err = 0;
1227 if (ops->link_status)
1228 err = ops->link_status(np, link_up_p);
1229
1230 return err;
1231}
1232
1233static void niu_timer(unsigned long __opaque)
1234{
1235 struct niu *np = (struct niu *) __opaque;
1236 unsigned long off;
1237 int err, link_up;
1238
1239 err = niu_link_status(np, &link_up);
1240 if (!err)
1241 niu_link_status_common(np, link_up);
1242
1243 if (netif_carrier_ok(np->dev))
1244 off = 5 * HZ;
1245 else
1246 off = 1 * HZ;
1247 np->timer.expires = jiffies + off;
1248
1249 add_timer(&np->timer);
1250}
1251
1252static const struct niu_phy_ops phy_ops_10g_fiber_niu = {
1253 .serdes_init = serdes_init_niu,
1254 .xcvr_init = xcvr_init_10g,
1255 .link_status = link_status_10g,
1256};
1257
1258static const struct niu_phy_ops phy_ops_10g_fiber = {
1259 .serdes_init = serdes_init_10g,
1260 .xcvr_init = xcvr_init_10g,
1261 .link_status = link_status_10g,
1262};
1263
1264static const struct niu_phy_ops phy_ops_10g_copper = {
1265 .serdes_init = serdes_init_10g,
1266 .link_status = link_status_10g, /* XXX */
1267};
1268
1269static const struct niu_phy_ops phy_ops_1g_fiber = {
1270 .serdes_init = serdes_init_1g,
1271 .xcvr_init = xcvr_init_1g,
1272 .link_status = link_status_1g,
1273};
1274
1275static const struct niu_phy_ops phy_ops_1g_copper = {
1276 .xcvr_init = xcvr_init_1g,
1277 .link_status = link_status_1g,
1278};
1279
1280struct niu_phy_template {
1281 const struct niu_phy_ops *ops;
1282 u32 phy_addr_base;
1283};
1284
1285static const struct niu_phy_template phy_template_niu = {
1286 .ops = &phy_ops_10g_fiber_niu,
1287 .phy_addr_base = 16,
1288};
1289
1290static const struct niu_phy_template phy_template_10g_fiber = {
1291 .ops = &phy_ops_10g_fiber,
1292 .phy_addr_base = 8,
1293};
1294
1295static const struct niu_phy_template phy_template_10g_copper = {
1296 .ops = &phy_ops_10g_copper,
1297 .phy_addr_base = 10,
1298};
1299
1300static const struct niu_phy_template phy_template_1g_fiber = {
1301 .ops = &phy_ops_1g_fiber,
1302 .phy_addr_base = 0,
1303};
1304
1305static const struct niu_phy_template phy_template_1g_copper = {
1306 .ops = &phy_ops_1g_copper,
1307 .phy_addr_base = 0,
1308};
1309
1310static int niu_determine_phy_disposition(struct niu *np)
1311{
1312 struct niu_parent *parent = np->parent;
1313 u8 plat_type = parent->plat_type;
1314 const struct niu_phy_template *tp;
1315 u32 phy_addr_off = 0;
1316
1317 if (plat_type == PLAT_TYPE_NIU) {
1318 tp = &phy_template_niu;
1319 phy_addr_off += np->port;
1320 } else {
1321 switch (np->flags & (NIU_FLAGS_10G | NIU_FLAGS_FIBER)) {
1322 case 0:
1323 /* 1G copper */
1324 tp = &phy_template_1g_copper;
1325 if (plat_type == PLAT_TYPE_VF_P0)
1326 phy_addr_off = 10;
1327 else if (plat_type == PLAT_TYPE_VF_P1)
1328 phy_addr_off = 26;
1329
1330 phy_addr_off += (np->port ^ 0x3);
1331 break;
1332
1333 case NIU_FLAGS_10G:
1334 /* 10G copper */
1335 tp = &phy_template_1g_copper;
1336 break;
1337
1338 case NIU_FLAGS_FIBER:
1339 /* 1G fiber */
1340 tp = &phy_template_1g_fiber;
1341 break;
1342
1343 case NIU_FLAGS_10G | NIU_FLAGS_FIBER:
1344 /* 10G fiber */
1345 tp = &phy_template_10g_fiber;
1346 if (plat_type == PLAT_TYPE_VF_P0 ||
1347 plat_type == PLAT_TYPE_VF_P1)
1348 phy_addr_off = 8;
1349 phy_addr_off += np->port;
1350 break;
1351
1352 default:
1353 return -EINVAL;
1354 }
1355 }
1356
1357 np->phy_ops = tp->ops;
1358 np->phy_addr = tp->phy_addr_base + phy_addr_off;
1359
1360 return 0;
1361}
1362
1363static int niu_init_link(struct niu *np)
1364{
1365 struct niu_parent *parent = np->parent;
1366 int err, ignore;
1367
1368 if (parent->plat_type == PLAT_TYPE_NIU) {
1369 err = niu_xcvr_init(np);
1370 if (err)
1371 return err;
1372 msleep(200);
1373 }
1374 err = niu_serdes_init(np);
1375 if (err)
1376 return err;
1377 msleep(200);
1378 err = niu_xcvr_init(np);
1379 if (!err)
1380 niu_link_status(np, &ignore);
1381 return 0;
1382}
1383
1384static void niu_set_primary_mac(struct niu *np, unsigned char *addr)
1385{
1386 u16 reg0 = addr[4] << 8 | addr[5];
1387 u16 reg1 = addr[2] << 8 | addr[3];
1388 u16 reg2 = addr[0] << 8 | addr[1];
1389
1390 if (np->flags & NIU_FLAGS_XMAC) {
1391 nw64_mac(XMAC_ADDR0, reg0);
1392 nw64_mac(XMAC_ADDR1, reg1);
1393 nw64_mac(XMAC_ADDR2, reg2);
1394 } else {
1395 nw64_mac(BMAC_ADDR0, reg0);
1396 nw64_mac(BMAC_ADDR1, reg1);
1397 nw64_mac(BMAC_ADDR2, reg2);
1398 }
1399}
1400
1401static int niu_num_alt_addr(struct niu *np)
1402{
1403 if (np->flags & NIU_FLAGS_XMAC)
1404 return XMAC_NUM_ALT_ADDR;
1405 else
1406 return BMAC_NUM_ALT_ADDR;
1407}
1408
1409static int niu_set_alt_mac(struct niu *np, int index, unsigned char *addr)
1410{
1411 u16 reg0 = addr[4] << 8 | addr[5];
1412 u16 reg1 = addr[2] << 8 | addr[3];
1413 u16 reg2 = addr[0] << 8 | addr[1];
1414
1415 if (index >= niu_num_alt_addr(np))
1416 return -EINVAL;
1417
1418 if (np->flags & NIU_FLAGS_XMAC) {
1419 nw64_mac(XMAC_ALT_ADDR0(index), reg0);
1420 nw64_mac(XMAC_ALT_ADDR1(index), reg1);
1421 nw64_mac(XMAC_ALT_ADDR2(index), reg2);
1422 } else {
1423 nw64_mac(BMAC_ALT_ADDR0(index), reg0);
1424 nw64_mac(BMAC_ALT_ADDR1(index), reg1);
1425 nw64_mac(BMAC_ALT_ADDR2(index), reg2);
1426 }
1427
1428 return 0;
1429}
1430
1431static int niu_enable_alt_mac(struct niu *np, int index, int on)
1432{
1433 unsigned long reg;
1434 u64 val, mask;
1435
1436 if (index >= niu_num_alt_addr(np))
1437 return -EINVAL;
1438
1439 if (np->flags & NIU_FLAGS_XMAC)
1440 reg = XMAC_ADDR_CMPEN;
1441 else
1442 reg = BMAC_ADDR_CMPEN;
1443
1444 mask = 1 << index;
1445
1446 val = nr64_mac(reg);
1447 if (on)
1448 val |= mask;
1449 else
1450 val &= ~mask;
1451 nw64_mac(reg, val);
1452
1453 return 0;
1454}
1455
1456static void __set_rdc_table_num_hw(struct niu *np, unsigned long reg,
1457 int num, int mac_pref)
1458{
1459 u64 val = nr64_mac(reg);
1460 val &= ~(HOST_INFO_MACRDCTBLN | HOST_INFO_MPR);
1461 val |= num;
1462 if (mac_pref)
1463 val |= HOST_INFO_MPR;
1464 nw64_mac(reg, val);
1465}
1466
1467static int __set_rdc_table_num(struct niu *np,
1468 int xmac_index, int bmac_index,
1469 int rdc_table_num, int mac_pref)
1470{
1471 unsigned long reg;
1472
1473 if (rdc_table_num & ~HOST_INFO_MACRDCTBLN)
1474 return -EINVAL;
1475 if (np->flags & NIU_FLAGS_XMAC)
1476 reg = XMAC_HOST_INFO(xmac_index);
1477 else
1478 reg = BMAC_HOST_INFO(bmac_index);
1479 __set_rdc_table_num_hw(np, reg, rdc_table_num, mac_pref);
1480 return 0;
1481}
1482
1483static int niu_set_primary_mac_rdc_table(struct niu *np, int table_num,
1484 int mac_pref)
1485{
1486 return __set_rdc_table_num(np, 17, 0, table_num, mac_pref);
1487}
1488
1489static int niu_set_multicast_mac_rdc_table(struct niu *np, int table_num,
1490 int mac_pref)
1491{
1492 return __set_rdc_table_num(np, 16, 8, table_num, mac_pref);
1493}
1494
1495static int niu_set_alt_mac_rdc_table(struct niu *np, int idx,
1496 int table_num, int mac_pref)
1497{
1498 if (idx >= niu_num_alt_addr(np))
1499 return -EINVAL;
1500 return __set_rdc_table_num(np, idx, idx + 1, table_num, mac_pref);
1501}
1502
1503static u64 vlan_entry_set_parity(u64 reg_val)
1504{
1505 u64 port01_mask;
1506 u64 port23_mask;
1507
1508 port01_mask = 0x00ff;
1509 port23_mask = 0xff00;
1510
1511 if (hweight64(reg_val & port01_mask) & 1)
1512 reg_val |= ENET_VLAN_TBL_PARITY0;
1513 else
1514 reg_val &= ~ENET_VLAN_TBL_PARITY0;
1515
1516 if (hweight64(reg_val & port23_mask) & 1)
1517 reg_val |= ENET_VLAN_TBL_PARITY1;
1518 else
1519 reg_val &= ~ENET_VLAN_TBL_PARITY1;
1520
1521 return reg_val;
1522}
1523
1524static void vlan_tbl_write(struct niu *np, unsigned long index,
1525 int port, int vpr, int rdc_table)
1526{
1527 u64 reg_val = nr64(ENET_VLAN_TBL(index));
1528
1529 reg_val &= ~((ENET_VLAN_TBL_VPR |
1530 ENET_VLAN_TBL_VLANRDCTBLN) <<
1531 ENET_VLAN_TBL_SHIFT(port));
1532 if (vpr)
1533 reg_val |= (ENET_VLAN_TBL_VPR <<
1534 ENET_VLAN_TBL_SHIFT(port));
1535 reg_val |= (rdc_table << ENET_VLAN_TBL_SHIFT(port));
1536
1537 reg_val = vlan_entry_set_parity(reg_val);
1538
1539 nw64(ENET_VLAN_TBL(index), reg_val);
1540}
1541
1542static void vlan_tbl_clear(struct niu *np)
1543{
1544 int i;
1545
1546 for (i = 0; i < ENET_VLAN_TBL_NUM_ENTRIES; i++)
1547 nw64(ENET_VLAN_TBL(i), 0);
1548}
1549
1550static int tcam_wait_bit(struct niu *np, u64 bit)
1551{
1552 int limit = 1000;
1553
1554 while (--limit > 0) {
1555 if (nr64(TCAM_CTL) & bit)
1556 break;
1557 udelay(1);
1558 }
1559 if (limit < 0)
1560 return -ENODEV;
1561
1562 return 0;
1563}
1564
1565static int tcam_flush(struct niu *np, int index)
1566{
1567 nw64(TCAM_KEY_0, 0x00);
1568 nw64(TCAM_KEY_MASK_0, 0xff);
1569 nw64(TCAM_CTL, (TCAM_CTL_RWC_TCAM_WRITE | index));
1570
1571 return tcam_wait_bit(np, TCAM_CTL_STAT);
1572}
1573
1574#if 0
1575static int tcam_read(struct niu *np, int index,
1576 u64 *key, u64 *mask)
1577{
1578 int err;
1579
1580 nw64(TCAM_CTL, (TCAM_CTL_RWC_TCAM_READ | index));
1581 err = tcam_wait_bit(np, TCAM_CTL_STAT);
1582 if (!err) {
1583 key[0] = nr64(TCAM_KEY_0);
1584 key[1] = nr64(TCAM_KEY_1);
1585 key[2] = nr64(TCAM_KEY_2);
1586 key[3] = nr64(TCAM_KEY_3);
1587 mask[0] = nr64(TCAM_KEY_MASK_0);
1588 mask[1] = nr64(TCAM_KEY_MASK_1);
1589 mask[2] = nr64(TCAM_KEY_MASK_2);
1590 mask[3] = nr64(TCAM_KEY_MASK_3);
1591 }
1592 return err;
1593}
1594#endif
1595
1596static int tcam_write(struct niu *np, int index,
1597 u64 *key, u64 *mask)
1598{
1599 nw64(TCAM_KEY_0, key[0]);
1600 nw64(TCAM_KEY_1, key[1]);
1601 nw64(TCAM_KEY_2, key[2]);
1602 nw64(TCAM_KEY_3, key[3]);
1603 nw64(TCAM_KEY_MASK_0, mask[0]);
1604 nw64(TCAM_KEY_MASK_1, mask[1]);
1605 nw64(TCAM_KEY_MASK_2, mask[2]);
1606 nw64(TCAM_KEY_MASK_3, mask[3]);
1607 nw64(TCAM_CTL, (TCAM_CTL_RWC_TCAM_WRITE | index));
1608
1609 return tcam_wait_bit(np, TCAM_CTL_STAT);
1610}
1611
1612#if 0
1613static int tcam_assoc_read(struct niu *np, int index, u64 *data)
1614{
1615 int err;
1616
1617 nw64(TCAM_CTL, (TCAM_CTL_RWC_RAM_READ | index));
1618 err = tcam_wait_bit(np, TCAM_CTL_STAT);
1619 if (!err)
1620 *data = nr64(TCAM_KEY_1);
1621
1622 return err;
1623}
1624#endif
1625
1626static int tcam_assoc_write(struct niu *np, int index, u64 assoc_data)
1627{
1628 nw64(TCAM_KEY_1, assoc_data);
1629 nw64(TCAM_CTL, (TCAM_CTL_RWC_RAM_WRITE | index));
1630
1631 return tcam_wait_bit(np, TCAM_CTL_STAT);
1632}
1633
1634static void tcam_enable(struct niu *np, int on)
1635{
1636 u64 val = nr64(FFLP_CFG_1);
1637
1638 if (on)
1639 val &= ~FFLP_CFG_1_TCAM_DIS;
1640 else
1641 val |= FFLP_CFG_1_TCAM_DIS;
1642 nw64(FFLP_CFG_1, val);
1643}
1644
1645static void tcam_set_lat_and_ratio(struct niu *np, u64 latency, u64 ratio)
1646{
1647 u64 val = nr64(FFLP_CFG_1);
1648
1649 val &= ~(FFLP_CFG_1_FFLPINITDONE |
1650 FFLP_CFG_1_CAMLAT |
1651 FFLP_CFG_1_CAMRATIO);
1652 val |= (latency << FFLP_CFG_1_CAMLAT_SHIFT);
1653 val |= (ratio << FFLP_CFG_1_CAMRATIO_SHIFT);
1654 nw64(FFLP_CFG_1, val);
1655
1656 val = nr64(FFLP_CFG_1);
1657 val |= FFLP_CFG_1_FFLPINITDONE;
1658 nw64(FFLP_CFG_1, val);
1659}
1660
1661static int tcam_user_eth_class_enable(struct niu *np, unsigned long class,
1662 int on)
1663{
1664 unsigned long reg;
1665 u64 val;
1666
1667 if (class < CLASS_CODE_ETHERTYPE1 ||
1668 class > CLASS_CODE_ETHERTYPE2)
1669 return -EINVAL;
1670
1671 reg = L2_CLS(class - CLASS_CODE_ETHERTYPE1);
1672 val = nr64(reg);
1673 if (on)
1674 val |= L2_CLS_VLD;
1675 else
1676 val &= ~L2_CLS_VLD;
1677 nw64(reg, val);
1678
1679 return 0;
1680}
1681
1682#if 0
1683static int tcam_user_eth_class_set(struct niu *np, unsigned long class,
1684 u64 ether_type)
1685{
1686 unsigned long reg;
1687 u64 val;
1688
1689 if (class < CLASS_CODE_ETHERTYPE1 ||
1690 class > CLASS_CODE_ETHERTYPE2 ||
1691 (ether_type & ~(u64)0xffff) != 0)
1692 return -EINVAL;
1693
1694 reg = L2_CLS(class - CLASS_CODE_ETHERTYPE1);
1695 val = nr64(reg);
1696 val &= ~L2_CLS_ETYPE;
1697 val |= (ether_type << L2_CLS_ETYPE_SHIFT);
1698 nw64(reg, val);
1699
1700 return 0;
1701}
1702#endif
1703
1704static int tcam_user_ip_class_enable(struct niu *np, unsigned long class,
1705 int on)
1706{
1707 unsigned long reg;
1708 u64 val;
1709
1710 if (class < CLASS_CODE_USER_PROG1 ||
1711 class > CLASS_CODE_USER_PROG4)
1712 return -EINVAL;
1713
1714 reg = L3_CLS(class - CLASS_CODE_USER_PROG1);
1715 val = nr64(reg);
1716 if (on)
1717 val |= L3_CLS_VALID;
1718 else
1719 val &= ~L3_CLS_VALID;
1720 nw64(reg, val);
1721
1722 return 0;
1723}
1724
1725#if 0
1726static int tcam_user_ip_class_set(struct niu *np, unsigned long class,
1727 int ipv6, u64 protocol_id,
1728 u64 tos_mask, u64 tos_val)
1729{
1730 unsigned long reg;
1731 u64 val;
1732
1733 if (class < CLASS_CODE_USER_PROG1 ||
1734 class > CLASS_CODE_USER_PROG4 ||
1735 (protocol_id & ~(u64)0xff) != 0 ||
1736 (tos_mask & ~(u64)0xff) != 0 ||
1737 (tos_val & ~(u64)0xff) != 0)
1738 return -EINVAL;
1739
1740 reg = L3_CLS(class - CLASS_CODE_USER_PROG1);
1741 val = nr64(reg);
1742 val &= ~(L3_CLS_IPVER | L3_CLS_PID |
1743 L3_CLS_TOSMASK | L3_CLS_TOS);
1744 if (ipv6)
1745 val |= L3_CLS_IPVER;
1746 val |= (protocol_id << L3_CLS_PID_SHIFT);
1747 val |= (tos_mask << L3_CLS_TOSMASK_SHIFT);
1748 val |= (tos_val << L3_CLS_TOS_SHIFT);
1749 nw64(reg, val);
1750
1751 return 0;
1752}
1753#endif
1754
1755static int tcam_early_init(struct niu *np)
1756{
1757 unsigned long i;
1758 int err;
1759
1760 tcam_enable(np, 0);
1761 tcam_set_lat_and_ratio(np,
1762 DEFAULT_TCAM_LATENCY,
1763 DEFAULT_TCAM_ACCESS_RATIO);
1764 for (i = CLASS_CODE_ETHERTYPE1; i <= CLASS_CODE_ETHERTYPE2; i++) {
1765 err = tcam_user_eth_class_enable(np, i, 0);
1766 if (err)
1767 return err;
1768 }
1769 for (i = CLASS_CODE_USER_PROG1; i <= CLASS_CODE_USER_PROG4; i++) {
1770 err = tcam_user_ip_class_enable(np, i, 0);
1771 if (err)
1772 return err;
1773 }
1774
1775 return 0;
1776}
1777
1778static int tcam_flush_all(struct niu *np)
1779{
1780 unsigned long i;
1781
1782 for (i = 0; i < np->parent->tcam_num_entries; i++) {
1783 int err = tcam_flush(np, i);
1784 if (err)
1785 return err;
1786 }
1787 return 0;
1788}
1789
1790static u64 hash_addr_regval(unsigned long index, unsigned long num_entries)
1791{
1792 return ((u64)index | (num_entries == 1 ?
1793 HASH_TBL_ADDR_AUTOINC : 0));
1794}
1795
1796#if 0
1797static int hash_read(struct niu *np, unsigned long partition,
1798 unsigned long index, unsigned long num_entries,
1799 u64 *data)
1800{
1801 u64 val = hash_addr_regval(index, num_entries);
1802 unsigned long i;
1803
1804 if (partition >= FCRAM_NUM_PARTITIONS ||
1805 index + num_entries > FCRAM_SIZE)
1806 return -EINVAL;
1807
1808 nw64(HASH_TBL_ADDR(partition), val);
1809 for (i = 0; i < num_entries; i++)
1810 data[i] = nr64(HASH_TBL_DATA(partition));
1811
1812 return 0;
1813}
1814#endif
1815
1816static int hash_write(struct niu *np, unsigned long partition,
1817 unsigned long index, unsigned long num_entries,
1818 u64 *data)
1819{
1820 u64 val = hash_addr_regval(index, num_entries);
1821 unsigned long i;
1822
1823 if (partition >= FCRAM_NUM_PARTITIONS ||
1824 index + (num_entries * 8) > FCRAM_SIZE)
1825 return -EINVAL;
1826
1827 nw64(HASH_TBL_ADDR(partition), val);
1828 for (i = 0; i < num_entries; i++)
1829 nw64(HASH_TBL_DATA(partition), data[i]);
1830
1831 return 0;
1832}
1833
1834static void fflp_reset(struct niu *np)
1835{
1836 u64 val;
1837
1838 nw64(FFLP_CFG_1, FFLP_CFG_1_PIO_FIO_RST);
1839 udelay(10);
1840 nw64(FFLP_CFG_1, 0);
1841
1842 val = FFLP_CFG_1_FCRAMOUTDR_NORMAL | FFLP_CFG_1_FFLPINITDONE;
1843 nw64(FFLP_CFG_1, val);
1844}
1845
1846static void fflp_set_timings(struct niu *np)
1847{
1848 u64 val = nr64(FFLP_CFG_1);
1849
1850 val &= ~FFLP_CFG_1_FFLPINITDONE;
1851 val |= (DEFAULT_FCRAMRATIO << FFLP_CFG_1_FCRAMRATIO_SHIFT);
1852 nw64(FFLP_CFG_1, val);
1853
1854 val = nr64(FFLP_CFG_1);
1855 val |= FFLP_CFG_1_FFLPINITDONE;
1856 nw64(FFLP_CFG_1, val);
1857
1858 val = nr64(FCRAM_REF_TMR);
1859 val &= ~(FCRAM_REF_TMR_MAX | FCRAM_REF_TMR_MIN);
1860 val |= (DEFAULT_FCRAM_REFRESH_MAX << FCRAM_REF_TMR_MAX_SHIFT);
1861 val |= (DEFAULT_FCRAM_REFRESH_MIN << FCRAM_REF_TMR_MIN_SHIFT);
1862 nw64(FCRAM_REF_TMR, val);
1863}
1864
1865static int fflp_set_partition(struct niu *np, u64 partition,
1866 u64 mask, u64 base, int enable)
1867{
1868 unsigned long reg;
1869 u64 val;
1870
1871 if (partition >= FCRAM_NUM_PARTITIONS ||
1872 (mask & ~(u64)0x1f) != 0 ||
1873 (base & ~(u64)0x1f) != 0)
1874 return -EINVAL;
1875
1876 reg = FLW_PRT_SEL(partition);
1877
1878 val = nr64(reg);
1879 val &= ~(FLW_PRT_SEL_EXT | FLW_PRT_SEL_MASK | FLW_PRT_SEL_BASE);
1880 val |= (mask << FLW_PRT_SEL_MASK_SHIFT);
1881 val |= (base << FLW_PRT_SEL_BASE_SHIFT);
1882 if (enable)
1883 val |= FLW_PRT_SEL_EXT;
1884 nw64(reg, val);
1885
1886 return 0;
1887}
1888
1889static int fflp_disable_all_partitions(struct niu *np)
1890{
1891 unsigned long i;
1892
1893 for (i = 0; i < FCRAM_NUM_PARTITIONS; i++) {
1894 int err = fflp_set_partition(np, 0, 0, 0, 0);
1895 if (err)
1896 return err;
1897 }
1898 return 0;
1899}
1900
1901static void fflp_llcsnap_enable(struct niu *np, int on)
1902{
1903 u64 val = nr64(FFLP_CFG_1);
1904
1905 if (on)
1906 val |= FFLP_CFG_1_LLCSNAP;
1907 else
1908 val &= ~FFLP_CFG_1_LLCSNAP;
1909 nw64(FFLP_CFG_1, val);
1910}
1911
1912static void fflp_errors_enable(struct niu *np, int on)
1913{
1914 u64 val = nr64(FFLP_CFG_1);
1915
1916 if (on)
1917 val &= ~FFLP_CFG_1_ERRORDIS;
1918 else
1919 val |= FFLP_CFG_1_ERRORDIS;
1920 nw64(FFLP_CFG_1, val);
1921}
1922
1923static int fflp_hash_clear(struct niu *np)
1924{
1925 struct fcram_hash_ipv4 ent;
1926 unsigned long i;
1927
1928 /* IPV4 hash entry with valid bit clear, rest is don't care. */
1929 memset(&ent, 0, sizeof(ent));
1930 ent.header = HASH_HEADER_EXT;
1931
1932 for (i = 0; i < FCRAM_SIZE; i += sizeof(ent)) {
1933 int err = hash_write(np, 0, i, 1, (u64 *) &ent);
1934 if (err)
1935 return err;
1936 }
1937 return 0;
1938}
1939
1940static int fflp_early_init(struct niu *np)
1941{
1942 struct niu_parent *parent;
1943 unsigned long flags;
1944 int err;
1945
1946 niu_lock_parent(np, flags);
1947
1948 parent = np->parent;
1949 err = 0;
1950 if (!(parent->flags & PARENT_FLGS_CLS_HWINIT)) {
1951 niudbg(PROBE, "fflp_early_init: Initting hw on port %u\n",
1952 np->port);
1953 if (np->parent->plat_type != PLAT_TYPE_NIU) {
1954 fflp_reset(np);
1955 fflp_set_timings(np);
1956 err = fflp_disable_all_partitions(np);
1957 if (err) {
1958 niudbg(PROBE, "fflp_disable_all_partitions "
1959 "failed, err=%d\n", err);
1960 goto out;
1961 }
1962 }
1963
1964 err = tcam_early_init(np);
1965 if (err) {
1966 niudbg(PROBE, "tcam_early_init failed, err=%d\n",
1967 err);
1968 goto out;
1969 }
1970 fflp_llcsnap_enable(np, 1);
1971 fflp_errors_enable(np, 0);
1972 nw64(H1POLY, 0);
1973 nw64(H2POLY, 0);
1974
1975 err = tcam_flush_all(np);
1976 if (err) {
1977 niudbg(PROBE, "tcam_flush_all failed, err=%d\n",
1978 err);
1979 goto out;
1980 }
1981 if (np->parent->plat_type != PLAT_TYPE_NIU) {
1982 err = fflp_hash_clear(np);
1983 if (err) {
1984 niudbg(PROBE, "fflp_hash_clear failed, "
1985 "err=%d\n", err);
1986 goto out;
1987 }
1988 }
1989
1990 vlan_tbl_clear(np);
1991
1992 niudbg(PROBE, "fflp_early_init: Success\n");
1993 parent->flags |= PARENT_FLGS_CLS_HWINIT;
1994 }
1995out:
1996 niu_unlock_parent(np, flags);
1997 return err;
1998}
1999
2000static int niu_set_flow_key(struct niu *np, unsigned long class_code, u64 key)
2001{
2002 if (class_code < CLASS_CODE_USER_PROG1 ||
2003 class_code > CLASS_CODE_SCTP_IPV6)
2004 return -EINVAL;
2005
2006 nw64(FLOW_KEY(class_code - CLASS_CODE_USER_PROG1), key);
2007 return 0;
2008}
2009
2010static int niu_set_tcam_key(struct niu *np, unsigned long class_code, u64 key)
2011{
2012 if (class_code < CLASS_CODE_USER_PROG1 ||
2013 class_code > CLASS_CODE_SCTP_IPV6)
2014 return -EINVAL;
2015
2016 nw64(TCAM_KEY(class_code - CLASS_CODE_USER_PROG1), key);
2017 return 0;
2018}
2019
2020static void niu_rx_skb_append(struct sk_buff *skb, struct page *page,
2021 u32 offset, u32 size)
2022{
2023 int i = skb_shinfo(skb)->nr_frags;
2024 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
2025
2026 frag->page = page;
2027 frag->page_offset = offset;
2028 frag->size = size;
2029
2030 skb->len += size;
2031 skb->data_len += size;
2032 skb->truesize += size;
2033
2034 skb_shinfo(skb)->nr_frags = i + 1;
2035}
2036
2037static unsigned int niu_hash_rxaddr(struct rx_ring_info *rp, u64 a)
2038{
2039 a >>= PAGE_SHIFT;
2040 a ^= (a >> ilog2(MAX_RBR_RING_SIZE));
2041
2042 return (a & (MAX_RBR_RING_SIZE - 1));
2043}
2044
2045static struct page *niu_find_rxpage(struct rx_ring_info *rp, u64 addr,
2046 struct page ***link)
2047{
2048 unsigned int h = niu_hash_rxaddr(rp, addr);
2049 struct page *p, **pp;
2050
2051 addr &= PAGE_MASK;
2052 pp = &rp->rxhash[h];
2053 for (; (p = *pp) != NULL; pp = (struct page **) &p->mapping) {
2054 if (p->index == addr) {
2055 *link = pp;
2056 break;
2057 }
2058 }
2059
2060 return p;
2061}
2062
2063static void niu_hash_page(struct rx_ring_info *rp, struct page *page, u64 base)
2064{
2065 unsigned int h = niu_hash_rxaddr(rp, base);
2066
2067 page->index = base;
2068 page->mapping = (struct address_space *) rp->rxhash[h];
2069 rp->rxhash[h] = page;
2070}
2071
2072static int niu_rbr_add_page(struct niu *np, struct rx_ring_info *rp,
2073 gfp_t mask, int start_index)
2074{
2075 struct page *page;
2076 u64 addr;
2077 int i;
2078
2079 page = alloc_page(mask);
2080 if (!page)
2081 return -ENOMEM;
2082
2083 addr = np->ops->map_page(np->device, page, 0,
2084 PAGE_SIZE, DMA_FROM_DEVICE);
2085
2086 niu_hash_page(rp, page, addr);
2087 if (rp->rbr_blocks_per_page > 1)
2088 atomic_add(rp->rbr_blocks_per_page - 1,
2089 &compound_head(page)->_count);
2090
2091 for (i = 0; i < rp->rbr_blocks_per_page; i++) {
2092 __le32 *rbr = &rp->rbr[start_index + i];
2093
2094 *rbr = cpu_to_le32(addr >> RBR_DESCR_ADDR_SHIFT);
2095 addr += rp->rbr_block_size;
2096 }
2097
2098 return 0;
2099}
2100
2101static void niu_rbr_refill(struct niu *np, struct rx_ring_info *rp, gfp_t mask)
2102{
2103 int index = rp->rbr_index;
2104
2105 rp->rbr_pending++;
2106 if ((rp->rbr_pending % rp->rbr_blocks_per_page) == 0) {
2107 int err = niu_rbr_add_page(np, rp, mask, index);
2108
2109 if (unlikely(err)) {
2110 rp->rbr_pending--;
2111 return;
2112 }
2113
2114 rp->rbr_index += rp->rbr_blocks_per_page;
2115 BUG_ON(rp->rbr_index > rp->rbr_table_size);
2116 if (rp->rbr_index == rp->rbr_table_size)
2117 rp->rbr_index = 0;
2118
2119 if (rp->rbr_pending >= rp->rbr_kick_thresh) {
2120 nw64(RBR_KICK(rp->rx_channel), rp->rbr_pending);
2121 rp->rbr_pending = 0;
2122 }
2123 }
2124}
2125
2126static int niu_rx_pkt_ignore(struct niu *np, struct rx_ring_info *rp)
2127{
2128 unsigned int index = rp->rcr_index;
2129 int num_rcr = 0;
2130
2131 rp->rx_dropped++;
2132 while (1) {
2133 struct page *page, **link;
2134 u64 addr, val;
2135 u32 rcr_size;
2136
2137 num_rcr++;
2138
2139 val = le64_to_cpup(&rp->rcr[index]);
2140 addr = (val & RCR_ENTRY_PKT_BUF_ADDR) <<
2141 RCR_ENTRY_PKT_BUF_ADDR_SHIFT;
2142 page = niu_find_rxpage(rp, addr, &link);
2143
2144 rcr_size = rp->rbr_sizes[(val & RCR_ENTRY_PKTBUFSZ) >>
2145 RCR_ENTRY_PKTBUFSZ_SHIFT];
2146 if ((page->index + PAGE_SIZE) - rcr_size == addr) {
2147 *link = (struct page *) page->mapping;
2148 np->ops->unmap_page(np->device, page->index,
2149 PAGE_SIZE, DMA_FROM_DEVICE);
2150 page->index = 0;
2151 page->mapping = NULL;
2152 __free_page(page);
2153 rp->rbr_refill_pending++;
2154 }
2155
2156 index = NEXT_RCR(rp, index);
2157 if (!(val & RCR_ENTRY_MULTI))
2158 break;
2159
2160 }
2161 rp->rcr_index = index;
2162
2163 return num_rcr;
2164}
2165
2166static int niu_process_rx_pkt(struct niu *np, struct rx_ring_info *rp)
2167{
2168 unsigned int index = rp->rcr_index;
2169 struct sk_buff *skb;
2170 int len, num_rcr;
2171
2172 skb = netdev_alloc_skb(np->dev, RX_SKB_ALLOC_SIZE);
2173 if (unlikely(!skb))
2174 return niu_rx_pkt_ignore(np, rp);
2175
2176 num_rcr = 0;
2177 while (1) {
2178 struct page *page, **link;
2179 u32 rcr_size, append_size;
2180 u64 addr, val, off;
2181
2182 num_rcr++;
2183
2184 val = le64_to_cpup(&rp->rcr[index]);
2185
2186 len = (val & RCR_ENTRY_L2_LEN) >>
2187 RCR_ENTRY_L2_LEN_SHIFT;
2188 len -= ETH_FCS_LEN;
2189
2190 addr = (val & RCR_ENTRY_PKT_BUF_ADDR) <<
2191 RCR_ENTRY_PKT_BUF_ADDR_SHIFT;
2192 page = niu_find_rxpage(rp, addr, &link);
2193
2194 rcr_size = rp->rbr_sizes[(val & RCR_ENTRY_PKTBUFSZ) >>
2195 RCR_ENTRY_PKTBUFSZ_SHIFT];
2196
2197 off = addr & ~PAGE_MASK;
2198 append_size = rcr_size;
2199 if (num_rcr == 1) {
2200 int ptype;
2201
2202 off += 2;
2203 append_size -= 2;
2204
2205 ptype = (val >> RCR_ENTRY_PKT_TYPE_SHIFT);
2206 if ((ptype == RCR_PKT_TYPE_TCP ||
2207 ptype == RCR_PKT_TYPE_UDP) &&
2208 !(val & (RCR_ENTRY_NOPORT |
2209 RCR_ENTRY_ERROR)))
2210 skb->ip_summed = CHECKSUM_UNNECESSARY;
2211 else
2212 skb->ip_summed = CHECKSUM_NONE;
2213 }
2214 if (!(val & RCR_ENTRY_MULTI))
2215 append_size = len - skb->len;
2216
2217 niu_rx_skb_append(skb, page, off, append_size);
2218 if ((page->index + rp->rbr_block_size) - rcr_size == addr) {
2219 *link = (struct page *) page->mapping;
2220 np->ops->unmap_page(np->device, page->index,
2221 PAGE_SIZE, DMA_FROM_DEVICE);
2222 page->index = 0;
2223 page->mapping = NULL;
2224 rp->rbr_refill_pending++;
2225 } else
2226 get_page(page);
2227
2228 index = NEXT_RCR(rp, index);
2229 if (!(val & RCR_ENTRY_MULTI))
2230 break;
2231
2232 }
2233 rp->rcr_index = index;
2234
2235 skb_reserve(skb, NET_IP_ALIGN);
2236 __pskb_pull_tail(skb, min(len, NIU_RXPULL_MAX));
2237
2238 rp->rx_packets++;
2239 rp->rx_bytes += skb->len;
2240
2241 skb->protocol = eth_type_trans(skb, np->dev);
2242 netif_receive_skb(skb);
2243
David S. Miller792dd902008-01-04 23:52:06 -0800[diff] [blame^]2244 np->dev->last_rx = jiffies;
2245
David S. Millera3138df2007-10-09 01:54:01 -0700[diff] [blame]2246 return num_rcr;
2247}
2248
2249static int niu_rbr_fill(struct niu *np, struct rx_ring_info *rp, gfp_t mask)
2250{
2251 int blocks_per_page = rp->rbr_blocks_per_page;
2252 int err, index = rp->rbr_index;
2253
2254 err = 0;
2255 while (index < (rp->rbr_table_size - blocks_per_page)) {
2256 err = niu_rbr_add_page(np, rp, mask, index);
2257 if (err)
2258 break;
2259
2260 index += blocks_per_page;
2261 }
2262
2263 rp->rbr_index = index;
2264 return err;
2265}
2266
2267static void niu_rbr_free(struct niu *np, struct rx_ring_info *rp)
2268{
2269 int i;
2270
2271 for (i = 0; i < MAX_RBR_RING_SIZE; i++) {
2272 struct page *page;
2273
2274 page = rp->rxhash[i];
2275 while (page) {
2276 struct page *next = (struct page *) page->mapping;
2277 u64 base = page->index;
2278
2279 np->ops->unmap_page(np->device, base, PAGE_SIZE,
2280 DMA_FROM_DEVICE);
2281 page->index = 0;
2282 page->mapping = NULL;
2283
2284 __free_page(page);
2285
2286 page = next;
2287 }
2288 }
2289
2290 for (i = 0; i < rp->rbr_table_size; i++)
2291 rp->rbr[i] = cpu_to_le32(0);
2292 rp->rbr_index = 0;
2293}
2294
2295static int release_tx_packet(struct niu *np, struct tx_ring_info *rp, int idx)
2296{
2297 struct tx_buff_info *tb = &rp->tx_buffs[idx];
2298 struct sk_buff *skb = tb->skb;
2299 struct tx_pkt_hdr *tp;
2300 u64 tx_flags;
2301 int i, len;
2302
2303 tp = (struct tx_pkt_hdr *) skb->data;
2304 tx_flags = le64_to_cpup(&tp->flags);
2305
2306 rp->tx_packets++;
2307 rp->tx_bytes += (((tx_flags & TXHDR_LEN) >> TXHDR_LEN_SHIFT) -
2308 ((tx_flags & TXHDR_PAD) / 2));
2309
2310 len = skb_headlen(skb);
2311 np->ops->unmap_single(np->device, tb->mapping,
2312 len, DMA_TO_DEVICE);
2313
2314 if (le64_to_cpu(rp->descr[idx]) & TX_DESC_MARK)
2315 rp->mark_pending--;
2316
2317 tb->skb = NULL;
2318 do {
2319 idx = NEXT_TX(rp, idx);
2320 len -= MAX_TX_DESC_LEN;
2321 } while (len > 0);
2322
2323 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
2324 tb = &rp->tx_buffs[idx];
2325 BUG_ON(tb->skb != NULL);
2326 np->ops->unmap_page(np->device, tb->mapping,
2327 skb_shinfo(skb)->frags[i].size,
2328 DMA_TO_DEVICE);
2329 idx = NEXT_TX(rp, idx);
2330 }
2331
2332 dev_kfree_skb(skb);
2333
2334 return idx;
2335}
2336
2337#define NIU_TX_WAKEUP_THRESH(rp) ((rp)->pending / 4)
2338
2339static void niu_tx_work(struct niu *np, struct tx_ring_info *rp)
2340{
2341 u16 pkt_cnt, tmp;
2342 int cons;
2343 u64 cs;
2344
2345 cs = rp->tx_cs;
2346 if (unlikely(!(cs & (TX_CS_MK | TX_CS_MMK))))
2347 goto out;
2348
2349 tmp = pkt_cnt = (cs & TX_CS_PKT_CNT) >> TX_CS_PKT_CNT_SHIFT;
2350 pkt_cnt = (pkt_cnt - rp->last_pkt_cnt) &
2351 (TX_CS_PKT_CNT >> TX_CS_PKT_CNT_SHIFT);
2352
2353 rp->last_pkt_cnt = tmp;
2354
2355 cons = rp->cons;
2356
2357 niudbg(TX_DONE, "%s: niu_tx_work() pkt_cnt[%u] cons[%d]\n",
2358 np->dev->name, pkt_cnt, cons);
2359
2360 while (pkt_cnt--)
2361 cons = release_tx_packet(np, rp, cons);
2362
2363 rp->cons = cons;
2364 smp_mb();
2365
2366out:
2367 if (unlikely(netif_queue_stopped(np->dev) &&
2368 (niu_tx_avail(rp) > NIU_TX_WAKEUP_THRESH(rp)))) {
2369 netif_tx_lock(np->dev);
2370 if (netif_queue_stopped(np->dev) &&
2371 (niu_tx_avail(rp) > NIU_TX_WAKEUP_THRESH(rp)))
2372 netif_wake_queue(np->dev);
2373 netif_tx_unlock(np->dev);
2374 }
2375}
2376
2377static int niu_rx_work(struct niu *np, struct rx_ring_info *rp, int budget)
2378{
2379 int qlen, rcr_done = 0, work_done = 0;
2380 struct rxdma_mailbox *mbox = rp->mbox;
2381 u64 stat;
2382
2383#if 1
2384 stat = nr64(RX_DMA_CTL_STAT(rp->rx_channel));
2385 qlen = nr64(RCRSTAT_A(rp->rx_channel)) & RCRSTAT_A_QLEN;
2386#else
2387 stat = le64_to_cpup(&mbox->rx_dma_ctl_stat);
2388 qlen = (le64_to_cpup(&mbox->rcrstat_a) & RCRSTAT_A_QLEN);
2389#endif
2390 mbox->rx_dma_ctl_stat = 0;
2391 mbox->rcrstat_a = 0;
2392
2393 niudbg(RX_STATUS, "%s: niu_rx_work(chan[%d]), stat[%llx] qlen=%d\n",
2394 np->dev->name, rp->rx_channel, (unsigned long long) stat, qlen);
2395
2396 rcr_done = work_done = 0;
2397 qlen = min(qlen, budget);
2398 while (work_done < qlen) {
2399 rcr_done += niu_process_rx_pkt(np, rp);
2400 work_done++;
2401 }
2402
2403 if (rp->rbr_refill_pending >= rp->rbr_kick_thresh) {
2404 unsigned int i;
2405
2406 for (i = 0; i < rp->rbr_refill_pending; i++)
2407 niu_rbr_refill(np, rp, GFP_ATOMIC);
2408 rp->rbr_refill_pending = 0;
2409 }
2410
2411 stat = (RX_DMA_CTL_STAT_MEX |
2412 ((u64)work_done << RX_DMA_CTL_STAT_PKTREAD_SHIFT) |
2413 ((u64)rcr_done << RX_DMA_CTL_STAT_PTRREAD_SHIFT));
2414
2415 nw64(RX_DMA_CTL_STAT(rp->rx_channel), stat);
2416
2417 return work_done;
2418}
2419
2420static int niu_poll_core(struct niu *np, struct niu_ldg *lp, int budget)
2421{
2422 u64 v0 = lp->v0;
2423 u32 tx_vec = (v0 >> 32);
2424 u32 rx_vec = (v0 & 0xffffffff);
2425 int i, work_done = 0;
2426
2427 niudbg(INTR, "%s: niu_poll_core() v0[%016llx]\n",
2428 np->dev->name, (unsigned long long) v0);
2429
2430 for (i = 0; i < np->num_tx_rings; i++) {
2431 struct tx_ring_info *rp = &np->tx_rings[i];
2432 if (tx_vec & (1 << rp->tx_channel))
2433 niu_tx_work(np, rp);
2434 nw64(LD_IM0(LDN_TXDMA(rp->tx_channel)), 0);
2435 }
2436
2437 for (i = 0; i < np->num_rx_rings; i++) {
2438 struct rx_ring_info *rp = &np->rx_rings[i];
2439
2440 if (rx_vec & (1 << rp->rx_channel)) {
2441 int this_work_done;
2442
2443 this_work_done = niu_rx_work(np, rp,
2444 budget);
2445
2446 budget -= this_work_done;
2447 work_done += this_work_done;
2448 }
2449 nw64(LD_IM0(LDN_RXDMA(rp->rx_channel)), 0);
2450 }
2451
2452 return work_done;
2453}
2454
2455static int niu_poll(struct napi_struct *napi, int budget)
2456{
2457 struct niu_ldg *lp = container_of(napi, struct niu_ldg, napi);
2458 struct niu *np = lp->np;
2459 int work_done;
2460
2461 work_done = niu_poll_core(np, lp, budget);
2462
2463 if (work_done < budget) {
2464 netif_rx_complete(np->dev, napi);
2465 niu_ldg_rearm(np, lp, 1);
2466 }
2467 return work_done;
2468}
2469
2470static void niu_log_rxchan_errors(struct niu *np, struct rx_ring_info *rp,
2471 u64 stat)
2472{
2473 dev_err(np->device, PFX "%s: RX channel %u errors ( ",
2474 np->dev->name, rp->rx_channel);
2475
2476 if (stat & RX_DMA_CTL_STAT_RBR_TMOUT)
2477 printk("RBR_TMOUT ");
2478 if (stat & RX_DMA_CTL_STAT_RSP_CNT_ERR)
2479 printk("RSP_CNT ");
2480 if (stat & RX_DMA_CTL_STAT_BYTE_EN_BUS)
2481 printk("BYTE_EN_BUS ");
2482 if (stat & RX_DMA_CTL_STAT_RSP_DAT_ERR)
2483 printk("RSP_DAT ");
2484 if (stat & RX_DMA_CTL_STAT_RCR_ACK_ERR)
2485 printk("RCR_ACK ");
2486 if (stat & RX_DMA_CTL_STAT_RCR_SHA_PAR)
2487 printk("RCR_SHA_PAR ");
2488 if (stat & RX_DMA_CTL_STAT_RBR_PRE_PAR)
2489 printk("RBR_PRE_PAR ");
2490 if (stat & RX_DMA_CTL_STAT_CONFIG_ERR)
2491 printk("CONFIG ");
2492 if (stat & RX_DMA_CTL_STAT_RCRINCON)
2493 printk("RCRINCON ");
2494 if (stat & RX_DMA_CTL_STAT_RCRFULL)
2495 printk("RCRFULL ");
2496 if (stat & RX_DMA_CTL_STAT_RBRFULL)
2497 printk("RBRFULL ");
2498 if (stat & RX_DMA_CTL_STAT_RBRLOGPAGE)
2499 printk("RBRLOGPAGE ");
2500 if (stat & RX_DMA_CTL_STAT_CFIGLOGPAGE)
2501 printk("CFIGLOGPAGE ");
2502 if (stat & RX_DMA_CTL_STAT_DC_FIFO_ERR)
2503 printk("DC_FIDO ");
2504
2505 printk(")\n");
2506}
2507
2508static int niu_rx_error(struct niu *np, struct rx_ring_info *rp)
2509{
2510 u64 stat = nr64(RX_DMA_CTL_STAT(rp->rx_channel));
2511 int err = 0;
2512
David S. Millera3138df2007-10-09 01:54:01 -0700[diff] [blame]2513
2514 if (stat & (RX_DMA_CTL_STAT_CHAN_FATAL |
2515 RX_DMA_CTL_STAT_PORT_FATAL))
2516 err = -EINVAL;
2517
Matheos Worku406f3532008-01-04 23:48:26 -0800[diff] [blame]2518 if (err) {
2519 dev_err(np->device, PFX "%s: RX channel %u error, stat[%llx]\n",
2520 np->dev->name, rp->rx_channel,
2521 (unsigned long long) stat);
2522
2523 niu_log_rxchan_errors(np, rp, stat);
2524 }
2525
David S. Millera3138df2007-10-09 01:54:01 -0700[diff] [blame]2526 nw64(RX_DMA_CTL_STAT(rp->rx_channel),
2527 stat & RX_DMA_CTL_WRITE_CLEAR_ERRS);
2528
2529 return err;
2530}
2531
2532static void niu_log_txchan_errors(struct niu *np, struct tx_ring_info *rp,
2533 u64 cs)
2534{
2535 dev_err(np->device, PFX "%s: TX channel %u errors ( ",
2536 np->dev->name, rp->tx_channel);
2537
2538 if (cs & TX_CS_MBOX_ERR)
2539 printk("MBOX ");
2540 if (cs & TX_CS_PKT_SIZE_ERR)
2541 printk("PKT_SIZE ");
2542 if (cs & TX_CS_TX_RING_OFLOW)
2543 printk("TX_RING_OFLOW ");
2544 if (cs & TX_CS_PREF_BUF_PAR_ERR)
2545 printk("PREF_BUF_PAR ");
2546 if (cs & TX_CS_NACK_PREF)
2547 printk("NACK_PREF ");
2548 if (cs & TX_CS_NACK_PKT_RD)
2549 printk("NACK_PKT_RD ");
2550 if (cs & TX_CS_CONF_PART_ERR)
2551 printk("CONF_PART ");
2552 if (cs & TX_CS_PKT_PRT_ERR)
2553 printk("PKT_PTR ");
2554
2555 printk(")\n");
2556}
2557
2558static int niu_tx_error(struct niu *np, struct tx_ring_info *rp)
2559{
2560 u64 cs, logh, logl;
2561
2562 cs = nr64(TX_CS(rp->tx_channel));
2563 logh = nr64(TX_RNG_ERR_LOGH(rp->tx_channel));
2564 logl = nr64(TX_RNG_ERR_LOGL(rp->tx_channel));
2565
2566 dev_err(np->device, PFX "%s: TX channel %u error, "
2567 "cs[%llx] logh[%llx] logl[%llx]\n",
2568 np->dev->name, rp->tx_channel,
2569 (unsigned long long) cs,
2570 (unsigned long long) logh,
2571 (unsigned long long) logl);
2572
2573 niu_log_txchan_errors(np, rp, cs);
2574
2575 return -ENODEV;
2576}
2577
2578static int niu_mif_interrupt(struct niu *np)
2579{
2580 u64 mif_status = nr64(MIF_STATUS);
2581 int phy_mdint = 0;
2582
2583 if (np->flags & NIU_FLAGS_XMAC) {
2584 u64 xrxmac_stat = nr64_mac(XRXMAC_STATUS);
2585
2586 if (xrxmac_stat & XRXMAC_STATUS_PHY_MDINT)
2587 phy_mdint = 1;
2588 }
2589
2590 dev_err(np->device, PFX "%s: MIF interrupt, "
2591 "stat[%llx] phy_mdint(%d)\n",
2592 np->dev->name, (unsigned long long) mif_status, phy_mdint);
2593
2594 return -ENODEV;
2595}
2596
2597static void niu_xmac_interrupt(struct niu *np)
2598{
2599 struct niu_xmac_stats *mp = &np->mac_stats.xmac;
2600 u64 val;
2601
2602 val = nr64_mac(XTXMAC_STATUS);
2603 if (val & XTXMAC_STATUS_FRAME_CNT_EXP)
2604 mp->tx_frames += TXMAC_FRM_CNT_COUNT;
2605 if (val & XTXMAC_STATUS_BYTE_CNT_EXP)
2606 mp->tx_bytes += TXMAC_BYTE_CNT_COUNT;
2607 if (val & XTXMAC_STATUS_TXFIFO_XFR_ERR)
2608 mp->tx_fifo_errors++;
2609 if (val & XTXMAC_STATUS_TXMAC_OFLOW)
2610 mp->tx_overflow_errors++;
2611 if (val & XTXMAC_STATUS_MAX_PSIZE_ERR)
2612 mp->tx_max_pkt_size_errors++;
2613 if (val & XTXMAC_STATUS_TXMAC_UFLOW)
2614 mp->tx_underflow_errors++;
2615
2616 val = nr64_mac(XRXMAC_STATUS);
2617 if (val & XRXMAC_STATUS_LCL_FLT_STATUS)
2618 mp->rx_local_faults++;
2619 if (val & XRXMAC_STATUS_RFLT_DET)
2620 mp->rx_remote_faults++;
2621 if (val & XRXMAC_STATUS_LFLT_CNT_EXP)
2622 mp->rx_link_faults += LINK_FAULT_CNT_COUNT;
2623 if (val & XRXMAC_STATUS_ALIGNERR_CNT_EXP)
2624 mp->rx_align_errors += RXMAC_ALIGN_ERR_CNT_COUNT;
2625 if (val & XRXMAC_STATUS_RXFRAG_CNT_EXP)
2626 mp->rx_frags += RXMAC_FRAG_CNT_COUNT;
2627 if (val & XRXMAC_STATUS_RXMULTF_CNT_EXP)
2628 mp->rx_mcasts += RXMAC_MC_FRM_CNT_COUNT;
2629 if (val & XRXMAC_STATUS_RXBCAST_CNT_EXP)
2630 mp->rx_bcasts += RXMAC_BC_FRM_CNT_COUNT;
2631 if (val & XRXMAC_STATUS_RXBCAST_CNT_EXP)
2632 mp->rx_bcasts += RXMAC_BC_FRM_CNT_COUNT;
2633 if (val & XRXMAC_STATUS_RXHIST1_CNT_EXP)
2634 mp->rx_hist_cnt1 += RXMAC_HIST_CNT1_COUNT;
2635 if (val & XRXMAC_STATUS_RXHIST2_CNT_EXP)
2636 mp->rx_hist_cnt2 += RXMAC_HIST_CNT2_COUNT;
2637 if (val & XRXMAC_STATUS_RXHIST3_CNT_EXP)
2638 mp->rx_hist_cnt3 += RXMAC_HIST_CNT3_COUNT;
2639 if (val & XRXMAC_STATUS_RXHIST4_CNT_EXP)
2640 mp->rx_hist_cnt4 += RXMAC_HIST_CNT4_COUNT;
2641 if (val & XRXMAC_STATUS_RXHIST5_CNT_EXP)
2642 mp->rx_hist_cnt5 += RXMAC_HIST_CNT5_COUNT;
2643 if (val & XRXMAC_STATUS_RXHIST6_CNT_EXP)
2644 mp->rx_hist_cnt6 += RXMAC_HIST_CNT6_COUNT;
2645 if (val & XRXMAC_STATUS_RXHIST7_CNT_EXP)
2646 mp->rx_hist_cnt7 += RXMAC_HIST_CNT7_COUNT;
2647 if (val & XRXMAC_STAT_MSK_RXOCTET_CNT_EXP)
2648 mp->rx_octets += RXMAC_BT_CNT_COUNT;
2649 if (val & XRXMAC_STATUS_CVIOLERR_CNT_EXP)
2650 mp->rx_code_violations += RXMAC_CD_VIO_CNT_COUNT;
2651 if (val & XRXMAC_STATUS_LENERR_CNT_EXP)
2652 mp->rx_len_errors += RXMAC_MPSZER_CNT_COUNT;
2653 if (val & XRXMAC_STATUS_CRCERR_CNT_EXP)
2654 mp->rx_crc_errors += RXMAC_CRC_ER_CNT_COUNT;
2655 if (val & XRXMAC_STATUS_RXUFLOW)
2656 mp->rx_underflows++;
2657 if (val & XRXMAC_STATUS_RXOFLOW)
2658 mp->rx_overflows++;
2659
2660 val = nr64_mac(XMAC_FC_STAT);
2661 if (val & XMAC_FC_STAT_TX_MAC_NPAUSE)
2662 mp->pause_off_state++;
2663 if (val & XMAC_FC_STAT_TX_MAC_PAUSE)
2664 mp->pause_on_state++;
2665 if (val & XMAC_FC_STAT_RX_MAC_RPAUSE)
2666 mp->pause_received++;
2667}
2668
2669static void niu_bmac_interrupt(struct niu *np)
2670{
2671 struct niu_bmac_stats *mp = &np->mac_stats.bmac;
2672 u64 val;
2673
2674 val = nr64_mac(BTXMAC_STATUS);
2675 if (val & BTXMAC_STATUS_UNDERRUN)
2676 mp->tx_underflow_errors++;
2677 if (val & BTXMAC_STATUS_MAX_PKT_ERR)
2678 mp->tx_max_pkt_size_errors++;
2679 if (val & BTXMAC_STATUS_BYTE_CNT_EXP)
2680 mp->tx_bytes += BTXMAC_BYTE_CNT_COUNT;
2681 if (val & BTXMAC_STATUS_FRAME_CNT_EXP)
2682 mp->tx_frames += BTXMAC_FRM_CNT_COUNT;
2683
2684 val = nr64_mac(BRXMAC_STATUS);
2685 if (val & BRXMAC_STATUS_OVERFLOW)
2686 mp->rx_overflows++;
2687 if (val & BRXMAC_STATUS_FRAME_CNT_EXP)
2688 mp->rx_frames += BRXMAC_FRAME_CNT_COUNT;
2689 if (val & BRXMAC_STATUS_ALIGN_ERR_EXP)
2690 mp->rx_align_errors += BRXMAC_ALIGN_ERR_CNT_COUNT;
2691 if (val & BRXMAC_STATUS_CRC_ERR_EXP)
2692 mp->rx_crc_errors += BRXMAC_ALIGN_ERR_CNT_COUNT;
2693 if (val & BRXMAC_STATUS_LEN_ERR_EXP)
2694 mp->rx_len_errors += BRXMAC_CODE_VIOL_ERR_CNT_COUNT;
2695
2696 val = nr64_mac(BMAC_CTRL_STATUS);
2697 if (val & BMAC_CTRL_STATUS_NOPAUSE)
2698 mp->pause_off_state++;
2699 if (val & BMAC_CTRL_STATUS_PAUSE)
2700 mp->pause_on_state++;
2701 if (val & BMAC_CTRL_STATUS_PAUSE_RECV)
2702 mp->pause_received++;
2703}
2704
2705static int niu_mac_interrupt(struct niu *np)
2706{
2707 if (np->flags & NIU_FLAGS_XMAC)
2708 niu_xmac_interrupt(np);
2709 else
2710 niu_bmac_interrupt(np);
2711
2712 return 0;
2713}
2714
2715static void niu_log_device_error(struct niu *np, u64 stat)
2716{
2717 dev_err(np->device, PFX "%s: Core device errors ( ",
2718 np->dev->name);
2719
2720 if (stat & SYS_ERR_MASK_META2)
2721 printk("META2 ");
2722 if (stat & SYS_ERR_MASK_META1)
2723 printk("META1 ");
2724 if (stat & SYS_ERR_MASK_PEU)
2725 printk("PEU ");
2726 if (stat & SYS_ERR_MASK_TXC)
2727 printk("TXC ");
2728 if (stat & SYS_ERR_MASK_RDMC)
2729 printk("RDMC ");
2730 if (stat & SYS_ERR_MASK_TDMC)
2731 printk("TDMC ");
2732 if (stat & SYS_ERR_MASK_ZCP)
2733 printk("ZCP ");
2734 if (stat & SYS_ERR_MASK_FFLP)
2735 printk("FFLP ");
2736 if (stat & SYS_ERR_MASK_IPP)
2737 printk("IPP ");
2738 if (stat & SYS_ERR_MASK_MAC)
2739 printk("MAC ");
2740 if (stat & SYS_ERR_MASK_SMX)
2741 printk("SMX ");
2742
2743 printk(")\n");
2744}
2745
2746static int niu_device_error(struct niu *np)
2747{
2748 u64 stat = nr64(SYS_ERR_STAT);
2749
2750 dev_err(np->device, PFX "%s: Core device error, stat[%llx]\n",
2751 np->dev->name, (unsigned long long) stat);
2752
2753 niu_log_device_error(np, stat);
2754
2755 return -ENODEV;
2756}
2757
Matheos Worku406f3532008-01-04 23:48:26 -0800[diff] [blame]2758static int niu_slowpath_interrupt(struct niu *np, struct niu_ldg *lp,
2759 u64 v0, u64 v1, u64 v2)
David S. Millera3138df2007-10-09 01:54:01 -0700[diff] [blame]2760{
Matheos Worku406f3532008-01-04 23:48:26 -0800[diff] [blame]2761
David S. Millera3138df2007-10-09 01:54:01 -0700[diff] [blame]2762 int i, err = 0;
2763
Matheos Worku406f3532008-01-04 23:48:26 -0800[diff] [blame]2764 lp->v0 = v0;
2765 lp->v1 = v1;
2766 lp->v2 = v2;
2767
David S. Millera3138df2007-10-09 01:54:01 -0700[diff] [blame]2768 if (v1 & 0x00000000ffffffffULL) {
2769 u32 rx_vec = (v1 & 0xffffffff);
2770
2771 for (i = 0; i < np->num_rx_rings; i++) {
2772 struct rx_ring_info *rp = &np->rx_rings[i];
2773
2774 if (rx_vec & (1 << rp->rx_channel)) {
2775 int r = niu_rx_error(np, rp);
Matheos Worku406f3532008-01-04 23:48:26 -0800[diff] [blame]2776 if (r) {
David S. Millera3138df2007-10-09 01:54:01 -0700[diff] [blame]2777 err = r;
Matheos Worku406f3532008-01-04 23:48:26 -0800[diff] [blame]2778 } else {
2779 if (!v0)
2780 nw64(RX_DMA_CTL_STAT(rp->rx_channel),
2781 RX_DMA_CTL_STAT_MEX);
2782 }
David S. Millera3138df2007-10-09 01:54:01 -0700[diff] [blame]2783 }
2784 }
2785 }
2786 if (v1 & 0x7fffffff00000000ULL) {
2787 u32 tx_vec = (v1 >> 32) & 0x7fffffff;
2788
2789 for (i = 0; i < np->num_tx_rings; i++) {
2790 struct tx_ring_info *rp = &np->tx_rings[i];
2791
2792 if (tx_vec & (1 << rp->tx_channel)) {
2793 int r = niu_tx_error(np, rp);
2794 if (r)
2795 err = r;
2796 }
2797 }
2798 }
2799 if ((v0 | v1) & 0x8000000000000000ULL) {
2800 int r = niu_mif_interrupt(np);
2801 if (r)
2802 err = r;
2803 }
2804 if (v2) {
2805 if (v2 & 0x01ef) {
2806 int r = niu_mac_interrupt(np);
2807 if (r)
2808 err = r;
2809 }
2810 if (v2 & 0x0210) {
2811 int r = niu_device_error(np);
2812 if (r)
2813 err = r;
2814 }
2815 }
2816
2817 if (err)
2818 niu_enable_interrupts(np, 0);
2819
Matheos Worku406f3532008-01-04 23:48:26 -0800[diff] [blame]2820 return err;
David S. Millera3138df2007-10-09 01:54:01 -0700[diff] [blame]2821}
2822
2823static void niu_rxchan_intr(struct niu *np, struct rx_ring_info *rp,
2824 int ldn)
2825{
2826 struct rxdma_mailbox *mbox = rp->mbox;
2827 u64 stat_write, stat = le64_to_cpup(&mbox->rx_dma_ctl_stat);
2828
2829 stat_write = (RX_DMA_CTL_STAT_RCRTHRES |
2830 RX_DMA_CTL_STAT_RCRTO);
2831 nw64(RX_DMA_CTL_STAT(rp->rx_channel), stat_write);
2832
2833 niudbg(INTR, "%s: rxchan_intr stat[%llx]\n",
2834 np->dev->name, (unsigned long long) stat);
2835}
2836
2837static void niu_txchan_intr(struct niu *np, struct tx_ring_info *rp,
2838 int ldn)
2839{
2840 rp->tx_cs = nr64(TX_CS(rp->tx_channel));
2841
2842 niudbg(INTR, "%s: txchan_intr cs[%llx]\n",
2843 np->dev->name, (unsigned long long) rp->tx_cs);
2844}
2845
2846static void __niu_fastpath_interrupt(struct niu *np, int ldg, u64 v0)
2847{
2848 struct niu_parent *parent = np->parent;
2849 u32 rx_vec, tx_vec;
2850 int i;
2851
2852 tx_vec = (v0 >> 32);
2853 rx_vec = (v0 & 0xffffffff);
2854
2855 for (i = 0; i < np->num_rx_rings; i++) {
2856 struct rx_ring_info *rp = &np->rx_rings[i];
2857 int ldn = LDN_RXDMA(rp->rx_channel);
2858
2859 if (parent->ldg_map[ldn] != ldg)
2860 continue;
2861
2862 nw64(LD_IM0(ldn), LD_IM0_MASK);
2863 if (rx_vec & (1 << rp->rx_channel))
2864 niu_rxchan_intr(np, rp, ldn);
2865 }
2866
2867 for (i = 0; i < np->num_tx_rings; i++) {
2868 struct tx_ring_info *rp = &np->tx_rings[i];
2869 int ldn = LDN_TXDMA(rp->tx_channel);
2870
2871 if (parent->ldg_map[ldn] != ldg)
2872 continue;
2873
2874 nw64(LD_IM0(ldn), LD_IM0_MASK);
2875 if (tx_vec & (1 << rp->tx_channel))
2876 niu_txchan_intr(np, rp, ldn);
2877 }
2878}
2879
2880static void niu_schedule_napi(struct niu *np, struct niu_ldg *lp,
2881 u64 v0, u64 v1, u64 v2)
2882{
2883 if (likely(netif_rx_schedule_prep(np->dev, &lp->napi))) {
2884 lp->v0 = v0;
2885 lp->v1 = v1;
2886 lp->v2 = v2;
2887 __niu_fastpath_interrupt(np, lp->ldg_num, v0);
2888 __netif_rx_schedule(np->dev, &lp->napi);
2889 }
2890}
2891
2892static irqreturn_t niu_interrupt(int irq, void *dev_id)
2893{
2894 struct niu_ldg *lp = dev_id;
2895 struct niu *np = lp->np;
2896 int ldg = lp->ldg_num;
2897 unsigned long flags;
2898 u64 v0, v1, v2;
2899
2900 if (netif_msg_intr(np))
2901 printk(KERN_DEBUG PFX "niu_interrupt() ldg[%p](%d) ",
2902 lp, ldg);
2903
2904 spin_lock_irqsave(&np->lock, flags);
2905
2906 v0 = nr64(LDSV0(ldg));
2907 v1 = nr64(LDSV1(ldg));
2908 v2 = nr64(LDSV2(ldg));
2909
2910 if (netif_msg_intr(np))
2911 printk("v0[%llx] v1[%llx] v2[%llx]\n",
2912 (unsigned long long) v0,
2913 (unsigned long long) v1,
2914 (unsigned long long) v2);
2915
2916 if (unlikely(!v0 && !v1 && !v2)) {
2917 spin_unlock_irqrestore(&np->lock, flags);
2918 return IRQ_NONE;
2919 }
2920
2921 if (unlikely((v0 & ((u64)1 << LDN_MIF)) || v1 || v2)) {
Matheos Worku406f3532008-01-04 23:48:26 -0800[diff] [blame]2922 int err = niu_slowpath_interrupt(np, lp, v0, v1, v2);
David S. Millera3138df2007-10-09 01:54:01 -0700[diff] [blame]2923 if (err)
2924 goto out;
2925 }
2926 if (likely(v0 & ~((u64)1 << LDN_MIF)))
2927 niu_schedule_napi(np, lp, v0, v1, v2);
2928 else
2929 niu_ldg_rearm(np, lp, 1);
2930out:
2931 spin_unlock_irqrestore(&np->lock, flags);
2932
2933 return IRQ_HANDLED;
2934}
2935
2936static void niu_free_rx_ring_info(struct niu *np, struct rx_ring_info *rp)
2937{
2938 if (rp->mbox) {
2939 np->ops->free_coherent(np->device,
2940 sizeof(struct rxdma_mailbox),
2941 rp->mbox, rp->mbox_dma);
2942 rp->mbox = NULL;
2943 }
2944 if (rp->rcr) {
2945 np->ops->free_coherent(np->device,
2946 MAX_RCR_RING_SIZE * sizeof(__le64),
2947 rp->rcr, rp->rcr_dma);
2948 rp->rcr = NULL;
2949 rp->rcr_table_size = 0;
2950 rp->rcr_index = 0;
2951 }
2952 if (rp->rbr) {
2953 niu_rbr_free(np, rp);
2954
2955 np->ops->free_coherent(np->device,
2956 MAX_RBR_RING_SIZE * sizeof(__le32),
2957 rp->rbr, rp->rbr_dma);
2958 rp->rbr = NULL;
2959 rp->rbr_table_size = 0;
2960 rp->rbr_index = 0;
2961 }
2962 kfree(rp->rxhash);
2963 rp->rxhash = NULL;
2964}
2965
2966static void niu_free_tx_ring_info(struct niu *np, struct tx_ring_info *rp)
2967{
2968 if (rp->mbox) {
2969 np->ops->free_coherent(np->device,
2970 sizeof(struct txdma_mailbox),
2971 rp->mbox, rp->mbox_dma);
2972 rp->mbox = NULL;
2973 }
2974 if (rp->descr) {
2975 int i;
2976
2977 for (i = 0; i < MAX_TX_RING_SIZE; i++) {
2978 if (rp->tx_buffs[i].skb)
2979 (void) release_tx_packet(np, rp, i);
2980 }
2981
2982 np->ops->free_coherent(np->device,
2983 MAX_TX_RING_SIZE * sizeof(__le64),
2984 rp->descr, rp->descr_dma);
2985 rp->descr = NULL;
2986 rp->pending = 0;
2987 rp->prod = 0;
2988 rp->cons = 0;
2989 rp->wrap_bit = 0;
2990 }
2991}
2992
2993static void niu_free_channels(struct niu *np)
2994{
2995 int i;
2996
2997 if (np->rx_rings) {
2998 for (i = 0; i < np->num_rx_rings; i++) {
2999 struct rx_ring_info *rp = &np->rx_rings[i];
3000
3001 niu_free_rx_ring_info(np, rp);
3002 }
3003 kfree(np->rx_rings);
3004 np->rx_rings = NULL;
3005 np->num_rx_rings = 0;
3006 }
3007
3008 if (np->tx_rings) {
3009 for (i = 0; i < np->num_tx_rings; i++) {
3010 struct tx_ring_info *rp = &np->tx_rings[i];
3011
3012 niu_free_tx_ring_info(np, rp);
3013 }
3014 kfree(np->tx_rings);
3015 np->tx_rings = NULL;
3016 np->num_tx_rings = 0;
3017 }
3018}
3019
3020static int niu_alloc_rx_ring_info(struct niu *np,
3021 struct rx_ring_info *rp)
3022{
3023 BUILD_BUG_ON(sizeof(struct rxdma_mailbox) != 64);
3024
3025 rp->rxhash = kzalloc(MAX_RBR_RING_SIZE * sizeof(struct page *),
3026 GFP_KERNEL);
3027 if (!rp->rxhash)
3028 return -ENOMEM;
3029
3030 rp->mbox = np->ops->alloc_coherent(np->device,
3031 sizeof(struct rxdma_mailbox),
3032 &rp->mbox_dma, GFP_KERNEL);
3033 if (!rp->mbox)
3034 return -ENOMEM;
3035 if ((unsigned long)rp->mbox & (64UL - 1)) {
3036 dev_err(np->device, PFX "%s: Coherent alloc gives misaligned "
3037 "RXDMA mailbox %p\n", np->dev->name, rp->mbox);
3038 return -EINVAL;
3039 }
3040
3041 rp->rcr = np->ops->alloc_coherent(np->device,
3042 MAX_RCR_RING_SIZE * sizeof(__le64),
3043 &rp->rcr_dma, GFP_KERNEL);
3044 if (!rp->rcr)
3045 return -ENOMEM;
3046 if ((unsigned long)rp->rcr & (64UL - 1)) {
3047 dev_err(np->device, PFX "%s: Coherent alloc gives misaligned "
3048 "RXDMA RCR table %p\n", np->dev->name, rp->rcr);
3049 return -EINVAL;
3050 }
3051 rp->rcr_table_size = MAX_RCR_RING_SIZE;
3052 rp->rcr_index = 0;
3053
3054 rp->rbr = np->ops->alloc_coherent(np->device,
3055 MAX_RBR_RING_SIZE * sizeof(__le32),
3056 &rp->rbr_dma, GFP_KERNEL);
3057 if (!rp->rbr)
3058 return -ENOMEM;
3059 if ((unsigned long)rp->rbr & (64UL - 1)) {
3060 dev_err(np->device, PFX "%s: Coherent alloc gives misaligned "
3061 "RXDMA RBR table %p\n", np->dev->name, rp->rbr);
3062 return -EINVAL;
3063 }
3064 rp->rbr_table_size = MAX_RBR_RING_SIZE;
3065 rp->rbr_index = 0;
3066 rp->rbr_pending = 0;
3067
3068 return 0;
3069}
3070
3071static void niu_set_max_burst(struct niu *np, struct tx_ring_info *rp)
3072{
3073 int mtu = np->dev->mtu;
3074
3075 /* These values are recommended by the HW designers for fair
3076 * utilization of DRR amongst the rings.
3077 */
3078 rp->max_burst = mtu + 32;
3079 if (rp->max_burst > 4096)
3080 rp->max_burst = 4096;
3081}
3082
3083static int niu_alloc_tx_ring_info(struct niu *np,
3084 struct tx_ring_info *rp)
3085{
3086 BUILD_BUG_ON(sizeof(struct txdma_mailbox) != 64);
3087
3088 rp->mbox = np->ops->alloc_coherent(np->device,
3089 sizeof(struct txdma_mailbox),
3090 &rp->mbox_dma, GFP_KERNEL);
3091 if (!rp->mbox)
3092 return -ENOMEM;
3093 if ((unsigned long)rp->mbox & (64UL - 1)) {
3094 dev_err(np->device, PFX "%s: Coherent alloc gives misaligned "
3095 "TXDMA mailbox %p\n", np->dev->name, rp->mbox);
3096 return -EINVAL;
3097 }
3098
3099 rp->descr = np->ops->alloc_coherent(np->device,
3100 MAX_TX_RING_SIZE * sizeof(__le64),
3101 &rp->descr_dma, GFP_KERNEL);
3102 if (!rp->descr)
3103 return -ENOMEM;
3104 if ((unsigned long)rp->descr & (64UL - 1)) {
3105 dev_err(np->device, PFX "%s: Coherent alloc gives misaligned "
3106 "TXDMA descr table %p\n", np->dev->name, rp->descr);
3107 return -EINVAL;
3108 }
3109
3110 rp->pending = MAX_TX_RING_SIZE;
3111 rp->prod = 0;
3112 rp->cons = 0;
3113 rp->wrap_bit = 0;
3114
3115 /* XXX make these configurable... XXX */
3116 rp->mark_freq = rp->pending / 4;
3117
3118 niu_set_max_burst(np, rp);
3119
3120 return 0;
3121}
3122
3123static void niu_size_rbr(struct niu *np, struct rx_ring_info *rp)
3124{
Olof Johansson81429972007-10-21 16:32:58 -0700[diff] [blame]3125 u16 bss;
David S. Millera3138df2007-10-09 01:54:01 -0700[diff] [blame]3126
Olof Johansson81429972007-10-21 16:32:58 -0700[diff] [blame]3127 bss = min(PAGE_SHIFT, 15);
David S. Millera3138df2007-10-09 01:54:01 -0700[diff] [blame]3128
Olof Johansson81429972007-10-21 16:32:58 -0700[diff] [blame]3129 rp->rbr_block_size = 1 << bss;
3130 rp->rbr_blocks_per_page = 1 << (PAGE_SHIFT-bss);
David S. Millera3138df2007-10-09 01:54:01 -0700[diff] [blame]3131
3132 rp->rbr_sizes[0] = 256;
3133 rp->rbr_sizes[1] = 1024;
3134 if (np->dev->mtu > ETH_DATA_LEN) {
3135 switch (PAGE_SIZE) {
3136 case 4 * 1024:
3137 rp->rbr_sizes[2] = 4096;
3138 break;
3139
3140 default:
3141 rp->rbr_sizes[2] = 8192;
3142 break;
3143 }
3144 } else {
3145 rp->rbr_sizes[2] = 2048;
3146 }
3147 rp->rbr_sizes[3] = rp->rbr_block_size;
3148}
3149
3150static int niu_alloc_channels(struct niu *np)
3151{
3152 struct niu_parent *parent = np->parent;
3153 int first_rx_channel, first_tx_channel;
3154 int i, port, err;
3155
3156 port = np->port;
3157 first_rx_channel = first_tx_channel = 0;
3158 for (i = 0; i < port; i++) {
3159 first_rx_channel += parent->rxchan_per_port[i];
3160 first_tx_channel += parent->txchan_per_port[i];
3161 }
3162
3163 np->num_rx_rings = parent->rxchan_per_port[port];
3164 np->num_tx_rings = parent->txchan_per_port[port];
3165
3166 np->rx_rings = kzalloc(np->num_rx_rings * sizeof(struct rx_ring_info),
3167 GFP_KERNEL);
3168 err = -ENOMEM;
3169 if (!np->rx_rings)
3170 goto out_err;
3171
3172 for (i = 0; i < np->num_rx_rings; i++) {
3173 struct rx_ring_info *rp = &np->rx_rings[i];
3174
3175 rp->np = np;
3176 rp->rx_channel = first_rx_channel + i;
3177
3178 err = niu_alloc_rx_ring_info(np, rp);
3179 if (err)
3180 goto out_err;
3181
3182 niu_size_rbr(np, rp);
3183
3184 /* XXX better defaults, configurable, etc... XXX */
3185 rp->nonsyn_window = 64;
3186 rp->nonsyn_threshold = rp->rcr_table_size - 64;
3187 rp->syn_window = 64;
3188 rp->syn_threshold = rp->rcr_table_size - 64;
3189 rp->rcr_pkt_threshold = 16;
3190 rp->rcr_timeout = 8;
3191 rp->rbr_kick_thresh = RBR_REFILL_MIN;
3192 if (rp->rbr_kick_thresh < rp->rbr_blocks_per_page)
3193 rp->rbr_kick_thresh = rp->rbr_blocks_per_page;
3194
3195 err = niu_rbr_fill(np, rp, GFP_KERNEL);
3196 if (err)
3197 return err;
3198 }
3199
3200 np->tx_rings = kzalloc(np->num_tx_rings * sizeof(struct tx_ring_info),
3201 GFP_KERNEL);
3202 err = -ENOMEM;
3203 if (!np->tx_rings)
3204 goto out_err;
3205
3206 for (i = 0; i < np->num_tx_rings; i++) {
3207 struct tx_ring_info *rp = &np->tx_rings[i];
3208
3209 rp->np = np;
3210 rp->tx_channel = first_tx_channel + i;
3211
3212 err = niu_alloc_tx_ring_info(np, rp);
3213 if (err)
3214 goto out_err;
3215 }
3216
3217 return 0;
3218
3219out_err:
3220 niu_free_channels(np);
3221 return err;
3222}
3223
3224static int niu_tx_cs_sng_poll(struct niu *np, int channel)
3225{
3226 int limit = 1000;
3227
3228 while (--limit > 0) {
3229 u64 val = nr64(TX_CS(channel));
3230 if (val & TX_CS_SNG_STATE)
3231 return 0;
3232 }
3233 return -ENODEV;
3234}
3235
3236static int niu_tx_channel_stop(struct niu *np, int channel)
3237{
3238 u64 val = nr64(TX_CS(channel));
3239
3240 val |= TX_CS_STOP_N_GO;
3241 nw64(TX_CS(channel), val);
3242
3243 return niu_tx_cs_sng_poll(np, channel);
3244}
3245
3246static int niu_tx_cs_reset_poll(struct niu *np, int channel)
3247{
3248 int limit = 1000;
3249
3250 while (--limit > 0) {
3251 u64 val = nr64(TX_CS(channel));
3252 if (!(val & TX_CS_RST))
3253 return 0;
3254 }
3255 return -ENODEV;
3256}
3257
3258static int niu_tx_channel_reset(struct niu *np, int channel)
3259{
3260 u64 val = nr64(TX_CS(channel));
3261 int err;
3262
3263 val |= TX_CS_RST;
3264 nw64(TX_CS(channel), val);
3265
3266 err = niu_tx_cs_reset_poll(np, channel);
3267 if (!err)
3268 nw64(TX_RING_KICK(channel), 0);
3269
3270 return err;
3271}
3272
3273static int niu_tx_channel_lpage_init(struct niu *np, int channel)
3274{
3275 u64 val;
3276
3277 nw64(TX_LOG_MASK1(channel), 0);
3278 nw64(TX_LOG_VAL1(channel), 0);
3279 nw64(TX_LOG_MASK2(channel), 0);
3280 nw64(TX_LOG_VAL2(channel), 0);
3281 nw64(TX_LOG_PAGE_RELO1(channel), 0);
3282 nw64(TX_LOG_PAGE_RELO2(channel), 0);
3283 nw64(TX_LOG_PAGE_HDL(channel), 0);
3284
3285 val = (u64)np->port << TX_LOG_PAGE_VLD_FUNC_SHIFT;
3286 val |= (TX_LOG_PAGE_VLD_PAGE0 | TX_LOG_PAGE_VLD_PAGE1);
3287 nw64(TX_LOG_PAGE_VLD(channel), val);
3288
3289 /* XXX TXDMA 32bit mode? XXX */
3290
3291 return 0;
3292}
3293
3294static void niu_txc_enable_port(struct niu *np, int on)
3295{
3296 unsigned long flags;
3297 u64 val, mask;
3298
3299 niu_lock_parent(np, flags);
3300 val = nr64(TXC_CONTROL);
3301 mask = (u64)1 << np->port;
3302 if (on) {
3303 val |= TXC_CONTROL_ENABLE | mask;
3304 } else {
3305 val &= ~mask;
3306 if ((val & ~TXC_CONTROL_ENABLE) == 0)
3307 val &= ~TXC_CONTROL_ENABLE;
3308 }
3309 nw64(TXC_CONTROL, val);
3310 niu_unlock_parent(np, flags);
3311}
3312
3313static void niu_txc_set_imask(struct niu *np, u64 imask)
3314{
3315 unsigned long flags;
3316 u64 val;
3317
3318 niu_lock_parent(np, flags);
3319 val = nr64(TXC_INT_MASK);
3320 val &= ~TXC_INT_MASK_VAL(np->port);
3321 val |= (imask << TXC_INT_MASK_VAL_SHIFT(np->port));
3322 niu_unlock_parent(np, flags);
3323}
3324
3325static void niu_txc_port_dma_enable(struct niu *np, int on)
3326{
3327 u64 val = 0;
3328
3329 if (on) {
3330 int i;
3331
3332 for (i = 0; i < np->num_tx_rings; i++)
3333 val |= (1 << np->tx_rings[i].tx_channel);
3334 }
3335 nw64(TXC_PORT_DMA(np->port), val);
3336}
3337
3338static int niu_init_one_tx_channel(struct niu *np, struct tx_ring_info *rp)
3339{
3340 int err, channel = rp->tx_channel;
3341 u64 val, ring_len;
3342
3343 err = niu_tx_channel_stop(np, channel);
3344 if (err)
3345 return err;
3346
3347 err = niu_tx_channel_reset(np, channel);
3348 if (err)
3349 return err;
3350
3351 err = niu_tx_channel_lpage_init(np, channel);
3352 if (err)
3353 return err;
3354
3355 nw64(TXC_DMA_MAX(channel), rp->max_burst);
3356 nw64(TX_ENT_MSK(channel), 0);
3357
3358 if (rp->descr_dma & ~(TX_RNG_CFIG_STADDR_BASE |
3359 TX_RNG_CFIG_STADDR)) {
3360 dev_err(np->device, PFX "%s: TX ring channel %d "
3361 "DMA addr (%llx) is not aligned.\n",
3362 np->dev->name, channel,
3363 (unsigned long long) rp->descr_dma);
3364 return -EINVAL;
3365 }
3366
3367 /* The length field in TX_RNG_CFIG is measured in 64-byte
3368 * blocks. rp->pending is the number of TX descriptors in
3369 * our ring, 8 bytes each, thus we divide by 8 bytes more
3370 * to get the proper value the chip wants.
3371 */
3372 ring_len = (rp->pending / 8);
3373
3374 val = ((ring_len << TX_RNG_CFIG_LEN_SHIFT) |
3375 rp->descr_dma);
3376 nw64(TX_RNG_CFIG(channel), val);
3377
3378 if (((rp->mbox_dma >> 32) & ~TXDMA_MBH_MBADDR) ||
3379 ((u32)rp->mbox_dma & ~TXDMA_MBL_MBADDR)) {
3380 dev_err(np->device, PFX "%s: TX ring channel %d "
3381 "MBOX addr (%llx) is has illegal bits.\n",
3382 np->dev->name, channel,
3383 (unsigned long long) rp->mbox_dma);
3384 return -EINVAL;
3385 }
3386 nw64(TXDMA_MBH(channel), rp->mbox_dma >> 32);
3387 nw64(TXDMA_MBL(channel), rp->mbox_dma & TXDMA_MBL_MBADDR);
3388
3389 nw64(TX_CS(channel), 0);
3390
3391 rp->last_pkt_cnt = 0;
3392
3393 return 0;
3394}
3395
3396static void niu_init_rdc_groups(struct niu *np)
3397{
3398 struct niu_rdc_tables *tp = &np->parent->rdc_group_cfg[np->port];
3399 int i, first_table_num = tp->first_table_num;
3400
3401 for (i = 0; i < tp->num_tables; i++) {
3402 struct rdc_table *tbl = &tp->tables[i];
3403 int this_table = first_table_num + i;
3404 int slot;
3405
3406 for (slot = 0; slot < NIU_RDC_TABLE_SLOTS; slot++)
3407 nw64(RDC_TBL(this_table, slot),
3408 tbl->rxdma_channel[slot]);
3409 }
3410
3411 nw64(DEF_RDC(np->port), np->parent->rdc_default[np->port]);
3412}
3413
3414static void niu_init_drr_weight(struct niu *np)
3415{
3416 int type = phy_decode(np->parent->port_phy, np->port);
3417 u64 val;
3418
3419 switch (type) {
3420 case PORT_TYPE_10G:
3421 val = PT_DRR_WEIGHT_DEFAULT_10G;
3422 break;
3423
3424 case PORT_TYPE_1G:
3425 default:
3426 val = PT_DRR_WEIGHT_DEFAULT_1G;
3427 break;
3428 }
3429 nw64(PT_DRR_WT(np->port), val);
3430}
3431
3432static int niu_init_hostinfo(struct niu *np)
3433{
3434 struct niu_parent *parent = np->parent;
3435 struct niu_rdc_tables *tp = &parent->rdc_group_cfg[np->port];
3436 int i, err, num_alt = niu_num_alt_addr(np);
3437 int first_rdc_table = tp->first_table_num;
3438
3439 err = niu_set_primary_mac_rdc_table(np, first_rdc_table, 1);
3440 if (err)
3441 return err;
3442
3443 err = niu_set_multicast_mac_rdc_table(np, first_rdc_table, 1);
3444 if (err)
3445 return err;
3446
3447 for (i = 0; i < num_alt; i++) {
3448 err = niu_set_alt_mac_rdc_table(np, i, first_rdc_table, 1);
3449 if (err)
3450 return err;
3451 }
3452
3453 return 0;
3454}
3455
3456static int niu_rx_channel_reset(struct niu *np, int channel)
3457{
3458 return niu_set_and_wait_clear(np, RXDMA_CFIG1(channel),
3459 RXDMA_CFIG1_RST, 1000, 10,
3460 "RXDMA_CFIG1");
3461}
3462
3463static int niu_rx_channel_lpage_init(struct niu *np, int channel)
3464{
3465 u64 val;
3466
3467 nw64(RX_LOG_MASK1(channel), 0);
3468 nw64(RX_LOG_VAL1(channel), 0);
3469 nw64(RX_LOG_MASK2(channel), 0);
3470 nw64(RX_LOG_VAL2(channel), 0);
3471 nw64(RX_LOG_PAGE_RELO1(channel), 0);
3472 nw64(RX_LOG_PAGE_RELO2(channel), 0);
3473 nw64(RX_LOG_PAGE_HDL(channel), 0);
3474
3475 val = (u64)np->port << RX_LOG_PAGE_VLD_FUNC_SHIFT;
3476 val |= (RX_LOG_PAGE_VLD_PAGE0 | RX_LOG_PAGE_VLD_PAGE1);
3477 nw64(RX_LOG_PAGE_VLD(channel), val);
3478
3479 return 0;
3480}
3481
3482static void niu_rx_channel_wred_init(struct niu *np, struct rx_ring_info *rp)
3483{
3484 u64 val;
3485
3486 val = (((u64)rp->nonsyn_window << RDC_RED_PARA_WIN_SHIFT) |
3487 ((u64)rp->nonsyn_threshold << RDC_RED_PARA_THRE_SHIFT) |
3488 ((u64)rp->syn_window << RDC_RED_PARA_WIN_SYN_SHIFT) |
3489 ((u64)rp->syn_threshold << RDC_RED_PARA_THRE_SYN_SHIFT));
3490 nw64(RDC_RED_PARA(rp->rx_channel), val);
3491}
3492
3493static int niu_compute_rbr_cfig_b(struct rx_ring_info *rp, u64 *ret)
3494{
3495 u64 val = 0;
3496
3497 switch (rp->rbr_block_size) {
3498 case 4 * 1024:
3499 val |= (RBR_BLKSIZE_4K << RBR_CFIG_B_BLKSIZE_SHIFT);
3500 break;
3501 case 8 * 1024:
3502 val |= (RBR_BLKSIZE_8K << RBR_CFIG_B_BLKSIZE_SHIFT);
3503 break;
3504 case 16 * 1024:
3505 val |= (RBR_BLKSIZE_16K << RBR_CFIG_B_BLKSIZE_SHIFT);
3506 break;
3507 case 32 * 1024:
3508 val |= (RBR_BLKSIZE_32K << RBR_CFIG_B_BLKSIZE_SHIFT);
3509 break;
3510 default:
3511 return -EINVAL;
3512 }
3513 val |= RBR_CFIG_B_VLD2;
3514 switch (rp->rbr_sizes[2]) {
3515 case 2 * 1024:
3516 val |= (RBR_BUFSZ2_2K << RBR_CFIG_B_BUFSZ2_SHIFT);
3517 break;
3518 case 4 * 1024:
3519 val |= (RBR_BUFSZ2_4K << RBR_CFIG_B_BUFSZ2_SHIFT);
3520 break;
3521 case 8 * 1024:
3522 val |= (RBR_BUFSZ2_8K << RBR_CFIG_B_BUFSZ2_SHIFT);
3523 break;
3524 case 16 * 1024:
3525 val |= (RBR_BUFSZ2_16K << RBR_CFIG_B_BUFSZ2_SHIFT);
3526 break;
3527
3528 default:
3529 return -EINVAL;
3530 }
3531 val |= RBR_CFIG_B_VLD1;
3532 switch (rp->rbr_sizes[1]) {
3533 case 1 * 1024:
3534 val |= (RBR_BUFSZ1_1K << RBR_CFIG_B_BUFSZ1_SHIFT);
3535 break;
3536 case 2 * 1024:
3537 val |= (RBR_BUFSZ1_2K << RBR_CFIG_B_BUFSZ1_SHIFT);
3538 break;
3539 case 4 * 1024:
3540 val |= (RBR_BUFSZ1_4K << RBR_CFIG_B_BUFSZ1_SHIFT);
3541 break;
3542 case 8 * 1024:
3543 val |= (RBR_BUFSZ1_8K << RBR_CFIG_B_BUFSZ1_SHIFT);
3544 break;
3545
3546 default:
3547 return -EINVAL;
3548 }
3549 val |= RBR_CFIG_B_VLD0;
3550 switch (rp->rbr_sizes[0]) {
3551 case 256:
3552 val |= (RBR_BUFSZ0_256 << RBR_CFIG_B_BUFSZ0_SHIFT);
3553 break;
3554 case 512:
3555 val |= (RBR_BUFSZ0_512 << RBR_CFIG_B_BUFSZ0_SHIFT);
3556 break;
3557 case 1 * 1024:
3558 val |= (RBR_BUFSZ0_1K << RBR_CFIG_B_BUFSZ0_SHIFT);
3559 break;
3560 case 2 * 1024:
3561 val |= (RBR_BUFSZ0_2K << RBR_CFIG_B_BUFSZ0_SHIFT);
3562 break;
3563
3564 default:
3565 return -EINVAL;
3566 }
3567
3568 *ret = val;
3569 return 0;
3570}
3571
3572static int niu_enable_rx_channel(struct niu *np, int channel, int on)
3573{
3574 u64 val = nr64(RXDMA_CFIG1(channel));
3575 int limit;
3576
3577 if (on)
3578 val |= RXDMA_CFIG1_EN;
3579 else
3580 val &= ~RXDMA_CFIG1_EN;
3581 nw64(RXDMA_CFIG1(channel), val);
3582
3583 limit = 1000;
3584 while (--limit > 0) {
3585 if (nr64(RXDMA_CFIG1(channel)) & RXDMA_CFIG1_QST)
3586 break;
3587 udelay(10);
3588 }
3589 if (limit <= 0)
3590 return -ENODEV;
3591 return 0;
3592}
3593
3594static int niu_init_one_rx_channel(struct niu *np, struct rx_ring_info *rp)
3595{
3596 int err, channel = rp->rx_channel;
3597 u64 val;
3598
3599 err = niu_rx_channel_reset(np, channel);
3600 if (err)
3601 return err;
3602
3603 err = niu_rx_channel_lpage_init(np, channel);
3604 if (err)
3605 return err;
3606
3607 niu_rx_channel_wred_init(np, rp);
3608
3609 nw64(RX_DMA_ENT_MSK(channel), RX_DMA_ENT_MSK_RBR_EMPTY);
3610 nw64(RX_DMA_CTL_STAT(channel),
3611 (RX_DMA_CTL_STAT_MEX |
3612 RX_DMA_CTL_STAT_RCRTHRES |
3613 RX_DMA_CTL_STAT_RCRTO |
3614 RX_DMA_CTL_STAT_RBR_EMPTY));
3615 nw64(RXDMA_CFIG1(channel), rp->mbox_dma >> 32);
3616 nw64(RXDMA_CFIG2(channel), (rp->mbox_dma & 0x00000000ffffffc0));
3617 nw64(RBR_CFIG_A(channel),
3618 ((u64)rp->rbr_table_size << RBR_CFIG_A_LEN_SHIFT) |
3619 (rp->rbr_dma & (RBR_CFIG_A_STADDR_BASE | RBR_CFIG_A_STADDR)));
3620 err = niu_compute_rbr_cfig_b(rp, &val);
3621 if (err)
3622 return err;
3623 nw64(RBR_CFIG_B(channel), val);
3624 nw64(RCRCFIG_A(channel),
3625 ((u64)rp->rcr_table_size << RCRCFIG_A_LEN_SHIFT) |
3626 (rp->rcr_dma & (RCRCFIG_A_STADDR_BASE | RCRCFIG_A_STADDR)));
3627 nw64(RCRCFIG_B(channel),
3628 ((u64)rp->rcr_pkt_threshold << RCRCFIG_B_PTHRES_SHIFT) |
3629 RCRCFIG_B_ENTOUT |
3630 ((u64)rp->rcr_timeout << RCRCFIG_B_TIMEOUT_SHIFT));
3631
3632 err = niu_enable_rx_channel(np, channel, 1);
3633 if (err)
3634 return err;
3635
3636 nw64(RBR_KICK(channel), rp->rbr_index);
3637
3638 val = nr64(RX_DMA_CTL_STAT(channel));
3639 val |= RX_DMA_CTL_STAT_RBR_EMPTY;
3640 nw64(RX_DMA_CTL_STAT(channel), val);
3641
3642 return 0;
3643}
3644
3645static int niu_init_rx_channels(struct niu *np)
3646{
3647 unsigned long flags;
3648 u64 seed = jiffies_64;
3649 int err, i;
3650
3651 niu_lock_parent(np, flags);
3652 nw64(RX_DMA_CK_DIV, np->parent->rxdma_clock_divider);
3653 nw64(RED_RAN_INIT, RED_RAN_INIT_OPMODE | (seed & RED_RAN_INIT_VAL));
3654 niu_unlock_parent(np, flags);
3655
3656 /* XXX RXDMA 32bit mode? XXX */
3657
3658 niu_init_rdc_groups(np);
3659 niu_init_drr_weight(np);
3660
3661 err = niu_init_hostinfo(np);
3662 if (err)
3663 return err;
3664
3665 for (i = 0; i < np->num_rx_rings; i++) {
3666 struct rx_ring_info *rp = &np->rx_rings[i];
3667
3668 err = niu_init_one_rx_channel(np, rp);
3669 if (err)
3670 return err;
3671 }
3672
3673 return 0;
3674}
3675
3676static int niu_set_ip_frag_rule(struct niu *np)
3677{
3678 struct niu_parent *parent = np->parent;
3679 struct niu_classifier *cp = &np->clas;
3680 struct niu_tcam_entry *tp;
3681 int index, err;
3682
3683 /* XXX fix this allocation scheme XXX */
3684 index = cp->tcam_index;
3685 tp = &parent->tcam[index];
3686
3687 /* Note that the noport bit is the same in both ipv4 and
3688 * ipv6 format TCAM entries.
3689 */
3690 memset(tp, 0, sizeof(*tp));
3691 tp->key[1] = TCAM_V4KEY1_NOPORT;
3692 tp->key_mask[1] = TCAM_V4KEY1_NOPORT;
3693 tp->assoc_data = (TCAM_ASSOCDATA_TRES_USE_OFFSET |
3694 ((u64)0 << TCAM_ASSOCDATA_OFFSET_SHIFT));
3695 err = tcam_write(np, index, tp->key, tp->key_mask);
3696 if (err)
3697 return err;
3698 err = tcam_assoc_write(np, index, tp->assoc_data);
3699 if (err)
3700 return err;
3701
3702 return 0;
3703}
3704
3705static int niu_init_classifier_hw(struct niu *np)
3706{
3707 struct niu_parent *parent = np->parent;
3708 struct niu_classifier *cp = &np->clas;
3709 int i, err;
3710
3711 nw64(H1POLY, cp->h1_init);
3712 nw64(H2POLY, cp->h2_init);
3713
3714 err = niu_init_hostinfo(np);
3715 if (err)
3716 return err;
3717
3718 for (i = 0; i < ENET_VLAN_TBL_NUM_ENTRIES; i++) {
3719 struct niu_vlan_rdc *vp = &cp->vlan_mappings[i];
3720
3721 vlan_tbl_write(np, i, np->port,
3722 vp->vlan_pref, vp->rdc_num);
3723 }
3724
3725 for (i = 0; i < cp->num_alt_mac_mappings; i++) {
3726 struct niu_altmac_rdc *ap = &cp->alt_mac_mappings[i];
3727
3728 err = niu_set_alt_mac_rdc_table(np, ap->alt_mac_num,
3729 ap->rdc_num, ap->mac_pref);
3730 if (err)
3731 return err;
3732 }
3733
3734 for (i = CLASS_CODE_USER_PROG1; i <= CLASS_CODE_SCTP_IPV6; i++) {
3735 int index = i - CLASS_CODE_USER_PROG1;
3736
3737 err = niu_set_tcam_key(np, i, parent->tcam_key[index]);
3738 if (err)
3739 return err;
3740 err = niu_set_flow_key(np, i, parent->flow_key[index]);
3741 if (err)
3742 return err;
3743 }
3744
3745 err = niu_set_ip_frag_rule(np);
3746 if (err)
3747 return err;
3748
3749 tcam_enable(np, 1);
3750
3751 return 0;
3752}
3753
3754static int niu_zcp_write(struct niu *np, int index, u64 *data)
3755{
3756 nw64(ZCP_RAM_DATA0, data[0]);
3757 nw64(ZCP_RAM_DATA1, data[1]);
3758 nw64(ZCP_RAM_DATA2, data[2]);
3759 nw64(ZCP_RAM_DATA3, data[3]);
3760 nw64(ZCP_RAM_DATA4, data[4]);
3761 nw64(ZCP_RAM_BE, ZCP_RAM_BE_VAL);
3762 nw64(ZCP_RAM_ACC,
3763 (ZCP_RAM_ACC_WRITE |
3764 (0 << ZCP_RAM_ACC_ZFCID_SHIFT) |
3765 (ZCP_RAM_SEL_CFIFO(np->port) << ZCP_RAM_ACC_RAM_SEL_SHIFT)));
3766
3767 return niu_wait_bits_clear(np, ZCP_RAM_ACC, ZCP_RAM_ACC_BUSY,
3768 1000, 100);
3769}
3770
3771static int niu_zcp_read(struct niu *np, int index, u64 *data)
3772{
3773 int err;
3774
3775 err = niu_wait_bits_clear(np, ZCP_RAM_ACC, ZCP_RAM_ACC_BUSY,
3776 1000, 100);
3777 if (err) {
3778 dev_err(np->device, PFX "%s: ZCP read busy won't clear, "
3779 "ZCP_RAM_ACC[%llx]\n", np->dev->name,
3780 (unsigned long long) nr64(ZCP_RAM_ACC));
3781 return err;
3782 }
3783
3784 nw64(ZCP_RAM_ACC,
3785 (ZCP_RAM_ACC_READ |
3786 (0 << ZCP_RAM_ACC_ZFCID_SHIFT) |
3787 (ZCP_RAM_SEL_CFIFO(np->port) << ZCP_RAM_ACC_RAM_SEL_SHIFT)));
3788
3789 err = niu_wait_bits_clear(np, ZCP_RAM_ACC, ZCP_RAM_ACC_BUSY,
3790 1000, 100);
3791 if (err) {
3792 dev_err(np->device, PFX "%s: ZCP read busy2 won't clear, "
3793 "ZCP_RAM_ACC[%llx]\n", np->dev->name,
3794 (unsigned long long) nr64(ZCP_RAM_ACC));
3795 return err;
3796 }
3797
3798 data[0] = nr64(ZCP_RAM_DATA0);
3799 data[1] = nr64(ZCP_RAM_DATA1);
3800 data[2] = nr64(ZCP_RAM_DATA2);
3801 data[3] = nr64(ZCP_RAM_DATA3);
3802 data[4] = nr64(ZCP_RAM_DATA4);
3803
3804 return 0;
3805}
3806
3807static void niu_zcp_cfifo_reset(struct niu *np)
3808{
3809 u64 val = nr64(RESET_CFIFO);
3810
3811 val |= RESET_CFIFO_RST(np->port);
3812 nw64(RESET_CFIFO, val);
3813 udelay(10);
3814
3815 val &= ~RESET_CFIFO_RST(np->port);
3816 nw64(RESET_CFIFO, val);
3817}
3818
3819static int niu_init_zcp(struct niu *np)
3820{
3821 u64 data[5], rbuf[5];
3822 int i, max, err;
3823
3824 if (np->parent->plat_type != PLAT_TYPE_NIU) {
3825 if (np->port == 0 || np->port == 1)
3826 max = ATLAS_P0_P1_CFIFO_ENTRIES;
3827 else
3828 max = ATLAS_P2_P3_CFIFO_ENTRIES;
3829 } else
3830 max = NIU_CFIFO_ENTRIES;
3831
3832 data[0] = 0;
3833 data[1] = 0;
3834 data[2] = 0;
3835 data[3] = 0;
3836 data[4] = 0;
3837
3838 for (i = 0; i < max; i++) {
3839 err = niu_zcp_write(np, i, data);
3840 if (err)
3841 return err;
3842 err = niu_zcp_read(np, i, rbuf);
3843 if (err)
3844 return err;
3845 }
3846
3847 niu_zcp_cfifo_reset(np);
3848 nw64(CFIFO_ECC(np->port), 0);
3849 nw64(ZCP_INT_STAT, ZCP_INT_STAT_ALL);
3850 (void) nr64(ZCP_INT_STAT);
3851 nw64(ZCP_INT_MASK, ZCP_INT_MASK_ALL);
3852
3853 return 0;
3854}
3855
3856static void niu_ipp_write(struct niu *np, int index, u64 *data)
3857{
3858 u64 val = nr64_ipp(IPP_CFIG);
3859
3860 nw64_ipp(IPP_CFIG, val | IPP_CFIG_DFIFO_PIO_W);
3861 nw64_ipp(IPP_DFIFO_WR_PTR, index);
3862 nw64_ipp(IPP_DFIFO_WR0, data[0]);
3863 nw64_ipp(IPP_DFIFO_WR1, data[1]);
3864 nw64_ipp(IPP_DFIFO_WR2, data[2]);
3865 nw64_ipp(IPP_DFIFO_WR3, data[3]);
3866 nw64_ipp(IPP_DFIFO_WR4, data[4]);
3867 nw64_ipp(IPP_CFIG, val & ~IPP_CFIG_DFIFO_PIO_W);
3868}
3869
3870static void niu_ipp_read(struct niu *np, int index, u64 *data)
3871{
3872 nw64_ipp(IPP_DFIFO_RD_PTR, index);
3873 data[0] = nr64_ipp(IPP_DFIFO_RD0);
3874 data[1] = nr64_ipp(IPP_DFIFO_RD1);
3875 data[2] = nr64_ipp(IPP_DFIFO_RD2);
3876 data[3] = nr64_ipp(IPP_DFIFO_RD3);
3877 data[4] = nr64_ipp(IPP_DFIFO_RD4);
3878}
3879
3880static int niu_ipp_reset(struct niu *np)
3881{
3882 return niu_set_and_wait_clear_ipp(np, IPP_CFIG, IPP_CFIG_SOFT_RST,
3883 1000, 100, "IPP_CFIG");
3884}
3885
3886static int niu_init_ipp(struct niu *np)
3887{
3888 u64 data[5], rbuf[5], val;
3889 int i, max, err;
3890
3891 if (np->parent->plat_type != PLAT_TYPE_NIU) {
3892 if (np->port == 0 || np->port == 1)
3893 max = ATLAS_P0_P1_DFIFO_ENTRIES;
3894 else
3895 max = ATLAS_P2_P3_DFIFO_ENTRIES;
3896 } else
3897 max = NIU_DFIFO_ENTRIES;
3898
3899 data[0] = 0;
3900 data[1] = 0;
3901 data[2] = 0;
3902 data[3] = 0;
3903 data[4] = 0;
3904
3905 for (i = 0; i < max; i++) {
3906 niu_ipp_write(np, i, data);
3907 niu_ipp_read(np, i, rbuf);
3908 }
3909
3910 (void) nr64_ipp(IPP_INT_STAT);
3911 (void) nr64_ipp(IPP_INT_STAT);
3912
3913 err = niu_ipp_reset(np);
3914 if (err)
3915 return err;
3916
3917 (void) nr64_ipp(IPP_PKT_DIS);
3918 (void) nr64_ipp(IPP_BAD_CS_CNT);
3919 (void) nr64_ipp(IPP_ECC);
3920
3921 (void) nr64_ipp(IPP_INT_STAT);
3922
3923 nw64_ipp(IPP_MSK, ~IPP_MSK_ALL);
3924
3925 val = nr64_ipp(IPP_CFIG);
3926 val &= ~IPP_CFIG_IP_MAX_PKT;
3927 val |= (IPP_CFIG_IPP_ENABLE |
3928 IPP_CFIG_DFIFO_ECC_EN |
3929 IPP_CFIG_DROP_BAD_CRC |
3930 IPP_CFIG_CKSUM_EN |
3931 (0x1ffff << IPP_CFIG_IP_MAX_PKT_SHIFT));
3932 nw64_ipp(IPP_CFIG, val);
3933
3934 return 0;
3935}
3936
Mirko Lindner0c3b0912007-12-05 21:10:02 -0800[diff] [blame]3937static void niu_handle_led(struct niu *np, int status)
David S. Millera3138df2007-10-09 01:54:01 -0700[diff] [blame]3938{
David S. Millera3138df2007-10-09 01:54:01 -0700[diff] [blame]3939 u64 val;
David S. Millera3138df2007-10-09 01:54:01 -0700[diff] [blame]3940 val = nr64_mac(XMAC_CONFIG);
3941
3942 if ((np->flags & NIU_FLAGS_10G) != 0 &&
3943 (np->flags & NIU_FLAGS_FIBER) != 0) {
Mirko Lindner0c3b0912007-12-05 21:10:02 -0800[diff] [blame]3944 if (status) {
David S. Millera3138df2007-10-09 01:54:01 -0700[diff] [blame]3945 val |= XMAC_CONFIG_LED_POLARITY;
3946 val &= ~XMAC_CONFIG_FORCE_LED_ON;
3947 } else {
3948 val |= XMAC_CONFIG_FORCE_LED_ON;
3949 val &= ~XMAC_CONFIG_LED_POLARITY;
3950 }
3951 }
3952
Mirko Lindner0c3b0912007-12-05 21:10:02 -0800[diff] [blame]3953 nw64_mac(XMAC_CONFIG, val);
3954}
3955
3956static void niu_init_xif_xmac(struct niu *np)
3957{
3958 struct niu_link_config *lp = &np->link_config;
3959 u64 val;
3960
3961 val = nr64_mac(XMAC_CONFIG);
David S. Millera3138df2007-10-09 01:54:01 -0700[diff] [blame]3962 val &= ~XMAC_CONFIG_SEL_POR_CLK_SRC;
3963
3964 val |= XMAC_CONFIG_TX_OUTPUT_EN;
3965
3966 if (lp->loopback_mode == LOOPBACK_MAC) {
3967 val &= ~XMAC_CONFIG_SEL_POR_CLK_SRC;
3968 val |= XMAC_CONFIG_LOOPBACK;
3969 } else {
3970 val &= ~XMAC_CONFIG_LOOPBACK;
3971 }
3972
3973 if (np->flags & NIU_FLAGS_10G) {
3974 val &= ~XMAC_CONFIG_LFS_DISABLE;
3975 } else {
3976 val |= XMAC_CONFIG_LFS_DISABLE;
3977 if (!(np->flags & NIU_FLAGS_FIBER))
3978 val |= XMAC_CONFIG_1G_PCS_BYPASS;
3979 else
3980 val &= ~XMAC_CONFIG_1G_PCS_BYPASS;
3981 }
3982
3983 val &= ~XMAC_CONFIG_10G_XPCS_BYPASS;
3984
3985 if (lp->active_speed == SPEED_100)
3986 val |= XMAC_CONFIG_SEL_CLK_25MHZ;
3987 else
3988 val &= ~XMAC_CONFIG_SEL_CLK_25MHZ;
3989
3990 nw64_mac(XMAC_CONFIG, val);
3991
3992 val = nr64_mac(XMAC_CONFIG);
3993 val &= ~XMAC_CONFIG_MODE_MASK;
3994 if (np->flags & NIU_FLAGS_10G) {
3995 val |= XMAC_CONFIG_MODE_XGMII;
3996 } else {
3997 if (lp->active_speed == SPEED_100)
3998 val |= XMAC_CONFIG_MODE_MII;
3999 else
4000 val |= XMAC_CONFIG_MODE_GMII;
4001 }
4002
4003 nw64_mac(XMAC_CONFIG, val);
4004}
4005
4006static void niu_init_xif_bmac(struct niu *np)
4007{
4008 struct niu_link_config *lp = &np->link_config;
4009 u64 val;
4010
4011 val = BMAC_XIF_CONFIG_TX_OUTPUT_EN;
4012
4013 if (lp->loopback_mode == LOOPBACK_MAC)
4014 val |= BMAC_XIF_CONFIG_MII_LOOPBACK;
4015 else
4016 val &= ~BMAC_XIF_CONFIG_MII_LOOPBACK;
4017
4018 if (lp->active_speed == SPEED_1000)
4019 val |= BMAC_XIF_CONFIG_GMII_MODE;
4020 else
4021 val &= ~BMAC_XIF_CONFIG_GMII_MODE;
4022
4023 val &= ~(BMAC_XIF_CONFIG_LINK_LED |
4024 BMAC_XIF_CONFIG_LED_POLARITY);
4025
4026 if (!(np->flags & NIU_FLAGS_10G) &&
4027 !(np->flags & NIU_FLAGS_FIBER) &&
4028 lp->active_speed == SPEED_100)
4029 val |= BMAC_XIF_CONFIG_25MHZ_CLOCK;
4030 else
4031 val &= ~BMAC_XIF_CONFIG_25MHZ_CLOCK;
4032
4033 nw64_mac(BMAC_XIF_CONFIG, val);
4034}
4035
4036static void niu_init_xif(struct niu *np)
4037{
4038 if (np->flags & NIU_FLAGS_XMAC)
4039 niu_init_xif_xmac(np);
4040 else
4041 niu_init_xif_bmac(np);
4042}
4043
4044static void niu_pcs_mii_reset(struct niu *np)
4045{
4046 u64 val = nr64_pcs(PCS_MII_CTL);
4047 val |= PCS_MII_CTL_RST;
4048 nw64_pcs(PCS_MII_CTL, val);
4049}
4050
4051static void niu_xpcs_reset(struct niu *np)
4052{
4053 u64 val = nr64_xpcs(XPCS_CONTROL1);
4054 val |= XPCS_CONTROL1_RESET;
4055 nw64_xpcs(XPCS_CONTROL1, val);
4056}
4057
4058static int niu_init_pcs(struct niu *np)
4059{
4060 struct niu_link_config *lp = &np->link_config;
4061 u64 val;
4062
4063 switch (np->flags & (NIU_FLAGS_10G | NIU_FLAGS_FIBER)) {
4064 case NIU_FLAGS_FIBER:
4065 /* 1G fiber */
4066 nw64_pcs(PCS_CONF, PCS_CONF_MASK | PCS_CONF_ENABLE);
4067 nw64_pcs(PCS_DPATH_MODE, 0);
4068 niu_pcs_mii_reset(np);
4069 break;
4070
4071 case NIU_FLAGS_10G:
4072 case NIU_FLAGS_10G | NIU_FLAGS_FIBER:
4073 if (!(np->flags & NIU_FLAGS_XMAC))
4074 return -EINVAL;
4075
4076 /* 10G copper or fiber */
4077 val = nr64_mac(XMAC_CONFIG);
4078 val &= ~XMAC_CONFIG_10G_XPCS_BYPASS;
4079 nw64_mac(XMAC_CONFIG, val);
4080
4081 niu_xpcs_reset(np);
4082
4083 val = nr64_xpcs(XPCS_CONTROL1);
4084 if (lp->loopback_mode == LOOPBACK_PHY)
4085 val |= XPCS_CONTROL1_LOOPBACK;
4086 else
4087 val &= ~XPCS_CONTROL1_LOOPBACK;
4088 nw64_xpcs(XPCS_CONTROL1, val);
4089
4090 nw64_xpcs(XPCS_DESKEW_ERR_CNT, 0);
4091 (void) nr64_xpcs(XPCS_SYMERR_CNT01);
4092 (void) nr64_xpcs(XPCS_SYMERR_CNT23);
4093 break;
4094
4095 case 0:
4096 /* 1G copper */
4097 nw64_pcs(PCS_DPATH_MODE, PCS_DPATH_MODE_MII);
4098 niu_pcs_mii_reset(np);
4099 break;
4100
4101 default:
4102 return -EINVAL;
4103 }
4104
4105 return 0;
4106}
4107
4108static int niu_reset_tx_xmac(struct niu *np)
4109{
4110 return niu_set_and_wait_clear_mac(np, XTXMAC_SW_RST,
4111 (XTXMAC_SW_RST_REG_RS |
4112 XTXMAC_SW_RST_SOFT_RST),
4113 1000, 100, "XTXMAC_SW_RST");
4114}
4115
4116static int niu_reset_tx_bmac(struct niu *np)
4117{
4118 int limit;
4119
4120 nw64_mac(BTXMAC_SW_RST, BTXMAC_SW_RST_RESET);
4121 limit = 1000;
4122 while (--limit >= 0) {
4123 if (!(nr64_mac(BTXMAC_SW_RST) & BTXMAC_SW_RST_RESET))
4124 break;
4125 udelay(100);
4126 }
4127 if (limit < 0) {
4128 dev_err(np->device, PFX "Port %u TX BMAC would not reset, "
4129 "BTXMAC_SW_RST[%llx]\n",
4130 np->port,
4131 (unsigned long long) nr64_mac(BTXMAC_SW_RST));
4132 return -ENODEV;
4133 }
4134
4135 return 0;
4136}
4137
4138static int niu_reset_tx_mac(struct niu *np)
4139{
4140 if (np->flags & NIU_FLAGS_XMAC)
4141 return niu_reset_tx_xmac(np);
4142 else
4143 return niu_reset_tx_bmac(np);
4144}
4145
4146static void niu_init_tx_xmac(struct niu *np, u64 min, u64 max)
4147{
4148 u64 val;
4149
4150 val = nr64_mac(XMAC_MIN);
4151 val &= ~(XMAC_MIN_TX_MIN_PKT_SIZE |
4152 XMAC_MIN_RX_MIN_PKT_SIZE);
4153 val |= (min << XMAC_MIN_RX_MIN_PKT_SIZE_SHFT);
4154 val |= (min << XMAC_MIN_TX_MIN_PKT_SIZE_SHFT);
4155 nw64_mac(XMAC_MIN, val);
4156
4157 nw64_mac(XMAC_MAX, max);
4158
4159 nw64_mac(XTXMAC_STAT_MSK, ~(u64)0);
4160
4161 val = nr64_mac(XMAC_IPG);
4162 if (np->flags & NIU_FLAGS_10G) {
4163 val &= ~XMAC_IPG_IPG_XGMII;
4164 val |= (IPG_12_15_XGMII << XMAC_IPG_IPG_XGMII_SHIFT);
4165 } else {
4166 val &= ~XMAC_IPG_IPG_MII_GMII;
4167 val |= (IPG_12_MII_GMII << XMAC_IPG_IPG_MII_GMII_SHIFT);
4168 }
4169 nw64_mac(XMAC_IPG, val);
4170
4171 val = nr64_mac(XMAC_CONFIG);
4172 val &= ~(XMAC_CONFIG_ALWAYS_NO_CRC |
4173 XMAC_CONFIG_STRETCH_MODE |
4174 XMAC_CONFIG_VAR_MIN_IPG_EN |
4175 XMAC_CONFIG_TX_ENABLE);
4176 nw64_mac(XMAC_CONFIG, val);
4177
4178 nw64_mac(TXMAC_FRM_CNT, 0);
4179 nw64_mac(TXMAC_BYTE_CNT, 0);
4180}
4181
4182static void niu_init_tx_bmac(struct niu *np, u64 min, u64 max)
4183{
4184 u64 val;
4185
4186 nw64_mac(BMAC_MIN_FRAME, min);
4187 nw64_mac(BMAC_MAX_FRAME, max);
4188
4189 nw64_mac(BTXMAC_STATUS_MASK, ~(u64)0);
4190 nw64_mac(BMAC_CTRL_TYPE, 0x8808);
4191 nw64_mac(BMAC_PREAMBLE_SIZE, 7);
4192
4193 val = nr64_mac(BTXMAC_CONFIG);
4194 val &= ~(BTXMAC_CONFIG_FCS_DISABLE |
4195 BTXMAC_CONFIG_ENABLE);
4196 nw64_mac(BTXMAC_CONFIG, val);
4197}
4198
4199static void niu_init_tx_mac(struct niu *np)
4200{
4201 u64 min, max;
4202
4203 min = 64;
4204 if (np->dev->mtu > ETH_DATA_LEN)
4205 max = 9216;
4206 else
4207 max = 1522;
4208
4209 /* The XMAC_MIN register only accepts values for TX min which
4210 * have the low 3 bits cleared.
4211 */
4212 BUILD_BUG_ON(min & 0x7);
4213
4214 if (np->flags & NIU_FLAGS_XMAC)
4215 niu_init_tx_xmac(np, min, max);
4216 else
4217 niu_init_tx_bmac(np, min, max);
4218}
4219
4220static int niu_reset_rx_xmac(struct niu *np)
4221{
4222 int limit;
4223
4224 nw64_mac(XRXMAC_SW_RST,
4225 XRXMAC_SW_RST_REG_RS | XRXMAC_SW_RST_SOFT_RST);
4226 limit = 1000;
4227 while (--limit >= 0) {
4228 if (!(nr64_mac(XRXMAC_SW_RST) & (XRXMAC_SW_RST_REG_RS |
4229 XRXMAC_SW_RST_SOFT_RST)))
4230 break;
4231 udelay(100);
4232 }
4233 if (limit < 0) {
4234 dev_err(np->device, PFX "Port %u RX XMAC would not reset, "
4235 "XRXMAC_SW_RST[%llx]\n",
4236 np->port,
4237 (unsigned long long) nr64_mac(XRXMAC_SW_RST));
4238 return -ENODEV;
4239 }
4240
4241 return 0;
4242}
4243
4244static int niu_reset_rx_bmac(struct niu *np)
4245{
4246 int limit;
4247
4248 nw64_mac(BRXMAC_SW_RST, BRXMAC_SW_RST_RESET);
4249 limit = 1000;
4250 while (--limit >= 0) {
4251 if (!(nr64_mac(BRXMAC_SW_RST) & BRXMAC_SW_RST_RESET))
4252 break;
4253 udelay(100);
4254 }
4255 if (limit < 0) {
4256 dev_err(np->device, PFX "Port %u RX BMAC would not reset, "
4257 "BRXMAC_SW_RST[%llx]\n",
4258 np->port,
4259 (unsigned long long) nr64_mac(BRXMAC_SW_RST));
4260 return -ENODEV;
4261 }
4262
4263 return 0;
4264}
4265
4266static int niu_reset_rx_mac(struct niu *np)
4267{
4268 if (np->flags & NIU_FLAGS_XMAC)
4269 return niu_reset_rx_xmac(np);
4270 else
4271 return niu_reset_rx_bmac(np);
4272}
4273
4274static void niu_init_rx_xmac(struct niu *np)
4275{
4276 struct niu_parent *parent = np->parent;
4277 struct niu_rdc_tables *tp = &parent->rdc_group_cfg[np->port];
4278 int first_rdc_table = tp->first_table_num;
4279 unsigned long i;
4280 u64 val;
4281
4282 nw64_mac(XMAC_ADD_FILT0, 0);
4283 nw64_mac(XMAC_ADD_FILT1, 0);
4284 nw64_mac(XMAC_ADD_FILT2, 0);
4285 nw64_mac(XMAC_ADD_FILT12_MASK, 0);
4286 nw64_mac(XMAC_ADD_FILT00_MASK, 0);
4287 for (i = 0; i < MAC_NUM_HASH; i++)
4288 nw64_mac(XMAC_HASH_TBL(i), 0);
4289 nw64_mac(XRXMAC_STAT_MSK, ~(u64)0);
4290 niu_set_primary_mac_rdc_table(np, first_rdc_table, 1);
4291 niu_set_multicast_mac_rdc_table(np, first_rdc_table, 1);
4292
4293 val = nr64_mac(XMAC_CONFIG);
4294 val &= ~(XMAC_CONFIG_RX_MAC_ENABLE |
4295 XMAC_CONFIG_PROMISCUOUS |
4296 XMAC_CONFIG_PROMISC_GROUP |
4297 XMAC_CONFIG_ERR_CHK_DIS |
4298 XMAC_CONFIG_RX_CRC_CHK_DIS |
4299 XMAC_CONFIG_RESERVED_MULTICAST |
4300 XMAC_CONFIG_RX_CODEV_CHK_DIS |
4301 XMAC_CONFIG_ADDR_FILTER_EN |
4302 XMAC_CONFIG_RCV_PAUSE_ENABLE |
4303 XMAC_CONFIG_STRIP_CRC |
4304 XMAC_CONFIG_PASS_FLOW_CTRL |
4305 XMAC_CONFIG_MAC2IPP_PKT_CNT_EN);
4306 val |= (XMAC_CONFIG_HASH_FILTER_EN);
4307 nw64_mac(XMAC_CONFIG, val);
4308
4309 nw64_mac(RXMAC_BT_CNT, 0);
4310 nw64_mac(RXMAC_BC_FRM_CNT, 0);
4311 nw64_mac(RXMAC_MC_FRM_CNT, 0);
4312 nw64_mac(RXMAC_FRAG_CNT, 0);
4313 nw64_mac(RXMAC_HIST_CNT1, 0);
4314 nw64_mac(RXMAC_HIST_CNT2, 0);
4315 nw64_mac(RXMAC_HIST_CNT3, 0);
4316 nw64_mac(RXMAC_HIST_CNT4, 0);
4317 nw64_mac(RXMAC_HIST_CNT5, 0);
4318 nw64_mac(RXMAC_HIST_CNT6, 0);
4319 nw64_mac(RXMAC_HIST_CNT7, 0);
4320 nw64_mac(RXMAC_MPSZER_CNT, 0);
4321 nw64_mac(RXMAC_CRC_ER_CNT, 0);
4322 nw64_mac(RXMAC_CD_VIO_CNT, 0);
4323 nw64_mac(LINK_FAULT_CNT, 0);
4324}
4325
4326static void niu_init_rx_bmac(struct niu *np)
4327{
4328 struct niu_parent *parent = np->parent;
4329 struct niu_rdc_tables *tp = &parent->rdc_group_cfg[np->port];
4330 int first_rdc_table = tp->first_table_num;
4331 unsigned long i;
4332 u64 val;
4333
4334 nw64_mac(BMAC_ADD_FILT0, 0);
4335 nw64_mac(BMAC_ADD_FILT1, 0);
4336 nw64_mac(BMAC_ADD_FILT2, 0);
4337 nw64_mac(BMAC_ADD_FILT12_MASK, 0);
4338 nw64_mac(BMAC_ADD_FILT00_MASK, 0);
4339 for (i = 0; i < MAC_NUM_HASH; i++)
4340 nw64_mac(BMAC_HASH_TBL(i), 0);
4341 niu_set_primary_mac_rdc_table(np, first_rdc_table, 1);
4342 niu_set_multicast_mac_rdc_table(np, first_rdc_table, 1);
4343 nw64_mac(BRXMAC_STATUS_MASK, ~(u64)0);
4344
4345 val = nr64_mac(BRXMAC_CONFIG);
4346 val &= ~(BRXMAC_CONFIG_ENABLE |
4347 BRXMAC_CONFIG_STRIP_PAD |
4348 BRXMAC_CONFIG_STRIP_FCS |
4349 BRXMAC_CONFIG_PROMISC |
4350 BRXMAC_CONFIG_PROMISC_GRP |
4351 BRXMAC_CONFIG_ADDR_FILT_EN |
4352 BRXMAC_CONFIG_DISCARD_DIS);
4353 val |= (BRXMAC_CONFIG_HASH_FILT_EN);
4354 nw64_mac(BRXMAC_CONFIG, val);
4355
4356 val = nr64_mac(BMAC_ADDR_CMPEN);
4357 val |= BMAC_ADDR_CMPEN_EN0;
4358 nw64_mac(BMAC_ADDR_CMPEN, val);
4359}
4360
4361static void niu_init_rx_mac(struct niu *np)
4362{
4363 niu_set_primary_mac(np, np->dev->dev_addr);
4364
4365 if (np->flags & NIU_FLAGS_XMAC)
4366 niu_init_rx_xmac(np);
4367 else
4368 niu_init_rx_bmac(np);
4369}
4370
4371static void niu_enable_tx_xmac(struct niu *np, int on)
4372{
4373 u64 val = nr64_mac(XMAC_CONFIG);
4374
4375 if (on)
4376 val |= XMAC_CONFIG_TX_ENABLE;
4377 else
4378 val &= ~XMAC_CONFIG_TX_ENABLE;
4379 nw64_mac(XMAC_CONFIG, val);
4380}
4381
4382static void niu_enable_tx_bmac(struct niu *np, int on)
4383{
4384 u64 val = nr64_mac(BTXMAC_CONFIG);
4385
4386 if (on)
4387 val |= BTXMAC_CONFIG_ENABLE;
4388 else
4389 val &= ~BTXMAC_CONFIG_ENABLE;
4390 nw64_mac(BTXMAC_CONFIG, val);
4391}
4392
4393static void niu_enable_tx_mac(struct niu *np, int on)
4394{
4395 if (np->flags & NIU_FLAGS_XMAC)
4396 niu_enable_tx_xmac(np, on);
4397 else
4398 niu_enable_tx_bmac(np, on);
4399}
4400
4401static void niu_enable_rx_xmac(struct niu *np, int on)
4402{
4403 u64 val = nr64_mac(XMAC_CONFIG);
4404
4405 val &= ~(XMAC_CONFIG_HASH_FILTER_EN |
4406 XMAC_CONFIG_PROMISCUOUS);
4407
4408 if (np->flags & NIU_FLAGS_MCAST)
4409 val |= XMAC_CONFIG_HASH_FILTER_EN;
4410 if (np->flags & NIU_FLAGS_PROMISC)
4411 val |= XMAC_CONFIG_PROMISCUOUS;
4412
4413 if (on)
4414 val |= XMAC_CONFIG_RX_MAC_ENABLE;
4415 else
4416 val &= ~XMAC_CONFIG_RX_MAC_ENABLE;
4417 nw64_mac(XMAC_CONFIG, val);
4418}
4419
4420static void niu_enable_rx_bmac(struct niu *np, int on)
4421{
4422 u64 val = nr64_mac(BRXMAC_CONFIG);
4423
4424 val &= ~(BRXMAC_CONFIG_HASH_FILT_EN |
4425 BRXMAC_CONFIG_PROMISC);
4426
4427 if (np->flags & NIU_FLAGS_MCAST)
4428 val |= BRXMAC_CONFIG_HASH_FILT_EN;
4429 if (np->flags & NIU_FLAGS_PROMISC)
4430 val |= BRXMAC_CONFIG_PROMISC;
4431
4432 if (on)
4433 val |= BRXMAC_CONFIG_ENABLE;
4434 else
4435 val &= ~BRXMAC_CONFIG_ENABLE;
4436 nw64_mac(BRXMAC_CONFIG, val);
4437}
4438
4439static void niu_enable_rx_mac(struct niu *np, int on)
4440{
4441 if (np->flags & NIU_FLAGS_XMAC)
4442 niu_enable_rx_xmac(np, on);
4443 else
4444 niu_enable_rx_bmac(np, on);
4445}
4446
4447static int niu_init_mac(struct niu *np)
4448{
4449 int err;
4450
4451 niu_init_xif(np);
4452 err = niu_init_pcs(np);
4453 if (err)
4454 return err;
4455
4456 err = niu_reset_tx_mac(np);
4457 if (err)
4458 return err;
4459 niu_init_tx_mac(np);
4460 err = niu_reset_rx_mac(np);
4461 if (err)
4462 return err;
4463 niu_init_rx_mac(np);
4464
4465 /* This looks hookey but the RX MAC reset we just did will
4466 * undo some of the state we setup in niu_init_tx_mac() so we
4467 * have to call it again. In particular, the RX MAC reset will
4468 * set the XMAC_MAX register back to it's default value.
4469 */
4470 niu_init_tx_mac(np);
4471 niu_enable_tx_mac(np, 1);
4472
4473 niu_enable_rx_mac(np, 1);
4474
4475 return 0;
4476}
4477
4478static void niu_stop_one_tx_channel(struct niu *np, struct tx_ring_info *rp)
4479{
4480 (void) niu_tx_channel_stop(np, rp->tx_channel);
4481}
4482
4483static void niu_stop_tx_channels(struct niu *np)
4484{
4485 int i;
4486
4487 for (i = 0; i < np->num_tx_rings; i++) {
4488 struct tx_ring_info *rp = &np->tx_rings[i];
4489
4490 niu_stop_one_tx_channel(np, rp);
4491 }
4492}
4493
4494static void niu_reset_one_tx_channel(struct niu *np, struct tx_ring_info *rp)
4495{
4496 (void) niu_tx_channel_reset(np, rp->tx_channel);
4497}
4498
4499static void niu_reset_tx_channels(struct niu *np)
4500{
4501 int i;
4502
4503 for (i = 0; i < np->num_tx_rings; i++) {
4504 struct tx_ring_info *rp = &np->tx_rings[i];
4505
4506 niu_reset_one_tx_channel(np, rp);
4507 }
4508}
4509
4510static void niu_stop_one_rx_channel(struct niu *np, struct rx_ring_info *rp)
4511{
4512 (void) niu_enable_rx_channel(np, rp->rx_channel, 0);
4513}
4514
4515static void niu_stop_rx_channels(struct niu *np)
4516{
4517 int i;
4518
4519 for (i = 0; i < np->num_rx_rings; i++) {
4520 struct rx_ring_info *rp = &np->rx_rings[i];
4521
4522 niu_stop_one_rx_channel(np, rp);
4523 }
4524}
4525
4526static void niu_reset_one_rx_channel(struct niu *np, struct rx_ring_info *rp)
4527{
4528 int channel = rp->rx_channel;
4529
4530 (void) niu_rx_channel_reset(np, channel);
4531 nw64(RX_DMA_ENT_MSK(channel), RX_DMA_ENT_MSK_ALL);
4532 nw64(RX_DMA_CTL_STAT(channel), 0);
4533 (void) niu_enable_rx_channel(np, channel, 0);
4534}
4535
4536static void niu_reset_rx_channels(struct niu *np)
4537{
4538 int i;
4539
4540 for (i = 0; i < np->num_rx_rings; i++) {
4541 struct rx_ring_info *rp = &np->rx_rings[i];
4542
4543 niu_reset_one_rx_channel(np, rp);
4544 }
4545}
4546
4547static void niu_disable_ipp(struct niu *np)
4548{
4549 u64 rd, wr, val;
4550 int limit;
4551
4552 rd = nr64_ipp(IPP_DFIFO_RD_PTR);
4553 wr = nr64_ipp(IPP_DFIFO_WR_PTR);
4554 limit = 100;
4555 while (--limit >= 0 && (rd != wr)) {
4556 rd = nr64_ipp(IPP_DFIFO_RD_PTR);
4557 wr = nr64_ipp(IPP_DFIFO_WR_PTR);
4558 }
4559 if (limit < 0 &&
4560 (rd != 0 && wr != 1)) {
4561 dev_err(np->device, PFX "%s: IPP would not quiesce, "
4562 "rd_ptr[%llx] wr_ptr[%llx]\n",
4563 np->dev->name,
4564 (unsigned long long) nr64_ipp(IPP_DFIFO_RD_PTR),
4565 (unsigned long long) nr64_ipp(IPP_DFIFO_WR_PTR));
4566 }
4567
4568 val = nr64_ipp(IPP_CFIG);
4569 val &= ~(IPP_CFIG_IPP_ENABLE |
4570 IPP_CFIG_DFIFO_ECC_EN |
4571 IPP_CFIG_DROP_BAD_CRC |
4572 IPP_CFIG_CKSUM_EN);
4573 nw64_ipp(IPP_CFIG, val);
4574
4575 (void) niu_ipp_reset(np);
4576}
4577
4578static int niu_init_hw(struct niu *np)
4579{
4580 int i, err;
4581
4582 niudbg(IFUP, "%s: Initialize TXC\n", np->dev->name);
4583 niu_txc_enable_port(np, 1);
4584 niu_txc_port_dma_enable(np, 1);
4585 niu_txc_set_imask(np, 0);
4586
4587 niudbg(IFUP, "%s: Initialize TX channels\n", np->dev->name);
4588 for (i = 0; i < np->num_tx_rings; i++) {
4589 struct tx_ring_info *rp = &np->tx_rings[i];
4590
4591 err = niu_init_one_tx_channel(np, rp);
4592 if (err)
4593 return err;
4594 }
4595
4596 niudbg(IFUP, "%s: Initialize RX channels\n", np->dev->name);
4597 err = niu_init_rx_channels(np);
4598 if (err)
4599 goto out_uninit_tx_channels;
4600
4601 niudbg(IFUP, "%s: Initialize classifier\n", np->dev->name);
4602 err = niu_init_classifier_hw(np);
4603 if (err)
4604 goto out_uninit_rx_channels;
4605
4606 niudbg(IFUP, "%s: Initialize ZCP\n", np->dev->name);
4607 err = niu_init_zcp(np);
4608 if (err)
4609 goto out_uninit_rx_channels;
4610
4611 niudbg(IFUP, "%s: Initialize IPP\n", np->dev->name);
4612 err = niu_init_ipp(np);
4613 if (err)
4614 goto out_uninit_rx_channels;
4615
4616 niudbg(IFUP, "%s: Initialize MAC\n", np->dev->name);
4617 err = niu_init_mac(np);
4618 if (err)
4619 goto out_uninit_ipp;
4620
4621 return 0;
4622
4623out_uninit_ipp:
4624 niudbg(IFUP, "%s: Uninit IPP\n", np->dev->name);
4625 niu_disable_ipp(np);
4626
4627out_uninit_rx_channels:
4628 niudbg(IFUP, "%s: Uninit RX channels\n", np->dev->name);
4629 niu_stop_rx_channels(np);
4630 niu_reset_rx_channels(np);
4631
4632out_uninit_tx_channels:
4633 niudbg(IFUP, "%s: Uninit TX channels\n", np->dev->name);
4634 niu_stop_tx_channels(np);
4635 niu_reset_tx_channels(np);
4636
4637 return err;
4638}
4639
4640static void niu_stop_hw(struct niu *np)
4641{
4642 niudbg(IFDOWN, "%s: Disable interrupts\n", np->dev->name);
4643 niu_enable_interrupts(np, 0);
4644
4645 niudbg(IFDOWN, "%s: Disable RX MAC\n", np->dev->name);
4646 niu_enable_rx_mac(np, 0);
4647
4648 niudbg(IFDOWN, "%s: Disable IPP\n", np->dev->name);
4649 niu_disable_ipp(np);
4650
4651 niudbg(IFDOWN, "%s: Stop TX channels\n", np->dev->name);
4652 niu_stop_tx_channels(np);
4653
4654 niudbg(IFDOWN, "%s: Stop RX channels\n", np->dev->name);
4655 niu_stop_rx_channels(np);
4656
4657 niudbg(IFDOWN, "%s: Reset TX channels\n", np->dev->name);
4658 niu_reset_tx_channels(np);
4659
4660 niudbg(IFDOWN, "%s: Reset RX channels\n", np->dev->name);
4661 niu_reset_rx_channels(np);
4662}
4663
4664static int niu_request_irq(struct niu *np)
4665{
4666 int i, j, err;
4667
4668 err = 0;
4669 for (i = 0; i < np->num_ldg; i++) {
4670 struct niu_ldg *lp = &np->ldg[i];
4671
4672 err = request_irq(lp->irq, niu_interrupt,
4673 IRQF_SHARED | IRQF_SAMPLE_RANDOM,
4674 np->dev->name, lp);
4675 if (err)
4676 goto out_free_irqs;
4677
4678 }
4679
4680 return 0;
4681
4682out_free_irqs:
4683 for (j = 0; j < i; j++) {
4684 struct niu_ldg *lp = &np->ldg[j];
4685
4686 free_irq(lp->irq, lp);
4687 }
4688 return err;
4689}
4690
4691static void niu_free_irq(struct niu *np)
4692{
4693 int i;
4694
4695 for (i = 0; i < np->num_ldg; i++) {
4696 struct niu_ldg *lp = &np->ldg[i];
4697
4698 free_irq(lp->irq, lp);
4699 }
4700}
4701
4702static void niu_enable_napi(struct niu *np)
4703{
4704 int i;
4705
4706 for (i = 0; i < np->num_ldg; i++)
4707 napi_enable(&np->ldg[i].napi);
4708}
4709
4710static void niu_disable_napi(struct niu *np)
4711{
4712 int i;
4713
4714 for (i = 0; i < np->num_ldg; i++)
4715 napi_disable(&np->ldg[i].napi);
4716}
4717
4718static int niu_open(struct net_device *dev)
4719{
4720 struct niu *np = netdev_priv(dev);
4721 int err;
4722
4723 netif_carrier_off(dev);
4724
4725 err = niu_alloc_channels(np);
4726 if (err)
4727 goto out_err;
4728
4729 err = niu_enable_interrupts(np, 0);
4730 if (err)
4731 goto out_free_channels;
4732
4733 err = niu_request_irq(np);
4734 if (err)
4735 goto out_free_channels;
4736
4737 niu_enable_napi(np);
4738
4739 spin_lock_irq(&np->lock);
4740
4741 err = niu_init_hw(np);
4742 if (!err) {
4743 init_timer(&np->timer);
4744 np->timer.expires = jiffies + HZ;
4745 np->timer.data = (unsigned long) np;
4746 np->timer.function = niu_timer;
4747
4748 err = niu_enable_interrupts(np, 1);
4749 if (err)
4750 niu_stop_hw(np);
4751 }
4752
4753 spin_unlock_irq(&np->lock);
4754
4755 if (err) {
4756 niu_disable_napi(np);
4757 goto out_free_irq;
4758 }
4759
4760 netif_start_queue(dev);
4761
4762 if (np->link_config.loopback_mode != LOOPBACK_DISABLED)
4763 netif_carrier_on(dev);
4764
4765 add_timer(&np->timer);
4766
4767 return 0;
4768
4769out_free_irq:
4770 niu_free_irq(np);
4771
4772out_free_channels:
4773 niu_free_channels(np);
4774
4775out_err:
4776 return err;
4777}
4778
4779static void niu_full_shutdown(struct niu *np, struct net_device *dev)
4780{
4781 cancel_work_sync(&np->reset_task);
4782
4783 niu_disable_napi(np);
4784 netif_stop_queue(dev);
4785
4786 del_timer_sync(&np->timer);
4787
4788 spin_lock_irq(&np->lock);
4789
4790 niu_stop_hw(np);
4791
4792 spin_unlock_irq(&np->lock);
4793}
4794
4795static int niu_close(struct net_device *dev)
4796{
4797 struct niu *np = netdev_priv(dev);
4798
4799 niu_full_shutdown(np, dev);
4800
4801 niu_free_irq(np);
4802
4803 niu_free_channels(np);
4804
Mirko Lindner0c3b0912007-12-05 21:10:02 -0800[diff] [blame]4805 niu_handle_led(np, 0);
4806
David S. Millera3138df2007-10-09 01:54:01 -0700[diff] [blame]4807 return 0;
4808}
4809
4810static void niu_sync_xmac_stats(struct niu *np)
4811{
4812 struct niu_xmac_stats *mp = &np->mac_stats.xmac;
4813
4814 mp->tx_frames += nr64_mac(TXMAC_FRM_CNT);
4815 mp->tx_bytes += nr64_mac(TXMAC_BYTE_CNT);
4816
4817 mp->rx_link_faults += nr64_mac(LINK_FAULT_CNT);
4818 mp->rx_align_errors += nr64_mac(RXMAC_ALIGN_ERR_CNT);
4819 mp->rx_frags += nr64_mac(RXMAC_FRAG_CNT);
4820 mp->rx_mcasts += nr64_mac(RXMAC_MC_FRM_CNT);
4821 mp->rx_bcasts += nr64_mac(RXMAC_BC_FRM_CNT);
4822 mp->rx_hist_cnt1 += nr64_mac(RXMAC_HIST_CNT1);
4823 mp->rx_hist_cnt2 += nr64_mac(RXMAC_HIST_CNT2);
4824 mp->rx_hist_cnt3 += nr64_mac(RXMAC_HIST_CNT3);
4825 mp->rx_hist_cnt4 += nr64_mac(RXMAC_HIST_CNT4);
4826 mp->rx_hist_cnt5 += nr64_mac(RXMAC_HIST_CNT5);
4827 mp->rx_hist_cnt6 += nr64_mac(RXMAC_HIST_CNT6);
4828 mp->rx_hist_cnt7 += nr64_mac(RXMAC_HIST_CNT7);
4829 mp->rx_octets += nr64_mac(RXMAC_BT_CNT);
4830 mp->rx_code_violations += nr64_mac(RXMAC_CD_VIO_CNT);
4831 mp->rx_len_errors += nr64_mac(RXMAC_MPSZER_CNT);
4832 mp->rx_crc_errors += nr64_mac(RXMAC_CRC_ER_CNT);
4833}
4834
4835static void niu_sync_bmac_stats(struct niu *np)
4836{
4837 struct niu_bmac_stats *mp = &np->mac_stats.bmac;
4838
4839 mp->tx_bytes += nr64_mac(BTXMAC_BYTE_CNT);
4840 mp->tx_frames += nr64_mac(BTXMAC_FRM_CNT);
4841
4842 mp->rx_frames += nr64_mac(BRXMAC_FRAME_CNT);
4843 mp->rx_align_errors += nr64_mac(BRXMAC_ALIGN_ERR_CNT);
4844 mp->rx_crc_errors += nr64_mac(BRXMAC_ALIGN_ERR_CNT);
4845 mp->rx_len_errors += nr64_mac(BRXMAC_CODE_VIOL_ERR_CNT);
4846}
4847
4848static void niu_sync_mac_stats(struct niu *np)
4849{
4850 if (np->flags & NIU_FLAGS_XMAC)
4851 niu_sync_xmac_stats(np);
4852 else
4853 niu_sync_bmac_stats(np);
4854}
4855
4856static void niu_get_rx_stats(struct niu *np)
4857{
4858 unsigned long pkts, dropped, errors, bytes;
4859 int i;
4860
4861 pkts = dropped = errors = bytes = 0;
4862 for (i = 0; i < np->num_rx_rings; i++) {
4863 struct rx_ring_info *rp = &np->rx_rings[i];
4864
4865 pkts += rp->rx_packets;
4866 bytes += rp->rx_bytes;
4867 dropped += rp->rx_dropped;
4868 errors += rp->rx_errors;
4869 }
4870 np->net_stats.rx_packets = pkts;
4871 np->net_stats.rx_bytes = bytes;
4872 np->net_stats.rx_dropped = dropped;
4873 np->net_stats.rx_errors = errors;
4874}
4875
4876static void niu_get_tx_stats(struct niu *np)
4877{
4878 unsigned long pkts, errors, bytes;
4879 int i;
4880
4881 pkts = errors = bytes = 0;
4882 for (i = 0; i < np->num_tx_rings; i++) {
4883 struct tx_ring_info *rp = &np->tx_rings[i];
4884
4885 pkts += rp->tx_packets;
4886 bytes += rp->tx_bytes;
4887 errors += rp->tx_errors;
4888 }
4889 np->net_stats.tx_packets = pkts;
4890 np->net_stats.tx_bytes = bytes;
4891 np->net_stats.tx_errors = errors;
4892}
4893
4894static struct net_device_stats *niu_get_stats(struct net_device *dev)
4895{
4896 struct niu *np = netdev_priv(dev);
4897
4898 niu_get_rx_stats(np);
4899 niu_get_tx_stats(np);
4900
4901 return &np->net_stats;
4902}
4903
4904static void niu_load_hash_xmac(struct niu *np, u16 *hash)
4905{
4906 int i;
4907
4908 for (i = 0; i < 16; i++)
4909 nw64_mac(XMAC_HASH_TBL(i), hash[i]);
4910}
4911
4912static void niu_load_hash_bmac(struct niu *np, u16 *hash)
4913{
4914 int i;
4915
4916 for (i = 0; i < 16; i++)
4917 nw64_mac(BMAC_HASH_TBL(i), hash[i]);
4918}
4919
4920static void niu_load_hash(struct niu *np, u16 *hash)
4921{
4922 if (np->flags & NIU_FLAGS_XMAC)
4923 niu_load_hash_xmac(np, hash);
4924 else
4925 niu_load_hash_bmac(np, hash);
4926}
4927
4928static void niu_set_rx_mode(struct net_device *dev)
4929{
4930 struct niu *np = netdev_priv(dev);
4931 int i, alt_cnt, err;
4932 struct dev_addr_list *addr;
4933 unsigned long flags;
4934 u16 hash[16] = { 0, };
4935
4936 spin_lock_irqsave(&np->lock, flags);
4937 niu_enable_rx_mac(np, 0);
4938
4939 np->flags &= ~(NIU_FLAGS_MCAST | NIU_FLAGS_PROMISC);
4940 if (dev->flags & IFF_PROMISC)
4941 np->flags |= NIU_FLAGS_PROMISC;
4942 if ((dev->flags & IFF_ALLMULTI) || (dev->mc_count > 0))
4943 np->flags |= NIU_FLAGS_MCAST;
4944
4945 alt_cnt = dev->uc_count;
4946 if (alt_cnt > niu_num_alt_addr(np)) {
4947 alt_cnt = 0;
4948 np->flags |= NIU_FLAGS_PROMISC;
4949 }
4950
4951 if (alt_cnt) {
4952 int index = 0;
4953
4954 for (addr = dev->uc_list; addr; addr = addr->next) {
4955 err = niu_set_alt_mac(np, index,
4956 addr->da_addr);
4957 if (err)
4958 printk(KERN_WARNING PFX "%s: Error %d "
4959 "adding alt mac %d\n",
4960 dev->name, err, index);
4961 err = niu_enable_alt_mac(np, index, 1);
4962 if (err)
4963 printk(KERN_WARNING PFX "%s: Error %d "
4964 "enabling alt mac %d\n",
4965 dev->name, err, index);
4966
4967 index++;
4968 }
4969 } else {
4970 for (i = 0; i < niu_num_alt_addr(np); i++) {
4971 err = niu_enable_alt_mac(np, i, 0);
4972 if (err)
4973 printk(KERN_WARNING PFX "%s: Error %d "
4974 "disabling alt mac %d\n",
4975 dev->name, err, i);
4976 }
4977 }
4978 if (dev->flags & IFF_ALLMULTI) {
4979 for (i = 0; i < 16; i++)
4980 hash[i] = 0xffff;
4981 } else if (dev->mc_count > 0) {
4982 for (addr = dev->mc_list; addr; addr = addr->next) {
4983 u32 crc = ether_crc_le(ETH_ALEN, addr->da_addr);
4984
4985 crc >>= 24;
4986 hash[crc >> 4] |= (1 << (15 - (crc & 0xf)));
4987 }
4988 }
4989
4990 if (np->flags & NIU_FLAGS_MCAST)
4991 niu_load_hash(np, hash);
4992
4993 niu_enable_rx_mac(np, 1);
4994 spin_unlock_irqrestore(&np->lock, flags);
4995}
4996
4997static int niu_set_mac_addr(struct net_device *dev, void *p)
4998{
4999 struct niu *np = netdev_priv(dev);
5000 struct sockaddr *addr = p;
5001 unsigned long flags;
5002
5003 if (!is_valid_ether_addr(addr->sa_data))
5004 return -EINVAL;
5005
5006 memcpy(dev->dev_addr, addr->sa_data, ETH_ALEN);
5007
5008 if (!netif_running(dev))
5009 return 0;
5010
5011 spin_lock_irqsave(&np->lock, flags);
5012 niu_enable_rx_mac(np, 0);
5013 niu_set_primary_mac(np, dev->dev_addr);
5014 niu_enable_rx_mac(np, 1);
5015 spin_unlock_irqrestore(&np->lock, flags);
5016
5017 return 0;
5018}
5019
5020static int niu_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
5021{
5022 return -EOPNOTSUPP;
5023}
5024
5025static void niu_netif_stop(struct niu *np)
5026{
5027 np->dev->trans_start = jiffies; /* prevent tx timeout */
5028
5029 niu_disable_napi(np);
5030
5031 netif_tx_disable(np->dev);
5032}
5033
5034static void niu_netif_start(struct niu *np)
5035{
5036 /* NOTE: unconditional netif_wake_queue is only appropriate
5037 * so long as all callers are assured to have free tx slots
5038 * (such as after niu_init_hw).
5039 */
5040 netif_wake_queue(np->dev);
5041
5042 niu_enable_napi(np);
5043
5044 niu_enable_interrupts(np, 1);
5045}
5046
5047static void niu_reset_task(struct work_struct *work)
5048{
5049 struct niu *np = container_of(work, struct niu, reset_task);
5050 unsigned long flags;
5051 int err;
5052
5053 spin_lock_irqsave(&np->lock, flags);
5054 if (!netif_running(np->dev)) {
5055 spin_unlock_irqrestore(&np->lock, flags);
5056 return;
5057 }
5058
5059 spin_unlock_irqrestore(&np->lock, flags);
5060
5061 del_timer_sync(&np->timer);
5062
5063 niu_netif_stop(np);
5064
5065 spin_lock_irqsave(&np->lock, flags);
5066
5067 niu_stop_hw(np);
5068
5069 err = niu_init_hw(np);
5070 if (!err) {
5071 np->timer.expires = jiffies + HZ;
5072 add_timer(&np->timer);
5073 niu_netif_start(np);
5074 }
5075
5076 spin_unlock_irqrestore(&np->lock, flags);
5077}
5078
5079static void niu_tx_timeout(struct net_device *dev)
5080{
5081 struct niu *np = netdev_priv(dev);
5082
5083 dev_err(np->device, PFX "%s: Transmit timed out, resetting\n",
5084 dev->name);
5085
5086 schedule_work(&np->reset_task);
5087}
5088
5089static void niu_set_txd(struct tx_ring_info *rp, int index,
5090 u64 mapping, u64 len, u64 mark,
5091 u64 n_frags)
5092{
5093 __le64 *desc = &rp->descr[index];
5094
5095 *desc = cpu_to_le64(mark |
5096 (n_frags << TX_DESC_NUM_PTR_SHIFT) |
5097 (len << TX_DESC_TR_LEN_SHIFT) |
5098 (mapping & TX_DESC_SAD));
5099}
5100
5101static u64 niu_compute_tx_flags(struct sk_buff *skb, struct ethhdr *ehdr,
5102 u64 pad_bytes, u64 len)
5103{
5104 u16 eth_proto, eth_proto_inner;
5105 u64 csum_bits, l3off, ihl, ret;
5106 u8 ip_proto;
5107 int ipv6;
5108
5109 eth_proto = be16_to_cpu(ehdr->h_proto);
5110 eth_proto_inner = eth_proto;
5111 if (eth_proto == ETH_P_8021Q) {
5112 struct vlan_ethhdr *vp = (struct vlan_ethhdr *) ehdr;
5113 __be16 val = vp->h_vlan_encapsulated_proto;
5114
5115 eth_proto_inner = be16_to_cpu(val);
5116 }
5117
5118 ipv6 = ihl = 0;
5119 switch (skb->protocol) {
5120 case __constant_htons(ETH_P_IP):
5121 ip_proto = ip_hdr(skb)->protocol;
5122 ihl = ip_hdr(skb)->ihl;
5123 break;
5124 case __constant_htons(ETH_P_IPV6):
5125 ip_proto = ipv6_hdr(skb)->nexthdr;
5126 ihl = (40 >> 2);
5127 ipv6 = 1;
5128 break;
5129 default:
5130 ip_proto = ihl = 0;
5131 break;
5132 }
5133
5134 csum_bits = TXHDR_CSUM_NONE;
5135 if (skb->ip_summed == CHECKSUM_PARTIAL) {
5136 u64 start, stuff;
5137
5138 csum_bits = (ip_proto == IPPROTO_TCP ?
5139 TXHDR_CSUM_TCP :
5140 (ip_proto == IPPROTO_UDP ?
5141 TXHDR_CSUM_UDP : TXHDR_CSUM_SCTP));
5142
5143 start = skb_transport_offset(skb) -
5144 (pad_bytes + sizeof(struct tx_pkt_hdr));
5145 stuff = start + skb->csum_offset;
5146
5147 csum_bits |= (start / 2) << TXHDR_L4START_SHIFT;
5148 csum_bits |= (stuff / 2) << TXHDR_L4STUFF_SHIFT;
5149 }
5150
5151 l3off = skb_network_offset(skb) -
5152 (pad_bytes + sizeof(struct tx_pkt_hdr));
5153
5154 ret = (((pad_bytes / 2) << TXHDR_PAD_SHIFT) |
5155 (len << TXHDR_LEN_SHIFT) |
5156 ((l3off / 2) << TXHDR_L3START_SHIFT) |
5157 (ihl << TXHDR_IHL_SHIFT) |
5158 ((eth_proto_inner < 1536) ? TXHDR_LLC : 0) |
5159 ((eth_proto == ETH_P_8021Q) ? TXHDR_VLAN : 0) |
5160 (ipv6 ? TXHDR_IP_VER : 0) |
5161 csum_bits);
5162
5163 return ret;
5164}
5165
5166static struct tx_ring_info *tx_ring_select(struct niu *np, struct sk_buff *skb)
5167{
5168 return &np->tx_rings[0];
5169}
5170
5171static int niu_start_xmit(struct sk_buff *skb, struct net_device *dev)
5172{
5173 struct niu *np = netdev_priv(dev);
5174 unsigned long align, headroom;
5175 struct tx_ring_info *rp;
5176 struct tx_pkt_hdr *tp;
5177 unsigned int len, nfg;
5178 struct ethhdr *ehdr;
5179 int prod, i, tlen;
5180 u64 mapping, mrk;
5181
5182 rp = tx_ring_select(np, skb);
5183
5184 if (niu_tx_avail(rp) <= (skb_shinfo(skb)->nr_frags + 1)) {
5185 netif_stop_queue(dev);
5186 dev_err(np->device, PFX "%s: BUG! Tx ring full when "
5187 "queue awake!\n", dev->name);
5188 rp->tx_errors++;
5189 return NETDEV_TX_BUSY;
5190 }
5191
5192 if (skb->len < ETH_ZLEN) {
5193 unsigned int pad_bytes = ETH_ZLEN - skb->len;
5194
5195 if (skb_pad(skb, pad_bytes))
5196 goto out;
5197 skb_put(skb, pad_bytes);
5198 }
5199
5200 len = sizeof(struct tx_pkt_hdr) + 15;
5201 if (skb_headroom(skb) < len) {
5202 struct sk_buff *skb_new;
5203
5204 skb_new = skb_realloc_headroom(skb, len);
5205 if (!skb_new) {
5206 rp->tx_errors++;
5207 goto out_drop;
5208 }
5209 kfree_skb(skb);
5210 skb = skb_new;
5211 }
5212
5213 align = ((unsigned long) skb->data & (16 - 1));
5214 headroom = align + sizeof(struct tx_pkt_hdr);
5215
5216 ehdr = (struct ethhdr *) skb->data;
5217 tp = (struct tx_pkt_hdr *) skb_push(skb, headroom);
5218
5219 len = skb->len - sizeof(struct tx_pkt_hdr);
5220 tp->flags = cpu_to_le64(niu_compute_tx_flags(skb, ehdr, align, len));
5221 tp->resv = 0;
5222
5223 len = skb_headlen(skb);
5224 mapping = np->ops->map_single(np->device, skb->data,
5225 len, DMA_TO_DEVICE);
5226
5227 prod = rp->prod;
5228
5229 rp->tx_buffs[prod].skb = skb;
5230 rp->tx_buffs[prod].mapping = mapping;
5231
5232 mrk = TX_DESC_SOP;
5233 if (++rp->mark_counter == rp->mark_freq) {
5234 rp->mark_counter = 0;
5235 mrk |= TX_DESC_MARK;
5236 rp->mark_pending++;
5237 }
5238
5239 tlen = len;
5240 nfg = skb_shinfo(skb)->nr_frags;
5241 while (tlen > 0) {
5242 tlen -= MAX_TX_DESC_LEN;
5243 nfg++;
5244 }
5245
5246 while (len > 0) {
5247 unsigned int this_len = len;
5248
5249 if (this_len > MAX_TX_DESC_LEN)
5250 this_len = MAX_TX_DESC_LEN;
5251
5252 niu_set_txd(rp, prod, mapping, this_len, mrk, nfg);
5253 mrk = nfg = 0;
5254
5255 prod = NEXT_TX(rp, prod);
5256 mapping += this_len;
5257 len -= this_len;
5258 }
5259
5260 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
5261 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
5262
5263 len = frag->size;
5264 mapping = np->ops->map_page(np->device, frag->page,
5265 frag->page_offset, len,
5266 DMA_TO_DEVICE);
5267
5268 rp->tx_buffs[prod].skb = NULL;
5269 rp->tx_buffs[prod].mapping = mapping;
5270
5271 niu_set_txd(rp, prod, mapping, len, 0, 0);
5272
5273 prod = NEXT_TX(rp, prod);
5274 }
5275
5276 if (prod < rp->prod)
5277 rp->wrap_bit ^= TX_RING_KICK_WRAP;
5278 rp->prod = prod;
5279
5280 nw64(TX_RING_KICK(rp->tx_channel), rp->wrap_bit | (prod << 3));
5281
5282 if (unlikely(niu_tx_avail(rp) <= (MAX_SKB_FRAGS + 1))) {
5283 netif_stop_queue(dev);
5284 if (niu_tx_avail(rp) > NIU_TX_WAKEUP_THRESH(rp))
5285 netif_wake_queue(dev);
5286 }
5287
5288 dev->trans_start = jiffies;
5289
5290out:
5291 return NETDEV_TX_OK;
5292
5293out_drop:
5294 rp->tx_errors++;
5295 kfree_skb(skb);
5296 goto out;
5297}
5298
5299static int niu_change_mtu(struct net_device *dev, int new_mtu)
5300{
5301 struct niu *np = netdev_priv(dev);
5302 int err, orig_jumbo, new_jumbo;
5303
5304 if (new_mtu < 68 || new_mtu > NIU_MAX_MTU)
5305 return -EINVAL;
5306
5307 orig_jumbo = (dev->mtu > ETH_DATA_LEN);
5308 new_jumbo = (new_mtu > ETH_DATA_LEN);
5309
5310 dev->mtu = new_mtu;
5311
5312 if (!netif_running(dev) ||
5313 (orig_jumbo == new_jumbo))
5314 return 0;
5315
5316 niu_full_shutdown(np, dev);
5317
5318 niu_free_channels(np);
5319
5320 niu_enable_napi(np);
5321
5322 err = niu_alloc_channels(np);
5323 if (err)
5324 return err;
5325
5326 spin_lock_irq(&np->lock);
5327
5328 err = niu_init_hw(np);
5329 if (!err) {
5330 init_timer(&np->timer);
5331 np->timer.expires = jiffies + HZ;
5332 np->timer.data = (unsigned long) np;
5333 np->timer.function = niu_timer;
5334
5335 err = niu_enable_interrupts(np, 1);
5336 if (err)
5337 niu_stop_hw(np);
5338 }
5339
5340 spin_unlock_irq(&np->lock);
5341
5342 if (!err) {
5343 netif_start_queue(dev);
5344 if (np->link_config.loopback_mode != LOOPBACK_DISABLED)
5345 netif_carrier_on(dev);
5346
5347 add_timer(&np->timer);
5348 }
5349
5350 return err;
5351}
5352
5353static void niu_get_drvinfo(struct net_device *dev,
5354 struct ethtool_drvinfo *info)
5355{
5356 struct niu *np = netdev_priv(dev);
5357 struct niu_vpd *vpd = &np->vpd;
5358
5359 strcpy(info->driver, DRV_MODULE_NAME);
5360 strcpy(info->version, DRV_MODULE_VERSION);
5361 sprintf(info->fw_version, "%d.%d",
5362 vpd->fcode_major, vpd->fcode_minor);
5363 if (np->parent->plat_type != PLAT_TYPE_NIU)
5364 strcpy(info->bus_info, pci_name(np->pdev));
5365}
5366
5367static int niu_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
5368{
5369 struct niu *np = netdev_priv(dev);
5370 struct niu_link_config *lp;
5371
5372 lp = &np->link_config;
5373
5374 memset(cmd, 0, sizeof(*cmd));
5375 cmd->phy_address = np->phy_addr;
5376 cmd->supported = lp->supported;
5377 cmd->advertising = lp->advertising;
5378 cmd->autoneg = lp->autoneg;
5379 cmd->speed = lp->active_speed;
5380 cmd->duplex = lp->active_duplex;
5381
5382 return 0;
5383}
5384
5385static int niu_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
5386{
5387 return -EINVAL;
5388}
5389
5390static u32 niu_get_msglevel(struct net_device *dev)
5391{
5392 struct niu *np = netdev_priv(dev);
5393 return np->msg_enable;
5394}
5395
5396static void niu_set_msglevel(struct net_device *dev, u32 value)
5397{
5398 struct niu *np = netdev_priv(dev);
5399 np->msg_enable = value;
5400}
5401
5402static int niu_get_eeprom_len(struct net_device *dev)
5403{
5404 struct niu *np = netdev_priv(dev);
5405
5406 return np->eeprom_len;
5407}
5408
5409static int niu_get_eeprom(struct net_device *dev,
5410 struct ethtool_eeprom *eeprom, u8 *data)
5411{
5412 struct niu *np = netdev_priv(dev);
5413 u32 offset, len, val;
5414
5415 offset = eeprom->offset;
5416 len = eeprom->len;
5417
5418 if (offset + len < offset)
5419 return -EINVAL;
5420 if (offset >= np->eeprom_len)
5421 return -EINVAL;
5422 if (offset + len > np->eeprom_len)
5423 len = eeprom->len = np->eeprom_len - offset;
5424
5425 if (offset & 3) {
5426 u32 b_offset, b_count;
5427
5428 b_offset = offset & 3;
5429 b_count = 4 - b_offset;
5430 if (b_count > len)
5431 b_count = len;
5432
5433 val = nr64(ESPC_NCR((offset - b_offset) / 4));
5434 memcpy(data, ((char *)&val) + b_offset, b_count);
5435 data += b_count;
5436 len -= b_count;
5437 offset += b_count;
5438 }
5439 while (len >= 4) {
5440 val = nr64(ESPC_NCR(offset / 4));
5441 memcpy(data, &val, 4);
5442 data += 4;
5443 len -= 4;
5444 offset += 4;
5445 }
5446 if (len) {
5447 val = nr64(ESPC_NCR(offset / 4));
5448 memcpy(data, &val, len);
5449 }
5450 return 0;
5451}
5452
5453static const struct {
5454 const char string[ETH_GSTRING_LEN];
5455} niu_xmac_stat_keys[] = {
5456 { "tx_frames" },
5457 { "tx_bytes" },
5458 { "tx_fifo_errors" },
5459 { "tx_overflow_errors" },
5460 { "tx_max_pkt_size_errors" },
5461 { "tx_underflow_errors" },
5462 { "rx_local_faults" },
5463 { "rx_remote_faults" },
5464 { "rx_link_faults" },
5465 { "rx_align_errors" },
5466 { "rx_frags" },
5467 { "rx_mcasts" },
5468 { "rx_bcasts" },
5469 { "rx_hist_cnt1" },
5470 { "rx_hist_cnt2" },
5471 { "rx_hist_cnt3" },
5472 { "rx_hist_cnt4" },
5473 { "rx_hist_cnt5" },
5474 { "rx_hist_cnt6" },
5475 { "rx_hist_cnt7" },
5476 { "rx_octets" },
5477 { "rx_code_violations" },
5478 { "rx_len_errors" },
5479 { "rx_crc_errors" },
5480 { "rx_underflows" },
5481 { "rx_overflows" },
5482 { "pause_off_state" },
5483 { "pause_on_state" },
5484 { "pause_received" },
5485};
5486
5487#define NUM_XMAC_STAT_KEYS ARRAY_SIZE(niu_xmac_stat_keys)
5488
5489static const struct {
5490 const char string[ETH_GSTRING_LEN];
5491} niu_bmac_stat_keys[] = {
5492 { "tx_underflow_errors" },
5493 { "tx_max_pkt_size_errors" },
5494 { "tx_bytes" },
5495 { "tx_frames" },
5496 { "rx_overflows" },
5497 { "rx_frames" },
5498 { "rx_align_errors" },
5499 { "rx_crc_errors" },
5500 { "rx_len_errors" },
5501 { "pause_off_state" },
5502 { "pause_on_state" },
5503 { "pause_received" },
5504};
5505
5506#define NUM_BMAC_STAT_KEYS ARRAY_SIZE(niu_bmac_stat_keys)
5507
5508static const struct {
5509 const char string[ETH_GSTRING_LEN];
5510} niu_rxchan_stat_keys[] = {
5511 { "rx_channel" },
5512 { "rx_packets" },
5513 { "rx_bytes" },
5514 { "rx_dropped" },
5515 { "rx_errors" },
5516};
5517
5518#define NUM_RXCHAN_STAT_KEYS ARRAY_SIZE(niu_rxchan_stat_keys)
5519
5520static const struct {
5521 const char string[ETH_GSTRING_LEN];
5522} niu_txchan_stat_keys[] = {
5523 { "tx_channel" },
5524 { "tx_packets" },
5525 { "tx_bytes" },
5526 { "tx_errors" },
5527};
5528
5529#define NUM_TXCHAN_STAT_KEYS ARRAY_SIZE(niu_txchan_stat_keys)
5530
5531static void niu_get_strings(struct net_device *dev, u32 stringset, u8 *data)
5532{
5533 struct niu *np = netdev_priv(dev);
5534 int i;
5535
5536 if (stringset != ETH_SS_STATS)
5537 return;
5538
5539 if (np->flags & NIU_FLAGS_XMAC) {
5540 memcpy(data, niu_xmac_stat_keys,
5541 sizeof(niu_xmac_stat_keys));
5542 data += sizeof(niu_xmac_stat_keys);
5543 } else {
5544 memcpy(data, niu_bmac_stat_keys,
5545 sizeof(niu_bmac_stat_keys));
5546 data += sizeof(niu_bmac_stat_keys);
5547 }
5548 for (i = 0; i < np->num_rx_rings; i++) {
5549 memcpy(data, niu_rxchan_stat_keys,
5550 sizeof(niu_rxchan_stat_keys));
5551 data += sizeof(niu_rxchan_stat_keys);
5552 }
5553 for (i = 0; i < np->num_tx_rings; i++) {
5554 memcpy(data, niu_txchan_stat_keys,
5555 sizeof(niu_txchan_stat_keys));
5556 data += sizeof(niu_txchan_stat_keys);
5557 }
5558}
5559
5560static int niu_get_stats_count(struct net_device *dev)
5561{
5562 struct niu *np = netdev_priv(dev);
5563
5564 return ((np->flags & NIU_FLAGS_XMAC ?
5565 NUM_XMAC_STAT_KEYS :
5566 NUM_BMAC_STAT_KEYS) +
5567 (np->num_rx_rings * NUM_RXCHAN_STAT_KEYS) +
5568 (np->num_tx_rings * NUM_TXCHAN_STAT_KEYS));
5569}
5570
5571static void niu_get_ethtool_stats(struct net_device *dev,
5572 struct ethtool_stats *stats, u64 *data)
5573{
5574 struct niu *np = netdev_priv(dev);
5575 int i;
5576
5577 niu_sync_mac_stats(np);
5578 if (np->flags & NIU_FLAGS_XMAC) {
5579 memcpy(data, &np->mac_stats.xmac,
5580 sizeof(struct niu_xmac_stats));
5581 data += (sizeof(struct niu_xmac_stats) / sizeof(u64));
5582 } else {
5583 memcpy(data, &np->mac_stats.bmac,
5584 sizeof(struct niu_bmac_stats));
5585 data += (sizeof(struct niu_bmac_stats) / sizeof(u64));
5586 }
5587 for (i = 0; i < np->num_rx_rings; i++) {
5588 struct rx_ring_info *rp = &np->rx_rings[i];
5589
5590 data[0] = rp->rx_channel;
5591 data[1] = rp->rx_packets;
5592 data[2] = rp->rx_bytes;
5593 data[3] = rp->rx_dropped;
5594 data[4] = rp->rx_errors;
5595 data += 5;
5596 }
5597 for (i = 0; i < np->num_tx_rings; i++) {
5598 struct tx_ring_info *rp = &np->tx_rings[i];
5599
5600 data[0] = rp->tx_channel;
5601 data[1] = rp->tx_packets;
5602 data[2] = rp->tx_bytes;
5603 data[3] = rp->tx_errors;
5604 data += 4;
5605 }
5606}
5607
5608static u64 niu_led_state_save(struct niu *np)
5609{
5610 if (np->flags & NIU_FLAGS_XMAC)
5611 return nr64_mac(XMAC_CONFIG);
5612 else
5613 return nr64_mac(BMAC_XIF_CONFIG);
5614}
5615
5616static void niu_led_state_restore(struct niu *np, u64 val)
5617{
5618 if (np->flags & NIU_FLAGS_XMAC)
5619 nw64_mac(XMAC_CONFIG, val);
5620 else
5621 nw64_mac(BMAC_XIF_CONFIG, val);
5622}
5623
5624static void niu_force_led(struct niu *np, int on)
5625{
5626 u64 val, reg, bit;
5627
5628 if (np->flags & NIU_FLAGS_XMAC) {
5629 reg = XMAC_CONFIG;
5630 bit = XMAC_CONFIG_FORCE_LED_ON;
5631 } else {
5632 reg = BMAC_XIF_CONFIG;
5633 bit = BMAC_XIF_CONFIG_LINK_LED;
5634 }
5635
5636 val = nr64_mac(reg);
5637 if (on)
5638 val |= bit;
5639 else
5640 val &= ~bit;
5641 nw64_mac(reg, val);
5642}
5643
5644static int niu_phys_id(struct net_device *dev, u32 data)
5645{
5646 struct niu *np = netdev_priv(dev);
5647 u64 orig_led_state;
5648 int i;
5649
5650 if (!netif_running(dev))
5651 return -EAGAIN;
5652
5653 if (data == 0)
5654 data = 2;
5655
5656 orig_led_state = niu_led_state_save(np);
5657 for (i = 0; i < (data * 2); i++) {
5658 int on = ((i % 2) == 0);
5659
5660 niu_force_led(np, on);
5661
5662 if (msleep_interruptible(500))
5663 break;
5664 }
5665 niu_led_state_restore(np, orig_led_state);
5666
5667 return 0;
5668}
5669
5670static const struct ethtool_ops niu_ethtool_ops = {
5671 .get_drvinfo = niu_get_drvinfo,
5672 .get_link = ethtool_op_get_link,
5673 .get_msglevel = niu_get_msglevel,
5674 .set_msglevel = niu_set_msglevel,
5675 .get_eeprom_len = niu_get_eeprom_len,
5676 .get_eeprom = niu_get_eeprom,
5677 .get_settings = niu_get_settings,
5678 .set_settings = niu_set_settings,
5679 .get_strings = niu_get_strings,
5680 .get_stats_count = niu_get_stats_count,
5681 .get_ethtool_stats = niu_get_ethtool_stats,
5682 .phys_id = niu_phys_id,
5683};
5684
5685static int niu_ldg_assign_ldn(struct niu *np, struct niu_parent *parent,
5686 int ldg, int ldn)
5687{
5688 if (ldg < NIU_LDG_MIN || ldg > NIU_LDG_MAX)
5689 return -EINVAL;
5690 if (ldn < 0 || ldn > LDN_MAX)
5691 return -EINVAL;
5692
5693 parent->ldg_map[ldn] = ldg;
5694
5695 if (np->parent->plat_type == PLAT_TYPE_NIU) {
5696 /* On N2 NIU, the ldn-->ldg assignments are setup and fixed by
5697 * the firmware, and we're not supposed to change them.
5698 * Validate the mapping, because if it's wrong we probably
5699 * won't get any interrupts and that's painful to debug.
5700 */
5701 if (nr64(LDG_NUM(ldn)) != ldg) {
5702 dev_err(np->device, PFX "Port %u, mis-matched "
5703 "LDG assignment "
5704 "for ldn %d, should be %d is %llu\n",
5705 np->port, ldn, ldg,
5706 (unsigned long long) nr64(LDG_NUM(ldn)));
5707 return -EINVAL;
5708 }
5709 } else
5710 nw64(LDG_NUM(ldn), ldg);
5711
5712 return 0;
5713}
5714
5715static int niu_set_ldg_timer_res(struct niu *np, int res)
5716{
5717 if (res < 0 || res > LDG_TIMER_RES_VAL)
5718 return -EINVAL;
5719
5720
5721 nw64(LDG_TIMER_RES, res);
5722
5723 return 0;
5724}
5725
5726static int niu_set_ldg_sid(struct niu *np, int ldg, int func, int vector)
5727{
5728 if ((ldg < NIU_LDG_MIN || ldg > NIU_LDG_MAX) ||
5729 (func < 0 || func > 3) ||
5730 (vector < 0 || vector > 0x1f))
5731 return -EINVAL;
5732
5733 nw64(SID(ldg), (func << SID_FUNC_SHIFT) | vector);
5734
5735 return 0;
5736}
5737
5738static int __devinit niu_pci_eeprom_read(struct niu *np, u32 addr)
5739{
5740 u64 frame, frame_base = (ESPC_PIO_STAT_READ_START |
5741 (addr << ESPC_PIO_STAT_ADDR_SHIFT));
5742 int limit;
5743
5744 if (addr > (ESPC_PIO_STAT_ADDR >> ESPC_PIO_STAT_ADDR_SHIFT))
5745 return -EINVAL;
5746
5747 frame = frame_base;
5748 nw64(ESPC_PIO_STAT, frame);
5749 limit = 64;
5750 do {
5751 udelay(5);
5752 frame = nr64(ESPC_PIO_STAT);
5753 if (frame & ESPC_PIO_STAT_READ_END)
5754 break;
5755 } while (limit--);
5756 if (!(frame & ESPC_PIO_STAT_READ_END)) {
5757 dev_err(np->device, PFX "EEPROM read timeout frame[%llx]\n",
5758 (unsigned long long) frame);
5759 return -ENODEV;
5760 }
5761
5762 frame = frame_base;
5763 nw64(ESPC_PIO_STAT, frame);
5764 limit = 64;
5765 do {
5766 udelay(5);
5767 frame = nr64(ESPC_PIO_STAT);
5768 if (frame & ESPC_PIO_STAT_READ_END)
5769 break;
5770 } while (limit--);
5771 if (!(frame & ESPC_PIO_STAT_READ_END)) {
5772 dev_err(np->device, PFX "EEPROM read timeout frame[%llx]\n",
5773 (unsigned long long) frame);
5774 return -ENODEV;
5775 }
5776
5777 frame = nr64(ESPC_PIO_STAT);
5778 return (frame & ESPC_PIO_STAT_DATA) >> ESPC_PIO_STAT_DATA_SHIFT;
5779}
5780
5781static int __devinit niu_pci_eeprom_read16(struct niu *np, u32 off)
5782{
5783 int err = niu_pci_eeprom_read(np, off);
5784 u16 val;
5785
5786 if (err < 0)
5787 return err;
5788 val = (err << 8);
5789 err = niu_pci_eeprom_read(np, off + 1);
5790 if (err < 0)
5791 return err;
5792 val |= (err & 0xff);
5793
5794 return val;
5795}
5796
5797static int __devinit niu_pci_eeprom_read16_swp(struct niu *np, u32 off)
5798{
5799 int err = niu_pci_eeprom_read(np, off);
5800 u16 val;
5801
5802 if (err < 0)
5803 return err;
5804
5805 val = (err & 0xff);
5806 err = niu_pci_eeprom_read(np, off + 1);
5807 if (err < 0)
5808 return err;
5809
5810 val |= (err & 0xff) << 8;
5811
5812 return val;
5813}
5814
5815static int __devinit niu_pci_vpd_get_propname(struct niu *np,
5816 u32 off,
5817 char *namebuf,
5818 int namebuf_len)
5819{
5820 int i;
5821
5822 for (i = 0; i < namebuf_len; i++) {
5823 int err = niu_pci_eeprom_read(np, off + i);
5824 if (err < 0)
5825 return err;
5826 *namebuf++ = err;
5827 if (!err)
5828 break;
5829 }
5830 if (i >= namebuf_len)
5831 return -EINVAL;
5832
5833 return i + 1;
5834}
5835
5836static void __devinit niu_vpd_parse_version(struct niu *np)
5837{
5838 struct niu_vpd *vpd = &np->vpd;
5839 int len = strlen(vpd->version) + 1;
5840 const char *s = vpd->version;
5841 int i;
5842
5843 for (i = 0; i < len - 5; i++) {
5844 if (!strncmp(s + i, "FCode ", 5))
5845 break;
5846 }
5847 if (i >= len - 5)
5848 return;
5849
5850 s += i + 5;
5851 sscanf(s, "%d.%d", &vpd->fcode_major, &vpd->fcode_minor);
5852
5853 niudbg(PROBE, "VPD_SCAN: FCODE major(%d) minor(%d)\n",
5854 vpd->fcode_major, vpd->fcode_minor);
5855 if (vpd->fcode_major > NIU_VPD_MIN_MAJOR ||
5856 (vpd->fcode_major == NIU_VPD_MIN_MAJOR &&
5857 vpd->fcode_minor >= NIU_VPD_MIN_MINOR))
5858 np->flags |= NIU_FLAGS_VPD_VALID;
5859}
5860
5861/* ESPC_PIO_EN_ENABLE must be set */
5862static int __devinit niu_pci_vpd_scan_props(struct niu *np,
5863 u32 start, u32 end)
5864{
5865 unsigned int found_mask = 0;
5866#define FOUND_MASK_MODEL 0x00000001
5867#define FOUND_MASK_BMODEL 0x00000002
5868#define FOUND_MASK_VERS 0x00000004
5869#define FOUND_MASK_MAC 0x00000008
5870#define FOUND_MASK_NMAC 0x00000010
5871#define FOUND_MASK_PHY 0x00000020
5872#define FOUND_MASK_ALL 0x0000003f
5873
5874 niudbg(PROBE, "VPD_SCAN: start[%x] end[%x]\n",
5875 start, end);
5876 while (start < end) {
5877 int len, err, instance, type, prop_len;
5878 char namebuf[64];
5879 u8 *prop_buf;
5880 int max_len;
5881
5882 if (found_mask == FOUND_MASK_ALL) {
5883 niu_vpd_parse_version(np);
5884 return 1;
5885 }
5886
5887 err = niu_pci_eeprom_read(np, start + 2);
5888 if (err < 0)
5889 return err;
5890 len = err;
5891 start += 3;
5892
5893 instance = niu_pci_eeprom_read(np, start);
5894 type = niu_pci_eeprom_read(np, start + 3);
5895 prop_len = niu_pci_eeprom_read(np, start + 4);
5896 err = niu_pci_vpd_get_propname(np, start + 5, namebuf, 64);
5897 if (err < 0)
5898 return err;
5899
5900 prop_buf = NULL;
5901 max_len = 0;
5902 if (!strcmp(namebuf, "model")) {
5903 prop_buf = np->vpd.model;
5904 max_len = NIU_VPD_MODEL_MAX;
5905 found_mask |= FOUND_MASK_MODEL;
5906 } else if (!strcmp(namebuf, "board-model")) {
5907 prop_buf = np->vpd.board_model;
5908 max_len = NIU_VPD_BD_MODEL_MAX;
5909 found_mask |= FOUND_MASK_BMODEL;
5910 } else if (!strcmp(namebuf, "version")) {
5911 prop_buf = np->vpd.version;
5912 max_len = NIU_VPD_VERSION_MAX;
5913 found_mask |= FOUND_MASK_VERS;
5914 } else if (!strcmp(namebuf, "local-mac-address")) {
5915 prop_buf = np->vpd.local_mac;
5916 max_len = ETH_ALEN;
5917 found_mask |= FOUND_MASK_MAC;
5918 } else if (!strcmp(namebuf, "num-mac-addresses")) {
5919 prop_buf = &np->vpd.mac_num;
5920 max_len = 1;
5921 found_mask |= FOUND_MASK_NMAC;
5922 } else if (!strcmp(namebuf, "phy-type")) {
5923 prop_buf = np->vpd.phy_type;
5924 max_len = NIU_VPD_PHY_TYPE_MAX;
5925 found_mask |= FOUND_MASK_PHY;
5926 }
5927
5928 if (max_len && prop_len > max_len) {
5929 dev_err(np->device, PFX "Property '%s' length (%d) is "
5930 "too long.\n", namebuf, prop_len);
5931 return -EINVAL;
5932 }
5933
5934 if (prop_buf) {
5935 u32 off = start + 5 + err;
5936 int i;
5937
5938 niudbg(PROBE, "VPD_SCAN: Reading in property [%s] "
5939 "len[%d]\n", namebuf, prop_len);
5940 for (i = 0; i < prop_len; i++)
5941 *prop_buf++ = niu_pci_eeprom_read(np, off + i);
5942 }
5943
5944 start += len;
5945 }
5946
5947 return 0;
5948}
5949
5950/* ESPC_PIO_EN_ENABLE must be set */
5951static void __devinit niu_pci_vpd_fetch(struct niu *np, u32 start)
5952{
5953 u32 offset;
5954 int err;
5955
5956 err = niu_pci_eeprom_read16_swp(np, start + 1);
5957 if (err < 0)
5958 return;
5959
5960 offset = err + 3;
5961
5962 while (start + offset < ESPC_EEPROM_SIZE) {
5963 u32 here = start + offset;
5964 u32 end;
5965
5966 err = niu_pci_eeprom_read(np, here);
5967 if (err != 0x90)
5968 return;
5969
5970 err = niu_pci_eeprom_read16_swp(np, here + 1);
5971 if (err < 0)
5972 return;
5973
5974 here = start + offset + 3;
5975 end = start + offset + err;
5976
5977 offset += err;
5978
5979 err = niu_pci_vpd_scan_props(np, here, end);
5980 if (err < 0 || err == 1)
5981 return;
5982 }
5983}
5984
5985/* ESPC_PIO_EN_ENABLE must be set */
5986static u32 __devinit niu_pci_vpd_offset(struct niu *np)
5987{
5988 u32 start = 0, end = ESPC_EEPROM_SIZE, ret;
5989 int err;
5990
5991 while (start < end) {
5992 ret = start;
5993
5994 /* ROM header signature? */
5995 err = niu_pci_eeprom_read16(np, start + 0);
5996 if (err != 0x55aa)
5997 return 0;
5998
5999 /* Apply offset to PCI data structure. */
6000 err = niu_pci_eeprom_read16(np, start + 23);
6001 if (err < 0)
6002 return 0;
6003 start += err;
6004
6005 /* Check for "PCIR" signature. */
6006 err = niu_pci_eeprom_read16(np, start + 0);
6007 if (err != 0x5043)
6008 return 0;
6009 err = niu_pci_eeprom_read16(np, start + 2);
6010 if (err != 0x4952)
6011 return 0;
6012
6013 /* Check for OBP image type. */
6014 err = niu_pci_eeprom_read(np, start + 20);
6015 if (err < 0)
6016 return 0;
6017 if (err != 0x01) {
6018 err = niu_pci_eeprom_read(np, ret + 2);
6019 if (err < 0)
6020 return 0;
6021
6022 start = ret + (err * 512);
6023 continue;
6024 }
6025
6026 err = niu_pci_eeprom_read16_swp(np, start + 8);
6027 if (err < 0)
6028 return err;
6029 ret += err;
6030
6031 err = niu_pci_eeprom_read(np, ret + 0);
6032 if (err != 0x82)
6033 return 0;
6034
6035 return ret;
6036 }
6037
6038 return 0;
6039}
6040
6041static int __devinit niu_phy_type_prop_decode(struct niu *np,
6042 const char *phy_prop)
6043{
6044 if (!strcmp(phy_prop, "mif")) {
6045 /* 1G copper, MII */
6046 np->flags &= ~(NIU_FLAGS_FIBER |
6047 NIU_FLAGS_10G);
6048 np->mac_xcvr = MAC_XCVR_MII;
6049 } else if (!strcmp(phy_prop, "xgf")) {
6050 /* 10G fiber, XPCS */
6051 np->flags |= (NIU_FLAGS_10G |
6052 NIU_FLAGS_FIBER);
6053 np->mac_xcvr = MAC_XCVR_XPCS;
6054 } else if (!strcmp(phy_prop, "pcs")) {
6055 /* 1G fiber, PCS */
6056 np->flags &= ~NIU_FLAGS_10G;
6057 np->flags |= NIU_FLAGS_FIBER;
6058 np->mac_xcvr = MAC_XCVR_PCS;
6059 } else if (!strcmp(phy_prop, "xgc")) {
6060 /* 10G copper, XPCS */
6061 np->flags |= NIU_FLAGS_10G;
6062 np->flags &= ~NIU_FLAGS_FIBER;
6063 np->mac_xcvr = MAC_XCVR_XPCS;
6064 } else {
6065 return -EINVAL;
6066 }
6067 return 0;
6068}
6069
6070static void __devinit niu_pci_vpd_validate(struct niu *np)
6071{
6072 struct net_device *dev = np->dev;
6073 struct niu_vpd *vpd = &np->vpd;
6074 u8 val8;
6075
6076 if (!is_valid_ether_addr(&vpd->local_mac[0])) {
6077 dev_err(np->device, PFX "VPD MAC invalid, "
6078 "falling back to SPROM.\n");
6079
6080 np->flags &= ~NIU_FLAGS_VPD_VALID;
6081 return;
6082 }
6083
6084 if (niu_phy_type_prop_decode(np, np->vpd.phy_type)) {
6085 dev_err(np->device, PFX "Illegal phy string [%s].\n",
6086 np->vpd.phy_type);
6087 dev_err(np->device, PFX "Falling back to SPROM.\n");
6088 np->flags &= ~NIU_FLAGS_VPD_VALID;
6089 return;
6090 }
6091
6092 memcpy(dev->perm_addr, vpd->local_mac, ETH_ALEN);
6093
6094 val8 = dev->perm_addr[5];
6095 dev->perm_addr[5] += np->port;
6096 if (dev->perm_addr[5] < val8)
6097 dev->perm_addr[4]++;
6098
6099 memcpy(dev->dev_addr, dev->perm_addr, dev->addr_len);
6100}
6101
6102static int __devinit niu_pci_probe_sprom(struct niu *np)
6103{
6104 struct net_device *dev = np->dev;
6105 int len, i;
6106 u64 val, sum;
6107 u8 val8;
6108
6109 val = (nr64(ESPC_VER_IMGSZ) & ESPC_VER_IMGSZ_IMGSZ);
6110 val >>= ESPC_VER_IMGSZ_IMGSZ_SHIFT;
6111 len = val / 4;
6112
6113 np->eeprom_len = len;
6114
6115 niudbg(PROBE, "SPROM: Image size %llu\n", (unsigned long long) val);
6116
6117 sum = 0;
6118 for (i = 0; i < len; i++) {
6119 val = nr64(ESPC_NCR(i));
6120 sum += (val >> 0) & 0xff;
6121 sum += (val >> 8) & 0xff;
6122 sum += (val >> 16) & 0xff;
6123 sum += (val >> 24) & 0xff;
6124 }
6125 niudbg(PROBE, "SPROM: Checksum %x\n", (int)(sum & 0xff));
6126 if ((sum & 0xff) != 0xab) {
6127 dev_err(np->device, PFX "Bad SPROM checksum "
6128 "(%x, should be 0xab)\n", (int) (sum & 0xff));
6129 return -EINVAL;
6130 }
6131
6132 val = nr64(ESPC_PHY_TYPE);
6133 switch (np->port) {
6134 case 0:
Al Viroa9d41192007-10-15 01:42:31 -0700[diff] [blame]6135 val8 = (val & ESPC_PHY_TYPE_PORT0) >>
David S. Millera3138df2007-10-09 01:54:01 -0700[diff] [blame]6136 ESPC_PHY_TYPE_PORT0_SHIFT;
6137 break;
6138 case 1:
Al Viroa9d41192007-10-15 01:42:31 -0700[diff] [blame]6139 val8 = (val & ESPC_PHY_TYPE_PORT1) >>
David S. Millera3138df2007-10-09 01:54:01 -0700[diff] [blame]6140 ESPC_PHY_TYPE_PORT1_SHIFT;
6141 break;
6142 case 2:
Al Viroa9d41192007-10-15 01:42:31 -0700[diff] [blame]6143 val8 = (val & ESPC_PHY_TYPE_PORT2) >>
David S. Millera3138df2007-10-09 01:54:01 -0700[diff] [blame]6144 ESPC_PHY_TYPE_PORT2_SHIFT;
6145 break;
6146 case 3:
Al Viroa9d41192007-10-15 01:42:31 -0700[diff] [blame]6147 val8 = (val & ESPC_PHY_TYPE_PORT3) >>
David S. Millera3138df2007-10-09 01:54:01 -0700[diff] [blame]6148 ESPC_PHY_TYPE_PORT3_SHIFT;
6149 break;
6150 default:
6151 dev_err(np->device, PFX "Bogus port number %u\n",
6152 np->port);
6153 return -EINVAL;
6154 }
Al Viroa9d41192007-10-15 01:42:31 -0700[diff] [blame]6155 niudbg(PROBE, "SPROM: PHY type %x\n", val8);
David S. Millera3138df2007-10-09 01:54:01 -0700[diff] [blame]6156
Al Viroa9d41192007-10-15 01:42:31 -0700[diff] [blame]6157 switch (val8) {
David S. Millera3138df2007-10-09 01:54:01 -0700[diff] [blame]6158 case ESPC_PHY_TYPE_1G_COPPER:
6159 /* 1G copper, MII */
6160 np->flags &= ~(NIU_FLAGS_FIBER |
6161 NIU_FLAGS_10G);
6162 np->mac_xcvr = MAC_XCVR_MII;
6163 break;
6164
6165 case ESPC_PHY_TYPE_1G_FIBER:
6166 /* 1G fiber, PCS */
6167 np->flags &= ~NIU_FLAGS_10G;
6168 np->flags |= NIU_FLAGS_FIBER;
6169 np->mac_xcvr = MAC_XCVR_PCS;
6170 break;
6171
6172 case ESPC_PHY_TYPE_10G_COPPER:
6173 /* 10G copper, XPCS */
6174 np->flags |= NIU_FLAGS_10G;
6175 np->flags &= ~NIU_FLAGS_FIBER;
6176 np->mac_xcvr = MAC_XCVR_XPCS;
6177 break;
6178
6179 case ESPC_PHY_TYPE_10G_FIBER:
6180 /* 10G fiber, XPCS */
6181 np->flags |= (NIU_FLAGS_10G |
6182 NIU_FLAGS_FIBER);
6183 np->mac_xcvr = MAC_XCVR_XPCS;
6184 break;
6185
6186 default:
Al Viroa9d41192007-10-15 01:42:31 -0700[diff] [blame]6187 dev_err(np->device, PFX "Bogus SPROM phy type %u\n", val8);
David S. Millera3138df2007-10-09 01:54:01 -0700[diff] [blame]6188 return -EINVAL;
6189 }
6190
6191 val = nr64(ESPC_MAC_ADDR0);
6192 niudbg(PROBE, "SPROM: MAC_ADDR0[%08llx]\n",
6193 (unsigned long long) val);
6194 dev->perm_addr[0] = (val >> 0) & 0xff;
6195 dev->perm_addr[1] = (val >> 8) & 0xff;
6196 dev->perm_addr[2] = (val >> 16) & 0xff;
6197 dev->perm_addr[3] = (val >> 24) & 0xff;
6198
6199 val = nr64(ESPC_MAC_ADDR1);
6200 niudbg(PROBE, "SPROM: MAC_ADDR1[%08llx]\n",
6201 (unsigned long long) val);
6202 dev->perm_addr[4] = (val >> 0) & 0xff;
6203 dev->perm_addr[5] = (val >> 8) & 0xff;
6204
6205 if (!is_valid_ether_addr(&dev->perm_addr[0])) {
6206 dev_err(np->device, PFX "SPROM MAC address invalid\n");
6207 dev_err(np->device, PFX "[ \n");
6208 for (i = 0; i < 6; i++)
6209 printk("%02x ", dev->perm_addr[i]);
6210 printk("]\n");
6211 return -EINVAL;
6212 }
6213
6214 val8 = dev->perm_addr[5];
6215 dev->perm_addr[5] += np->port;
6216 if (dev->perm_addr[5] < val8)
6217 dev->perm_addr[4]++;
6218
6219 memcpy(dev->dev_addr, dev->perm_addr, dev->addr_len);
6220
6221 val = nr64(ESPC_MOD_STR_LEN);
6222 niudbg(PROBE, "SPROM: MOD_STR_LEN[%llu]\n",
6223 (unsigned long long) val);
David S. Millere6a5fdf2007-10-15 01:36:24 -0700[diff] [blame]6224 if (val >= 8 * 4)
David S. Millera3138df2007-10-09 01:54:01 -0700[diff] [blame]6225 return -EINVAL;
6226
6227 for (i = 0; i < val; i += 4) {
6228 u64 tmp = nr64(ESPC_NCR(5 + (i / 4)));
6229
6230 np->vpd.model[i + 3] = (tmp >> 0) & 0xff;
6231 np->vpd.model[i + 2] = (tmp >> 8) & 0xff;
6232 np->vpd.model[i + 1] = (tmp >> 16) & 0xff;
6233 np->vpd.model[i + 0] = (tmp >> 24) & 0xff;
6234 }
6235 np->vpd.model[val] = '\0';
6236
6237 val = nr64(ESPC_BD_MOD_STR_LEN);
6238 niudbg(PROBE, "SPROM: BD_MOD_STR_LEN[%llu]\n",
6239 (unsigned long long) val);
David S. Millere6a5fdf2007-10-15 01:36:24 -0700[diff] [blame]6240 if (val >= 4 * 4)
David S. Millera3138df2007-10-09 01:54:01 -0700[diff] [blame]6241 return -EINVAL;
6242
6243 for (i = 0; i < val; i += 4) {
6244 u64 tmp = nr64(ESPC_NCR(14 + (i / 4)));
6245
6246 np->vpd.board_model[i + 3] = (tmp >> 0) & 0xff;
6247 np->vpd.board_model[i + 2] = (tmp >> 8) & 0xff;
6248 np->vpd.board_model[i + 1] = (tmp >> 16) & 0xff;
6249 np->vpd.board_model[i + 0] = (tmp >> 24) & 0xff;
6250 }
6251 np->vpd.board_model[val] = '\0';
6252
6253 np->vpd.mac_num =
6254 nr64(ESPC_NUM_PORTS_MACS) & ESPC_NUM_PORTS_MACS_VAL;
6255 niudbg(PROBE, "SPROM: NUM_PORTS_MACS[%d]\n",
6256 np->vpd.mac_num);
6257
6258 return 0;
6259}
6260
6261static int __devinit niu_get_and_validate_port(struct niu *np)
6262{
6263 struct niu_parent *parent = np->parent;
6264
6265 if (np->port <= 1)
6266 np->flags |= NIU_FLAGS_XMAC;
6267
6268 if (!parent->num_ports) {
6269 if (parent->plat_type == PLAT_TYPE_NIU) {
6270 parent->num_ports = 2;
6271 } else {
6272 parent->num_ports = nr64(ESPC_NUM_PORTS_MACS) &
6273 ESPC_NUM_PORTS_MACS_VAL;
6274
6275 if (!parent->num_ports)
6276 parent->num_ports = 4;
6277 }
6278 }
6279
6280 niudbg(PROBE, "niu_get_and_validate_port: port[%d] num_ports[%d]\n",
6281 np->port, parent->num_ports);
6282 if (np->port >= parent->num_ports)
6283 return -ENODEV;
6284
6285 return 0;
6286}
6287
6288static int __devinit phy_record(struct niu_parent *parent,
6289 struct phy_probe_info *p,
6290 int dev_id_1, int dev_id_2, u8 phy_port,
6291 int type)
6292{
6293 u32 id = (dev_id_1 << 16) | dev_id_2;
6294 u8 idx;
6295
6296 if (dev_id_1 < 0 || dev_id_2 < 0)
6297 return 0;
6298 if (type == PHY_TYPE_PMA_PMD || type == PHY_TYPE_PCS) {
6299 if ((id & NIU_PHY_ID_MASK) != NIU_PHY_ID_BCM8704)
6300 return 0;
6301 } else {
6302 if ((id & NIU_PHY_ID_MASK) != NIU_PHY_ID_BCM5464R)
6303 return 0;
6304 }
6305
6306 pr_info("niu%d: Found PHY %08x type %s at phy_port %u\n",
6307 parent->index, id,
6308 (type == PHY_TYPE_PMA_PMD ?
6309 "PMA/PMD" :
6310 (type == PHY_TYPE_PCS ?
6311 "PCS" : "MII")),
6312 phy_port);
6313
6314 if (p->cur[type] >= NIU_MAX_PORTS) {
6315 printk(KERN_ERR PFX "Too many PHY ports.\n");
6316 return -EINVAL;
6317 }
6318 idx = p->cur[type];
6319 p->phy_id[type][idx] = id;
6320 p->phy_port[type][idx] = phy_port;
6321 p->cur[type] = idx + 1;
6322 return 0;
6323}
6324
6325static int __devinit port_has_10g(struct phy_probe_info *p, int port)
6326{
6327 int i;
6328
6329 for (i = 0; i < p->cur[PHY_TYPE_PMA_PMD]; i++) {
6330 if (p->phy_port[PHY_TYPE_PMA_PMD][i] == port)
6331 return 1;
6332 }
6333 for (i = 0; i < p->cur[PHY_TYPE_PCS]; i++) {
6334 if (p->phy_port[PHY_TYPE_PCS][i] == port)
6335 return 1;
6336 }
6337
6338 return 0;
6339}
6340
6341static int __devinit count_10g_ports(struct phy_probe_info *p, int *lowest)
6342{
6343 int port, cnt;
6344
6345 cnt = 0;
6346 *lowest = 32;
6347 for (port = 8; port < 32; port++) {
6348 if (port_has_10g(p, port)) {
6349 if (!cnt)
6350 *lowest = port;
6351 cnt++;
6352 }
6353 }
6354
6355 return cnt;
6356}
6357
6358static int __devinit count_1g_ports(struct phy_probe_info *p, int *lowest)
6359{
6360 *lowest = 32;
6361 if (p->cur[PHY_TYPE_MII])
6362 *lowest = p->phy_port[PHY_TYPE_MII][0];
6363
6364 return p->cur[PHY_TYPE_MII];
6365}
6366
6367static void __devinit niu_n2_divide_channels(struct niu_parent *parent)
6368{
6369 int num_ports = parent->num_ports;
6370 int i;
6371
6372 for (i = 0; i < num_ports; i++) {
6373 parent->rxchan_per_port[i] = (16 / num_ports);
6374 parent->txchan_per_port[i] = (16 / num_ports);
6375
6376 pr_info(PFX "niu%d: Port %u [%u RX chans] "
6377 "[%u TX chans]\n",
6378 parent->index, i,
6379 parent->rxchan_per_port[i],
6380 parent->txchan_per_port[i]);
6381 }
6382}
6383
6384static void __devinit niu_divide_channels(struct niu_parent *parent,
6385 int num_10g, int num_1g)
6386{
6387 int num_ports = parent->num_ports;
6388 int rx_chans_per_10g, rx_chans_per_1g;
6389 int tx_chans_per_10g, tx_chans_per_1g;
6390 int i, tot_rx, tot_tx;
6391
6392 if (!num_10g || !num_1g) {
6393 rx_chans_per_10g = rx_chans_per_1g =
6394 (NIU_NUM_RXCHAN / num_ports);
6395 tx_chans_per_10g = tx_chans_per_1g =
6396 (NIU_NUM_TXCHAN / num_ports);
6397 } else {
6398 rx_chans_per_1g = NIU_NUM_RXCHAN / 8;
6399 rx_chans_per_10g = (NIU_NUM_RXCHAN -
6400 (rx_chans_per_1g * num_1g)) /
6401 num_10g;
6402
6403 tx_chans_per_1g = NIU_NUM_TXCHAN / 6;
6404 tx_chans_per_10g = (NIU_NUM_TXCHAN -
6405 (tx_chans_per_1g * num_1g)) /
6406 num_10g;
6407 }
6408
6409 tot_rx = tot_tx = 0;
6410 for (i = 0; i < num_ports; i++) {
6411 int type = phy_decode(parent->port_phy, i);
6412
6413 if (type == PORT_TYPE_10G) {
6414 parent->rxchan_per_port[i] = rx_chans_per_10g;
6415 parent->txchan_per_port[i] = tx_chans_per_10g;
6416 } else {
6417 parent->rxchan_per_port[i] = rx_chans_per_1g;
6418 parent->txchan_per_port[i] = tx_chans_per_1g;
6419 }
6420 pr_info(PFX "niu%d: Port %u [%u RX chans] "
6421 "[%u TX chans]\n",
6422 parent->index, i,
6423 parent->rxchan_per_port[i],
6424 parent->txchan_per_port[i]);
6425 tot_rx += parent->rxchan_per_port[i];
6426 tot_tx += parent->txchan_per_port[i];
6427 }
6428
6429 if (tot_rx > NIU_NUM_RXCHAN) {
6430 printk(KERN_ERR PFX "niu%d: Too many RX channels (%d), "
6431 "resetting to one per port.\n",
6432 parent->index, tot_rx);
6433 for (i = 0; i < num_ports; i++)
6434 parent->rxchan_per_port[i] = 1;
6435 }
6436 if (tot_tx > NIU_NUM_TXCHAN) {
6437 printk(KERN_ERR PFX "niu%d: Too many TX channels (%d), "
6438 "resetting to one per port.\n",
6439 parent->index, tot_tx);
6440 for (i = 0; i < num_ports; i++)
6441 parent->txchan_per_port[i] = 1;
6442 }
6443 if (tot_rx < NIU_NUM_RXCHAN || tot_tx < NIU_NUM_TXCHAN) {
6444 printk(KERN_WARNING PFX "niu%d: Driver bug, wasted channels, "
6445 "RX[%d] TX[%d]\n",
6446 parent->index, tot_rx, tot_tx);
6447 }
6448}
6449
6450static void __devinit niu_divide_rdc_groups(struct niu_parent *parent,
6451 int num_10g, int num_1g)
6452{
6453 int i, num_ports = parent->num_ports;
6454 int rdc_group, rdc_groups_per_port;
6455 int rdc_channel_base;
6456
6457 rdc_group = 0;
6458 rdc_groups_per_port = NIU_NUM_RDC_TABLES / num_ports;
6459
6460 rdc_channel_base = 0;
6461
6462 for (i = 0; i < num_ports; i++) {
6463 struct niu_rdc_tables *tp = &parent->rdc_group_cfg[i];
6464 int grp, num_channels = parent->rxchan_per_port[i];
6465 int this_channel_offset;
6466
6467 tp->first_table_num = rdc_group;
6468 tp->num_tables = rdc_groups_per_port;
6469 this_channel_offset = 0;
6470 for (grp = 0; grp < tp->num_tables; grp++) {
6471 struct rdc_table *rt = &tp->tables[grp];
6472 int slot;
6473
6474 pr_info(PFX "niu%d: Port %d RDC tbl(%d) [ ",
6475 parent->index, i, tp->first_table_num + grp);
6476 for (slot = 0; slot < NIU_RDC_TABLE_SLOTS; slot++) {
6477 rt->rxdma_channel[slot] =
6478 rdc_channel_base + this_channel_offset;
6479
6480 printk("%d ", rt->rxdma_channel[slot]);
6481
6482 if (++this_channel_offset == num_channels)
6483 this_channel_offset = 0;
6484 }
6485 printk("]\n");
6486 }
6487
6488 parent->rdc_default[i] = rdc_channel_base;
6489
6490 rdc_channel_base += num_channels;
6491 rdc_group += rdc_groups_per_port;
6492 }
6493}
6494
6495static int __devinit fill_phy_probe_info(struct niu *np,
6496 struct niu_parent *parent,
6497 struct phy_probe_info *info)
6498{
6499 unsigned long flags;
6500 int port, err;
6501
6502 memset(info, 0, sizeof(*info));
6503
6504 /* Port 0 to 7 are reserved for onboard Serdes, probe the rest. */
6505 niu_lock_parent(np, flags);
6506 err = 0;
6507 for (port = 8; port < 32; port++) {
6508 int dev_id_1, dev_id_2;
6509
6510 dev_id_1 = mdio_read(np, port,
6511 NIU_PMA_PMD_DEV_ADDR, MII_PHYSID1);
6512 dev_id_2 = mdio_read(np, port,
6513 NIU_PMA_PMD_DEV_ADDR, MII_PHYSID2);
6514 err = phy_record(parent, info, dev_id_1, dev_id_2, port,
6515 PHY_TYPE_PMA_PMD);
6516 if (err)
6517 break;
6518 dev_id_1 = mdio_read(np, port,
6519 NIU_PCS_DEV_ADDR, MII_PHYSID1);
6520 dev_id_2 = mdio_read(np, port,
6521 NIU_PCS_DEV_ADDR, MII_PHYSID2);
6522 err = phy_record(parent, info, dev_id_1, dev_id_2, port,
6523 PHY_TYPE_PCS);
6524 if (err)
6525 break;
6526 dev_id_1 = mii_read(np, port, MII_PHYSID1);
6527 dev_id_2 = mii_read(np, port, MII_PHYSID2);
6528 err = phy_record(parent, info, dev_id_1, dev_id_2, port,
6529 PHY_TYPE_MII);
6530 if (err)
6531 break;
6532 }
6533 niu_unlock_parent(np, flags);
6534
6535 return err;
6536}
6537
6538static int __devinit walk_phys(struct niu *np, struct niu_parent *parent)
6539{
6540 struct phy_probe_info *info = &parent->phy_probe_info;
6541 int lowest_10g, lowest_1g;
6542 int num_10g, num_1g;
6543 u32 val;
6544 int err;
6545
6546 err = fill_phy_probe_info(np, parent, info);
6547 if (err)
6548 return err;
6549
6550 num_10g = count_10g_ports(info, &lowest_10g);
6551 num_1g = count_1g_ports(info, &lowest_1g);
6552
6553 switch ((num_10g << 4) | num_1g) {
6554 case 0x24:
6555 if (lowest_1g == 10)
6556 parent->plat_type = PLAT_TYPE_VF_P0;
6557 else if (lowest_1g == 26)
6558 parent->plat_type = PLAT_TYPE_VF_P1;
6559 else
6560 goto unknown_vg_1g_port;
6561
6562 /* fallthru */
6563 case 0x22:
6564 val = (phy_encode(PORT_TYPE_10G, 0) |
6565 phy_encode(PORT_TYPE_10G, 1) |
6566 phy_encode(PORT_TYPE_1G, 2) |
6567 phy_encode(PORT_TYPE_1G, 3));
6568 break;
6569
6570 case 0x20:
6571 val = (phy_encode(PORT_TYPE_10G, 0) |
6572 phy_encode(PORT_TYPE_10G, 1));
6573 break;
6574
6575 case 0x10:
6576 val = phy_encode(PORT_TYPE_10G, np->port);
6577 break;
6578
6579 case 0x14:
6580 if (lowest_1g == 10)
6581 parent->plat_type = PLAT_TYPE_VF_P0;
6582 else if (lowest_1g == 26)
6583 parent->plat_type = PLAT_TYPE_VF_P1;
6584 else
6585 goto unknown_vg_1g_port;
6586
6587 /* fallthru */
6588 case 0x13:
6589 if ((lowest_10g & 0x7) == 0)
6590 val = (phy_encode(PORT_TYPE_10G, 0) |
6591 phy_encode(PORT_TYPE_1G, 1) |
6592 phy_encode(PORT_TYPE_1G, 2) |
6593 phy_encode(PORT_TYPE_1G, 3));
6594 else
6595 val = (phy_encode(PORT_TYPE_1G, 0) |
6596 phy_encode(PORT_TYPE_10G, 1) |
6597 phy_encode(PORT_TYPE_1G, 2) |
6598 phy_encode(PORT_TYPE_1G, 3));
6599 break;
6600
6601 case 0x04:
6602 if (lowest_1g == 10)
6603 parent->plat_type = PLAT_TYPE_VF_P0;
6604 else if (lowest_1g == 26)
6605 parent->plat_type = PLAT_TYPE_VF_P1;
6606 else
6607 goto unknown_vg_1g_port;
6608
6609 val = (phy_encode(PORT_TYPE_1G, 0) |
6610 phy_encode(PORT_TYPE_1G, 1) |
6611 phy_encode(PORT_TYPE_1G, 2) |
6612 phy_encode(PORT_TYPE_1G, 3));
6613 break;
6614
6615 default:
6616 printk(KERN_ERR PFX "Unsupported port config "
6617 "10G[%d] 1G[%d]\n",
6618 num_10g, num_1g);
6619 return -EINVAL;
6620 }
6621
6622 parent->port_phy = val;
6623
6624 if (parent->plat_type == PLAT_TYPE_NIU)
6625 niu_n2_divide_channels(parent);
6626 else
6627 niu_divide_channels(parent, num_10g, num_1g);
6628
6629 niu_divide_rdc_groups(parent, num_10g, num_1g);
6630
6631 return 0;
6632
6633unknown_vg_1g_port:
6634 printk(KERN_ERR PFX "Cannot identify platform type, 1gport=%d\n",
6635 lowest_1g);
6636 return -EINVAL;
6637}
6638
6639static int __devinit niu_probe_ports(struct niu *np)
6640{
6641 struct niu_parent *parent = np->parent;
6642 int err, i;
6643
6644 niudbg(PROBE, "niu_probe_ports(): port_phy[%08x]\n",
6645 parent->port_phy);
6646
6647 if (parent->port_phy == PORT_PHY_UNKNOWN) {
6648 err = walk_phys(np, parent);
6649 if (err)
6650 return err;
6651
6652 niu_set_ldg_timer_res(np, 2);
6653 for (i = 0; i <= LDN_MAX; i++)
6654 niu_ldn_irq_enable(np, i, 0);
6655 }
6656
6657 if (parent->port_phy == PORT_PHY_INVALID)
6658 return -EINVAL;
6659
6660 return 0;
6661}
6662
6663static int __devinit niu_classifier_swstate_init(struct niu *np)
6664{
6665 struct niu_classifier *cp = &np->clas;
6666
6667 niudbg(PROBE, "niu_classifier_swstate_init: num_tcam(%d)\n",
6668 np->parent->tcam_num_entries);
6669
6670 cp->tcam_index = (u16) np->port;
6671 cp->h1_init = 0xffffffff;
6672 cp->h2_init = 0xffff;
6673
6674 return fflp_early_init(np);
6675}
6676
6677static void __devinit niu_link_config_init(struct niu *np)
6678{
6679 struct niu_link_config *lp = &np->link_config;
6680
6681 lp->advertising = (ADVERTISED_10baseT_Half |
6682 ADVERTISED_10baseT_Full |
6683 ADVERTISED_100baseT_Half |
6684 ADVERTISED_100baseT_Full |
6685 ADVERTISED_1000baseT_Half |
6686 ADVERTISED_1000baseT_Full |
6687 ADVERTISED_10000baseT_Full |
6688 ADVERTISED_Autoneg);
6689 lp->speed = lp->active_speed = SPEED_INVALID;
6690 lp->duplex = lp->active_duplex = DUPLEX_INVALID;
6691#if 0
6692 lp->loopback_mode = LOOPBACK_MAC;
6693 lp->active_speed = SPEED_10000;
6694 lp->active_duplex = DUPLEX_FULL;
6695#else
6696 lp->loopback_mode = LOOPBACK_DISABLED;
6697#endif
6698}
6699
6700static int __devinit niu_init_mac_ipp_pcs_base(struct niu *np)
6701{
6702 switch (np->port) {
6703 case 0:
6704 np->mac_regs = np->regs + XMAC_PORT0_OFF;
6705 np->ipp_off = 0x00000;
6706 np->pcs_off = 0x04000;
6707 np->xpcs_off = 0x02000;
6708 break;
6709
6710 case 1:
6711 np->mac_regs = np->regs + XMAC_PORT1_OFF;
6712 np->ipp_off = 0x08000;
6713 np->pcs_off = 0x0a000;
6714 np->xpcs_off = 0x08000;
6715 break;
6716
6717 case 2:
6718 np->mac_regs = np->regs + BMAC_PORT2_OFF;
6719 np->ipp_off = 0x04000;
6720 np->pcs_off = 0x0e000;
6721 np->xpcs_off = ~0UL;
6722 break;
6723
6724 case 3:
6725 np->mac_regs = np->regs + BMAC_PORT3_OFF;
6726 np->ipp_off = 0x0c000;
6727 np->pcs_off = 0x12000;
6728 np->xpcs_off = ~0UL;
6729 break;
6730
6731 default:
6732 dev_err(np->device, PFX "Port %u is invalid, cannot "
6733 "compute MAC block offset.\n", np->port);
6734 return -EINVAL;
6735 }
6736
6737 return 0;
6738}
6739
6740static void __devinit niu_try_msix(struct niu *np, u8 *ldg_num_map)
6741{
6742 struct msix_entry msi_vec[NIU_NUM_LDG];
6743 struct niu_parent *parent = np->parent;
6744 struct pci_dev *pdev = np->pdev;
6745 int i, num_irqs, err;
6746 u8 first_ldg;
6747
6748 first_ldg = (NIU_NUM_LDG / parent->num_ports) * np->port;
6749 for (i = 0; i < (NIU_NUM_LDG / parent->num_ports); i++)
6750 ldg_num_map[i] = first_ldg + i;
6751
6752 num_irqs = (parent->rxchan_per_port[np->port] +
6753 parent->txchan_per_port[np->port] +
6754 (np->port == 0 ? 3 : 1));
6755 BUG_ON(num_irqs > (NIU_NUM_LDG / parent->num_ports));
6756
6757retry:
6758 for (i = 0; i < num_irqs; i++) {
6759 msi_vec[i].vector = 0;
6760 msi_vec[i].entry = i;
6761 }
6762
6763 err = pci_enable_msix(pdev, msi_vec, num_irqs);
6764 if (err < 0) {
6765 np->flags &= ~NIU_FLAGS_MSIX;
6766 return;
6767 }
6768 if (err > 0) {
6769 num_irqs = err;
6770 goto retry;
6771 }
6772
6773 np->flags |= NIU_FLAGS_MSIX;
6774 for (i = 0; i < num_irqs; i++)
6775 np->ldg[i].irq = msi_vec[i].vector;
6776 np->num_ldg = num_irqs;
6777}
6778
6779static int __devinit niu_n2_irq_init(struct niu *np, u8 *ldg_num_map)
6780{
6781#ifdef CONFIG_SPARC64
6782 struct of_device *op = np->op;
6783 const u32 *int_prop;
6784 int i;
6785
6786 int_prop = of_get_property(op->node, "interrupts", NULL);
6787 if (!int_prop)
6788 return -ENODEV;
6789
6790 for (i = 0; i < op->num_irqs; i++) {
6791 ldg_num_map[i] = int_prop[i];
6792 np->ldg[i].irq = op->irqs[i];
6793 }
6794
6795 np->num_ldg = op->num_irqs;
6796
6797 return 0;
6798#else
6799 return -EINVAL;
6800#endif
6801}
6802
6803static int __devinit niu_ldg_init(struct niu *np)
6804{
6805 struct niu_parent *parent = np->parent;
6806 u8 ldg_num_map[NIU_NUM_LDG];
6807 int first_chan, num_chan;
6808 int i, err, ldg_rotor;
6809 u8 port;
6810
6811 np->num_ldg = 1;
6812 np->ldg[0].irq = np->dev->irq;
6813 if (parent->plat_type == PLAT_TYPE_NIU) {
6814 err = niu_n2_irq_init(np, ldg_num_map);
6815 if (err)
6816 return err;
6817 } else
6818 niu_try_msix(np, ldg_num_map);
6819
6820 port = np->port;
6821 for (i = 0; i < np->num_ldg; i++) {
6822 struct niu_ldg *lp = &np->ldg[i];
6823
6824 netif_napi_add(np->dev, &lp->napi, niu_poll, 64);
6825
6826 lp->np = np;
6827 lp->ldg_num = ldg_num_map[i];
6828 lp->timer = 2; /* XXX */
6829
6830 /* On N2 NIU the firmware has setup the SID mappings so they go
6831 * to the correct values that will route the LDG to the proper
6832 * interrupt in the NCU interrupt table.
6833 */
6834 if (np->parent->plat_type != PLAT_TYPE_NIU) {
6835 err = niu_set_ldg_sid(np, lp->ldg_num, port, i);
6836 if (err)
6837 return err;
6838 }
6839 }
6840
6841 /* We adopt the LDG assignment ordering used by the N2 NIU
6842 * 'interrupt' properties because that simplifies a lot of
6843 * things. This ordering is:
6844 *
6845 * MAC
6846 * MIF (if port zero)
6847 * SYSERR (if port zero)
6848 * RX channels
6849 * TX channels
6850 */
6851
6852 ldg_rotor = 0;
6853
6854 err = niu_ldg_assign_ldn(np, parent, ldg_num_map[ldg_rotor],
6855 LDN_MAC(port));
6856 if (err)
6857 return err;
6858
6859 ldg_rotor++;
6860 if (ldg_rotor == np->num_ldg)
6861 ldg_rotor = 0;
6862
6863 if (port == 0) {
6864 err = niu_ldg_assign_ldn(np, parent,
6865 ldg_num_map[ldg_rotor],
6866 LDN_MIF);
6867 if (err)
6868 return err;
6869
6870 ldg_rotor++;
6871 if (ldg_rotor == np->num_ldg)
6872 ldg_rotor = 0;
6873
6874 err = niu_ldg_assign_ldn(np, parent,
6875 ldg_num_map[ldg_rotor],
6876 LDN_DEVICE_ERROR);
6877 if (err)
6878 return err;
6879
6880 ldg_rotor++;
6881 if (ldg_rotor == np->num_ldg)
6882 ldg_rotor = 0;
6883
6884 }
6885
6886 first_chan = 0;
6887 for (i = 0; i < port; i++)
6888 first_chan += parent->rxchan_per_port[port];
6889 num_chan = parent->rxchan_per_port[port];
6890
6891 for (i = first_chan; i < (first_chan + num_chan); i++) {
6892 err = niu_ldg_assign_ldn(np, parent,
6893 ldg_num_map[ldg_rotor],
6894 LDN_RXDMA(i));
6895 if (err)
6896 return err;
6897 ldg_rotor++;
6898 if (ldg_rotor == np->num_ldg)
6899 ldg_rotor = 0;
6900 }
6901
6902 first_chan = 0;
6903 for (i = 0; i < port; i++)
6904 first_chan += parent->txchan_per_port[port];
6905 num_chan = parent->txchan_per_port[port];
6906 for (i = first_chan; i < (first_chan + num_chan); i++) {
6907 err = niu_ldg_assign_ldn(np, parent,
6908 ldg_num_map[ldg_rotor],
6909 LDN_TXDMA(i));
6910 if (err)
6911 return err;
6912 ldg_rotor++;
6913 if (ldg_rotor == np->num_ldg)
6914 ldg_rotor = 0;
6915 }
6916
6917 return 0;
6918}
6919
6920static void __devexit niu_ldg_free(struct niu *np)
6921{
6922 if (np->flags & NIU_FLAGS_MSIX)
6923 pci_disable_msix(np->pdev);
6924}
6925
6926static int __devinit niu_get_of_props(struct niu *np)
6927{
6928#ifdef CONFIG_SPARC64
6929 struct net_device *dev = np->dev;
6930 struct device_node *dp;
6931 const char *phy_type;
6932 const u8 *mac_addr;
6933 int prop_len;
6934
6935 if (np->parent->plat_type == PLAT_TYPE_NIU)
6936 dp = np->op->node;
6937 else
6938 dp = pci_device_to_OF_node(np->pdev);
6939
6940 phy_type = of_get_property(dp, "phy-type", &prop_len);
6941 if (!phy_type) {
6942 dev_err(np->device, PFX "%s: OF node lacks "
6943 "phy-type property\n",
6944 dp->full_name);
6945 return -EINVAL;
6946 }
6947
6948 if (!strcmp(phy_type, "none"))
6949 return -ENODEV;
6950
6951 strcpy(np->vpd.phy_type, phy_type);
6952
6953 if (niu_phy_type_prop_decode(np, np->vpd.phy_type)) {
6954 dev_err(np->device, PFX "%s: Illegal phy string [%s].\n",
6955 dp->full_name, np->vpd.phy_type);
6956 return -EINVAL;
6957 }
6958
6959 mac_addr = of_get_property(dp, "local-mac-address", &prop_len);
6960 if (!mac_addr) {
6961 dev_err(np->device, PFX "%s: OF node lacks "
6962 "local-mac-address property\n",
6963 dp->full_name);
6964 return -EINVAL;
6965 }
6966 if (prop_len != dev->addr_len) {
6967 dev_err(np->device, PFX "%s: OF MAC address prop len (%d) "
6968 "is wrong.\n",
6969 dp->full_name, prop_len);
6970 }
6971 memcpy(dev->perm_addr, mac_addr, dev->addr_len);
6972 if (!is_valid_ether_addr(&dev->perm_addr[0])) {
6973 int i;
6974
6975 dev_err(np->device, PFX "%s: OF MAC address is invalid\n",
6976 dp->full_name);
6977 dev_err(np->device, PFX "%s: [ \n",
6978 dp->full_name);
6979 for (i = 0; i < 6; i++)
6980 printk("%02x ", dev->perm_addr[i]);
6981 printk("]\n");
6982 return -EINVAL;
6983 }
6984
6985 memcpy(dev->dev_addr, dev->perm_addr, dev->addr_len);
6986
6987 return 0;
6988#else
6989 return -EINVAL;
6990#endif
6991}
6992
6993static int __devinit niu_get_invariants(struct niu *np)
6994{
6995 int err, have_props;
6996 u32 offset;
6997
6998 err = niu_get_of_props(np);
6999 if (err == -ENODEV)
7000 return err;
7001
7002 have_props = !err;
7003
7004 err = niu_get_and_validate_port(np);
7005 if (err)
7006 return err;
7007
7008 err = niu_init_mac_ipp_pcs_base(np);
7009 if (err)
7010 return err;
7011
7012 if (!have_props) {
7013 if (np->parent->plat_type == PLAT_TYPE_NIU)
7014 return -EINVAL;
7015
7016 nw64(ESPC_PIO_EN, ESPC_PIO_EN_ENABLE);
7017 offset = niu_pci_vpd_offset(np);
7018 niudbg(PROBE, "niu_get_invariants: VPD offset [%08x]\n",
7019 offset);
7020 if (offset)
7021 niu_pci_vpd_fetch(np, offset);
7022 nw64(ESPC_PIO_EN, 0);
7023
7024 if (np->flags & NIU_FLAGS_VPD_VALID)
7025 niu_pci_vpd_validate(np);
7026
7027 if (!(np->flags & NIU_FLAGS_VPD_VALID)) {
7028 err = niu_pci_probe_sprom(np);
7029 if (err)
7030 return err;
7031 }
7032 }
7033
7034 err = niu_probe_ports(np);
7035 if (err)
7036 return err;
7037
7038 niu_ldg_init(np);
7039
7040 niu_classifier_swstate_init(np);
7041 niu_link_config_init(np);
7042
7043 err = niu_determine_phy_disposition(np);
7044 if (!err)
7045 err = niu_init_link(np);
7046
7047 return err;
7048}
7049
7050static LIST_HEAD(niu_parent_list);
7051static DEFINE_MUTEX(niu_parent_lock);
7052static int niu_parent_index;
7053
7054static ssize_t show_port_phy(struct device *dev,
7055 struct device_attribute *attr, char *buf)
7056{
7057 struct platform_device *plat_dev = to_platform_device(dev);
7058 struct niu_parent *p = plat_dev->dev.platform_data;
7059 u32 port_phy = p->port_phy;
7060 char *orig_buf = buf;
7061 int i;
7062
7063 if (port_phy == PORT_PHY_UNKNOWN ||
7064 port_phy == PORT_PHY_INVALID)
7065 return 0;
7066
7067 for (i = 0; i < p->num_ports; i++) {
7068 const char *type_str;
7069 int type;
7070
7071 type = phy_decode(port_phy, i);
7072 if (type == PORT_TYPE_10G)
7073 type_str = "10G";
7074 else
7075 type_str = "1G";
7076 buf += sprintf(buf,
7077 (i == 0) ? "%s" : " %s",
7078 type_str);
7079 }
7080 buf += sprintf(buf, "\n");
7081 return buf - orig_buf;
7082}
7083
7084static ssize_t show_plat_type(struct device *dev,
7085 struct device_attribute *attr, char *buf)
7086{
7087 struct platform_device *plat_dev = to_platform_device(dev);
7088 struct niu_parent *p = plat_dev->dev.platform_data;
7089 const char *type_str;
7090
7091 switch (p->plat_type) {
7092 case PLAT_TYPE_ATLAS:
7093 type_str = "atlas";
7094 break;
7095 case PLAT_TYPE_NIU:
7096 type_str = "niu";
7097 break;
7098 case PLAT_TYPE_VF_P0:
7099 type_str = "vf_p0";
7100 break;
7101 case PLAT_TYPE_VF_P1:
7102 type_str = "vf_p1";
7103 break;
7104 default:
7105 type_str = "unknown";
7106 break;
7107 }
7108
7109 return sprintf(buf, "%s\n", type_str);
7110}
7111
7112static ssize_t __show_chan_per_port(struct device *dev,
7113 struct device_attribute *attr, char *buf,
7114 int rx)
7115{
7116 struct platform_device *plat_dev = to_platform_device(dev);
7117 struct niu_parent *p = plat_dev->dev.platform_data;
7118 char *orig_buf = buf;
7119 u8 *arr;
7120 int i;
7121
7122 arr = (rx ? p->rxchan_per_port : p->txchan_per_port);
7123
7124 for (i = 0; i < p->num_ports; i++) {
7125 buf += sprintf(buf,
7126 (i == 0) ? "%d" : " %d",
7127 arr[i]);
7128 }
7129 buf += sprintf(buf, "\n");
7130
7131 return buf - orig_buf;
7132}
7133
7134static ssize_t show_rxchan_per_port(struct device *dev,
7135 struct device_attribute *attr, char *buf)
7136{
7137 return __show_chan_per_port(dev, attr, buf, 1);
7138}
7139
7140static ssize_t show_txchan_per_port(struct device *dev,
7141 struct device_attribute *attr, char *buf)
7142{
7143 return __show_chan_per_port(dev, attr, buf, 1);
7144}
7145
7146static ssize_t show_num_ports(struct device *dev,
7147 struct device_attribute *attr, char *buf)
7148{
7149 struct platform_device *plat_dev = to_platform_device(dev);
7150 struct niu_parent *p = plat_dev->dev.platform_data;
7151
7152 return sprintf(buf, "%d\n", p->num_ports);
7153}
7154
7155static struct device_attribute niu_parent_attributes[] = {
7156 __ATTR(port_phy, S_IRUGO, show_port_phy, NULL),
7157 __ATTR(plat_type, S_IRUGO, show_plat_type, NULL),
7158 __ATTR(rxchan_per_port, S_IRUGO, show_rxchan_per_port, NULL),
7159 __ATTR(txchan_per_port, S_IRUGO, show_txchan_per_port, NULL),
7160 __ATTR(num_ports, S_IRUGO, show_num_ports, NULL),
7161 {}
7162};
7163
7164static struct niu_parent * __devinit niu_new_parent(struct niu *np,
7165 union niu_parent_id *id,
7166 u8 ptype)
7167{
7168 struct platform_device *plat_dev;
7169 struct niu_parent *p;
7170 int i;
7171
7172 niudbg(PROBE, "niu_new_parent: Creating new parent.\n");
7173
7174 plat_dev = platform_device_register_simple("niu", niu_parent_index,
7175 NULL, 0);
7176 if (!plat_dev)
7177 return NULL;
7178
7179 for (i = 0; attr_name(niu_parent_attributes[i]); i++) {
7180 int err = device_create_file(&plat_dev->dev,
7181 &niu_parent_attributes[i]);
7182 if (err)
7183 goto fail_unregister;
7184 }
7185
7186 p = kzalloc(sizeof(*p), GFP_KERNEL);
7187 if (!p)
7188 goto fail_unregister;
7189
7190 p->index = niu_parent_index++;
7191
7192 plat_dev->dev.platform_data = p;
7193 p->plat_dev = plat_dev;
7194
7195 memcpy(&p->id, id, sizeof(*id));
7196 p->plat_type = ptype;
7197 INIT_LIST_HEAD(&p->list);
7198 atomic_set(&p->refcnt, 0);
7199 list_add(&p->list, &niu_parent_list);
7200 spin_lock_init(&p->lock);
7201
7202 p->rxdma_clock_divider = 7500;
7203
7204 p->tcam_num_entries = NIU_PCI_TCAM_ENTRIES;
7205 if (p->plat_type == PLAT_TYPE_NIU)
7206 p->tcam_num_entries = NIU_NONPCI_TCAM_ENTRIES;
7207
7208 for (i = CLASS_CODE_USER_PROG1; i <= CLASS_CODE_SCTP_IPV6; i++) {
7209 int index = i - CLASS_CODE_USER_PROG1;
7210
7211 p->tcam_key[index] = TCAM_KEY_TSEL;
7212 p->flow_key[index] = (FLOW_KEY_IPSA |
7213 FLOW_KEY_IPDA |
7214 FLOW_KEY_PROTO |
7215 (FLOW_KEY_L4_BYTE12 <<
7216 FLOW_KEY_L4_0_SHIFT) |
7217 (FLOW_KEY_L4_BYTE12 <<
7218 FLOW_KEY_L4_1_SHIFT));
7219 }
7220
7221 for (i = 0; i < LDN_MAX + 1; i++)
7222 p->ldg_map[i] = LDG_INVALID;
7223
7224 return p;
7225
7226fail_unregister:
7227 platform_device_unregister(plat_dev);
7228 return NULL;
7229}
7230
7231static struct niu_parent * __devinit niu_get_parent(struct niu *np,
7232 union niu_parent_id *id,
7233 u8 ptype)
7234{
7235 struct niu_parent *p, *tmp;
7236 int port = np->port;
7237
7238 niudbg(PROBE, "niu_get_parent: platform_type[%u] port[%u]\n",
7239 ptype, port);
7240
7241 mutex_lock(&niu_parent_lock);
7242 p = NULL;
7243 list_for_each_entry(tmp, &niu_parent_list, list) {
7244 if (!memcmp(id, &tmp->id, sizeof(*id))) {
7245 p = tmp;
7246 break;
7247 }
7248 }
7249 if (!p)
7250 p = niu_new_parent(np, id, ptype);
7251
7252 if (p) {
7253 char port_name[6];
7254 int err;
7255
7256 sprintf(port_name, "port%d", port);
7257 err = sysfs_create_link(&p->plat_dev->dev.kobj,
7258 &np->device->kobj,
7259 port_name);
7260 if (!err) {
7261 p->ports[port] = np;
7262 atomic_inc(&p->refcnt);
7263 }
7264 }
7265 mutex_unlock(&niu_parent_lock);
7266
7267 return p;
7268}
7269
7270static void niu_put_parent(struct niu *np)
7271{
7272 struct niu_parent *p = np->parent;
7273 u8 port = np->port;
7274 char port_name[6];
7275
7276 BUG_ON(!p || p->ports[port] != np);
7277
7278 niudbg(PROBE, "niu_put_parent: port[%u]\n", port);
7279
7280 sprintf(port_name, "port%d", port);
7281
7282 mutex_lock(&niu_parent_lock);
7283
7284 sysfs_remove_link(&p->plat_dev->dev.kobj, port_name);
7285
7286 p->ports[port] = NULL;
7287 np->parent = NULL;
7288
7289 if (atomic_dec_and_test(&p->refcnt)) {
7290 list_del(&p->list);
7291 platform_device_unregister(p->plat_dev);
7292 }
7293
7294 mutex_unlock(&niu_parent_lock);
7295}
7296
7297static void *niu_pci_alloc_coherent(struct device *dev, size_t size,
7298 u64 *handle, gfp_t flag)
7299{
7300 dma_addr_t dh;
7301 void *ret;
7302
7303 ret = dma_alloc_coherent(dev, size, &dh, flag);
7304 if (ret)
7305 *handle = dh;
7306 return ret;
7307}
7308
7309static void niu_pci_free_coherent(struct device *dev, size_t size,
7310 void *cpu_addr, u64 handle)
7311{
7312 dma_free_coherent(dev, size, cpu_addr, handle);
7313}
7314
7315static u64 niu_pci_map_page(struct device *dev, struct page *page,
7316 unsigned long offset, size_t size,
7317 enum dma_data_direction direction)
7318{
7319 return dma_map_page(dev, page, offset, size, direction);
7320}
7321
7322static void niu_pci_unmap_page(struct device *dev, u64 dma_address,
7323 size_t size, enum dma_data_direction direction)
7324{
7325 return dma_unmap_page(dev, dma_address, size, direction);
7326}
7327
7328static u64 niu_pci_map_single(struct device *dev, void *cpu_addr,
7329 size_t size,
7330 enum dma_data_direction direction)
7331{
7332 return dma_map_single(dev, cpu_addr, size, direction);
7333}
7334
7335static void niu_pci_unmap_single(struct device *dev, u64 dma_address,
7336 size_t size,
7337 enum dma_data_direction direction)
7338{
7339 dma_unmap_single(dev, dma_address, size, direction);
7340}
7341
7342static const struct niu_ops niu_pci_ops = {
7343 .alloc_coherent = niu_pci_alloc_coherent,
7344 .free_coherent = niu_pci_free_coherent,
7345 .map_page = niu_pci_map_page,
7346 .unmap_page = niu_pci_unmap_page,
7347 .map_single = niu_pci_map_single,
7348 .unmap_single = niu_pci_unmap_single,
7349};
7350
7351static void __devinit niu_driver_version(void)
7352{
7353 static int niu_version_printed;
7354
7355 if (niu_version_printed++ == 0)
7356 pr_info("%s", version);
7357}
7358
7359static struct net_device * __devinit niu_alloc_and_init(
7360 struct device *gen_dev, struct pci_dev *pdev,
7361 struct of_device *op, const struct niu_ops *ops,
7362 u8 port)
7363{
7364 struct net_device *dev = alloc_etherdev(sizeof(struct niu));
7365 struct niu *np;
7366
7367 if (!dev) {
7368 dev_err(gen_dev, PFX "Etherdev alloc failed, aborting.\n");
7369 return NULL;
7370 }
7371
7372 SET_NETDEV_DEV(dev, gen_dev);
7373
7374 np = netdev_priv(dev);
7375 np->dev = dev;
7376 np->pdev = pdev;
7377 np->op = op;
7378 np->device = gen_dev;
7379 np->ops = ops;
7380
7381 np->msg_enable = niu_debug;
7382
7383 spin_lock_init(&np->lock);
7384 INIT_WORK(&np->reset_task, niu_reset_task);
7385
7386 np->port = port;
7387
7388 return dev;
7389}
7390
7391static void __devinit niu_assign_netdev_ops(struct net_device *dev)
7392{
7393 dev->open = niu_open;
7394 dev->stop = niu_close;
7395 dev->get_stats = niu_get_stats;
7396 dev->set_multicast_list = niu_set_rx_mode;
7397 dev->set_mac_address = niu_set_mac_addr;
7398 dev->do_ioctl = niu_ioctl;
7399 dev->tx_timeout = niu_tx_timeout;
7400 dev->hard_start_xmit = niu_start_xmit;
7401 dev->ethtool_ops = &niu_ethtool_ops;
7402 dev->watchdog_timeo = NIU_TX_TIMEOUT;
7403 dev->change_mtu = niu_change_mtu;
7404}
7405
7406static void __devinit niu_device_announce(struct niu *np)
7407{
7408 struct net_device *dev = np->dev;
7409 int i;
7410
7411 pr_info("%s: NIU Ethernet ", dev->name);
7412 for (i = 0; i < 6; i++)
7413 printk("%2.2x%c", dev->dev_addr[i],
7414 i == 5 ? '\n' : ':');
7415
7416 pr_info("%s: Port type[%s] mode[%s:%s] XCVR[%s] phy[%s]\n",
7417 dev->name,
7418 (np->flags & NIU_FLAGS_XMAC ? "XMAC" : "BMAC"),
7419 (np->flags & NIU_FLAGS_10G ? "10G" : "1G"),
7420 (np->flags & NIU_FLAGS_FIBER ? "FIBER" : "COPPER"),
7421 (np->mac_xcvr == MAC_XCVR_MII ? "MII" :
7422 (np->mac_xcvr == MAC_XCVR_PCS ? "PCS" : "XPCS")),
7423 np->vpd.phy_type);
7424}
7425
7426static int __devinit niu_pci_init_one(struct pci_dev *pdev,
7427 const struct pci_device_id *ent)
7428{
7429 unsigned long niureg_base, niureg_len;
7430 union niu_parent_id parent_id;
7431 struct net_device *dev;
7432 struct niu *np;
7433 int err, pos;
7434 u64 dma_mask;
7435 u16 val16;
7436
7437 niu_driver_version();
7438
7439 err = pci_enable_device(pdev);
7440 if (err) {
7441 dev_err(&pdev->dev, PFX "Cannot enable PCI device, "
7442 "aborting.\n");
7443 return err;
7444 }
7445
7446 if (!(pci_resource_flags(pdev, 0) & IORESOURCE_MEM) ||
7447 !(pci_resource_flags(pdev, 2) & IORESOURCE_MEM)) {
7448 dev_err(&pdev->dev, PFX "Cannot find proper PCI device "
7449 "base addresses, aborting.\n");
7450 err = -ENODEV;
7451 goto err_out_disable_pdev;
7452 }
7453
7454 err = pci_request_regions(pdev, DRV_MODULE_NAME);
7455 if (err) {
7456 dev_err(&pdev->dev, PFX "Cannot obtain PCI resources, "
7457 "aborting.\n");
7458 goto err_out_disable_pdev;
7459 }
7460
7461 pos = pci_find_capability(pdev, PCI_CAP_ID_EXP);
7462 if (pos <= 0) {
7463 dev_err(&pdev->dev, PFX "Cannot find PCI Express capability, "
7464 "aborting.\n");
7465 goto err_out_free_res;
7466 }
7467
7468 dev = niu_alloc_and_init(&pdev->dev, pdev, NULL,
7469 &niu_pci_ops, PCI_FUNC(pdev->devfn));
7470 if (!dev) {
7471 err = -ENOMEM;
7472 goto err_out_free_res;
7473 }
7474 np = netdev_priv(dev);
7475
7476 memset(&parent_id, 0, sizeof(parent_id));
7477 parent_id.pci.domain = pci_domain_nr(pdev->bus);
7478 parent_id.pci.bus = pdev->bus->number;
7479 parent_id.pci.device = PCI_SLOT(pdev->devfn);
7480
7481 np->parent = niu_get_parent(np, &parent_id,
7482 PLAT_TYPE_ATLAS);
7483 if (!np->parent) {
7484 err = -ENOMEM;
7485 goto err_out_free_dev;
7486 }
7487
7488 pci_read_config_word(pdev, pos + PCI_EXP_DEVCTL, &val16);
7489 val16 &= ~PCI_EXP_DEVCTL_NOSNOOP_EN;
7490 val16 |= (PCI_EXP_DEVCTL_CERE |
7491 PCI_EXP_DEVCTL_NFERE |
7492 PCI_EXP_DEVCTL_FERE |
7493 PCI_EXP_DEVCTL_URRE |
7494 PCI_EXP_DEVCTL_RELAX_EN);
7495 pci_write_config_word(pdev, pos + PCI_EXP_DEVCTL, val16);
7496
7497 dma_mask = DMA_44BIT_MASK;
7498 err = pci_set_dma_mask(pdev, dma_mask);
7499 if (!err) {
7500 dev->features |= NETIF_F_HIGHDMA;
7501 err = pci_set_consistent_dma_mask(pdev, dma_mask);
7502 if (err) {
7503 dev_err(&pdev->dev, PFX "Unable to obtain 44 bit "
7504 "DMA for consistent allocations, "
7505 "aborting.\n");
7506 goto err_out_release_parent;
7507 }
7508 }
7509 if (err || dma_mask == DMA_32BIT_MASK) {
7510 err = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
7511 if (err) {
7512 dev_err(&pdev->dev, PFX "No usable DMA configuration, "
7513 "aborting.\n");
7514 goto err_out_release_parent;
7515 }
7516 }
7517
7518 dev->features |= (NETIF_F_SG | NETIF_F_HW_CSUM);
7519
7520 niureg_base = pci_resource_start(pdev, 0);
7521 niureg_len = pci_resource_len(pdev, 0);
7522
7523 np->regs = ioremap_nocache(niureg_base, niureg_len);
7524 if (!np->regs) {
7525 dev_err(&pdev->dev, PFX "Cannot map device registers, "
7526 "aborting.\n");
7527 err = -ENOMEM;
7528 goto err_out_release_parent;
7529 }
7530
7531 pci_set_master(pdev);
7532 pci_save_state(pdev);
7533
7534 dev->irq = pdev->irq;
7535
7536 niu_assign_netdev_ops(dev);
7537
7538 err = niu_get_invariants(np);
7539 if (err) {
7540 if (err != -ENODEV)
7541 dev_err(&pdev->dev, PFX "Problem fetching invariants "
7542 "of chip, aborting.\n");
7543 goto err_out_iounmap;
7544 }
7545
7546 err = register_netdev(dev);
7547 if (err) {
7548 dev_err(&pdev->dev, PFX "Cannot register net device, "
7549 "aborting.\n");
7550 goto err_out_iounmap;
7551 }
7552
7553 pci_set_drvdata(pdev, dev);
7554
7555 niu_device_announce(np);
7556
7557 return 0;
7558
7559err_out_iounmap:
7560 if (np->regs) {
7561 iounmap(np->regs);
7562 np->regs = NULL;
7563 }
7564
7565err_out_release_parent:
7566 niu_put_parent(np);
7567
7568err_out_free_dev:
7569 free_netdev(dev);
7570
7571err_out_free_res:
7572 pci_release_regions(pdev);
7573
7574err_out_disable_pdev:
7575 pci_disable_device(pdev);
7576 pci_set_drvdata(pdev, NULL);
7577
7578 return err;
7579}
7580
7581static void __devexit niu_pci_remove_one(struct pci_dev *pdev)
7582{
7583 struct net_device *dev = pci_get_drvdata(pdev);
7584
7585 if (dev) {
7586 struct niu *np = netdev_priv(dev);
7587
7588 unregister_netdev(dev);
7589 if (np->regs) {
7590 iounmap(np->regs);
7591 np->regs = NULL;
7592 }
7593
7594 niu_ldg_free(np);
7595
7596 niu_put_parent(np);
7597
7598 free_netdev(dev);
7599 pci_release_regions(pdev);
7600 pci_disable_device(pdev);
7601 pci_set_drvdata(pdev, NULL);
7602 }
7603}
7604
7605static int niu_suspend(struct pci_dev *pdev, pm_message_t state)
7606{
7607 struct net_device *dev = pci_get_drvdata(pdev);
7608 struct niu *np = netdev_priv(dev);
7609 unsigned long flags;
7610
7611 if (!netif_running(dev))
7612 return 0;
7613
7614 flush_scheduled_work();
7615 niu_netif_stop(np);
7616
7617 del_timer_sync(&np->timer);
7618
7619 spin_lock_irqsave(&np->lock, flags);
7620 niu_enable_interrupts(np, 0);
7621 spin_unlock_irqrestore(&np->lock, flags);
7622
7623 netif_device_detach(dev);
7624
7625 spin_lock_irqsave(&np->lock, flags);
7626 niu_stop_hw(np);
7627 spin_unlock_irqrestore(&np->lock, flags);
7628
7629 pci_save_state(pdev);
7630
7631 return 0;
7632}
7633
7634static int niu_resume(struct pci_dev *pdev)
7635{
7636 struct net_device *dev = pci_get_drvdata(pdev);
7637 struct niu *np = netdev_priv(dev);
7638 unsigned long flags;
7639 int err;
7640
7641 if (!netif_running(dev))
7642 return 0;
7643
7644 pci_restore_state(pdev);
7645
7646 netif_device_attach(dev);
7647
7648 spin_lock_irqsave(&np->lock, flags);
7649
7650 err = niu_init_hw(np);
7651 if (!err) {
7652 np->timer.expires = jiffies + HZ;
7653 add_timer(&np->timer);
7654 niu_netif_start(np);
7655 }
7656
7657 spin_unlock_irqrestore(&np->lock, flags);
7658
7659 return err;
7660}
7661
7662static struct pci_driver niu_pci_driver = {
7663 .name = DRV_MODULE_NAME,
7664 .id_table = niu_pci_tbl,
7665 .probe = niu_pci_init_one,
7666 .remove = __devexit_p(niu_pci_remove_one),
7667 .suspend = niu_suspend,
7668 .resume = niu_resume,
7669};
7670
7671#ifdef CONFIG_SPARC64
7672static void *niu_phys_alloc_coherent(struct device *dev, size_t size,
7673 u64 *dma_addr, gfp_t flag)
7674{
7675 unsigned long order = get_order(size);
7676 unsigned long page = __get_free_pages(flag, order);
7677
7678 if (page == 0UL)
7679 return NULL;
7680 memset((char *)page, 0, PAGE_SIZE << order);
7681 *dma_addr = __pa(page);
7682
7683 return (void *) page;
7684}
7685
7686static void niu_phys_free_coherent(struct device *dev, size_t size,
7687 void *cpu_addr, u64 handle)
7688{
7689 unsigned long order = get_order(size);
7690
7691 free_pages((unsigned long) cpu_addr, order);
7692}
7693
7694static u64 niu_phys_map_page(struct device *dev, struct page *page,
7695 unsigned long offset, size_t size,
7696 enum dma_data_direction direction)
7697{
7698 return page_to_phys(page) + offset;
7699}
7700
7701static void niu_phys_unmap_page(struct device *dev, u64 dma_address,
7702 size_t size, enum dma_data_direction direction)
7703{
7704 /* Nothing to do. */
7705}
7706
7707static u64 niu_phys_map_single(struct device *dev, void *cpu_addr,
7708 size_t size,
7709 enum dma_data_direction direction)
7710{
7711 return __pa(cpu_addr);
7712}
7713
7714static void niu_phys_unmap_single(struct device *dev, u64 dma_address,
7715 size_t size,
7716 enum dma_data_direction direction)
7717{
7718 /* Nothing to do. */
7719}
7720
7721static const struct niu_ops niu_phys_ops = {
7722 .alloc_coherent = niu_phys_alloc_coherent,
7723 .free_coherent = niu_phys_free_coherent,
7724 .map_page = niu_phys_map_page,
7725 .unmap_page = niu_phys_unmap_page,
7726 .map_single = niu_phys_map_single,
7727 .unmap_single = niu_phys_unmap_single,
7728};
7729
7730static unsigned long res_size(struct resource *r)
7731{
7732 return r->end - r->start + 1UL;
7733}
7734
7735static int __devinit niu_of_probe(struct of_device *op,
7736 const struct of_device_id *match)
7737{
7738 union niu_parent_id parent_id;
7739 struct net_device *dev;
7740 struct niu *np;
7741 const u32 *reg;
7742 int err;
7743
7744 niu_driver_version();
7745
7746 reg = of_get_property(op->node, "reg", NULL);
7747 if (!reg) {
7748 dev_err(&op->dev, PFX "%s: No 'reg' property, aborting.\n",
7749 op->node->full_name);
7750 return -ENODEV;
7751 }
7752
7753 dev = niu_alloc_and_init(&op->dev, NULL, op,
7754 &niu_phys_ops, reg[0] & 0x1);
7755 if (!dev) {
7756 err = -ENOMEM;
7757 goto err_out;
7758 }
7759 np = netdev_priv(dev);
7760
7761 memset(&parent_id, 0, sizeof(parent_id));
7762 parent_id.of = of_get_parent(op->node);
7763
7764 np->parent = niu_get_parent(np, &parent_id,
7765 PLAT_TYPE_NIU);
7766 if (!np->parent) {
7767 err = -ENOMEM;
7768 goto err_out_free_dev;
7769 }
7770
7771 dev->features |= (NETIF_F_SG | NETIF_F_HW_CSUM);
7772
7773 np->regs = of_ioremap(&op->resource[1], 0,
7774 res_size(&op->resource[1]),
7775 "niu regs");
7776 if (!np->regs) {
7777 dev_err(&op->dev, PFX "Cannot map device registers, "
7778 "aborting.\n");
7779 err = -ENOMEM;
7780 goto err_out_release_parent;
7781 }
7782
7783 np->vir_regs_1 = of_ioremap(&op->resource[2], 0,
7784 res_size(&op->resource[2]),
7785 "niu vregs-1");
7786 if (!np->vir_regs_1) {
7787 dev_err(&op->dev, PFX "Cannot map device vir registers 1, "
7788 "aborting.\n");
7789 err = -ENOMEM;
7790 goto err_out_iounmap;
7791 }
7792
7793 np->vir_regs_2 = of_ioremap(&op->resource[3], 0,
7794 res_size(&op->resource[3]),
7795 "niu vregs-2");
7796 if (!np->vir_regs_2) {
7797 dev_err(&op->dev, PFX "Cannot map device vir registers 2, "
7798 "aborting.\n");
7799 err = -ENOMEM;
7800 goto err_out_iounmap;
7801 }
7802
7803 niu_assign_netdev_ops(dev);
7804
7805 err = niu_get_invariants(np);
7806 if (err) {
7807 if (err != -ENODEV)
7808 dev_err(&op->dev, PFX "Problem fetching invariants "
7809 "of chip, aborting.\n");
7810 goto err_out_iounmap;
7811 }
7812
7813 err = register_netdev(dev);
7814 if (err) {
7815 dev_err(&op->dev, PFX "Cannot register net device, "
7816 "aborting.\n");
7817 goto err_out_iounmap;
7818 }
7819
7820 dev_set_drvdata(&op->dev, dev);
7821
7822 niu_device_announce(np);
7823
7824 return 0;
7825
7826err_out_iounmap:
7827 if (np->vir_regs_1) {
7828 of_iounmap(&op->resource[2], np->vir_regs_1,
7829 res_size(&op->resource[2]));
7830 np->vir_regs_1 = NULL;
7831 }
7832
7833 if (np->vir_regs_2) {
7834 of_iounmap(&op->resource[3], np->vir_regs_2,
7835 res_size(&op->resource[3]));
7836 np->vir_regs_2 = NULL;
7837 }
7838
7839 if (np->regs) {
7840 of_iounmap(&op->resource[1], np->regs,
7841 res_size(&op->resource[1]));
7842 np->regs = NULL;
7843 }
7844
7845err_out_release_parent:
7846 niu_put_parent(np);
7847
7848err_out_free_dev:
7849 free_netdev(dev);
7850
7851err_out:
7852 return err;
7853}
7854
7855static int __devexit niu_of_remove(struct of_device *op)
7856{
7857 struct net_device *dev = dev_get_drvdata(&op->dev);
7858
7859 if (dev) {
7860 struct niu *np = netdev_priv(dev);
7861
7862 unregister_netdev(dev);
7863
7864 if (np->vir_regs_1) {
7865 of_iounmap(&op->resource[2], np->vir_regs_1,
7866 res_size(&op->resource[2]));
7867 np->vir_regs_1 = NULL;
7868 }
7869
7870 if (np->vir_regs_2) {
7871 of_iounmap(&op->resource[3], np->vir_regs_2,
7872 res_size(&op->resource[3]));
7873 np->vir_regs_2 = NULL;
7874 }
7875
7876 if (np->regs) {
7877 of_iounmap(&op->resource[1], np->regs,
7878 res_size(&op->resource[1]));
7879 np->regs = NULL;
7880 }
7881
7882 niu_ldg_free(np);
7883
7884 niu_put_parent(np);
7885
7886 free_netdev(dev);
7887 dev_set_drvdata(&op->dev, NULL);
7888 }
7889 return 0;
7890}
7891
7892static struct of_device_id niu_match[] = {
7893 {
7894 .name = "network",
7895 .compatible = "SUNW,niusl",
7896 },
7897 {},
7898};
7899MODULE_DEVICE_TABLE(of, niu_match);
7900
7901static struct of_platform_driver niu_of_driver = {
7902 .name = "niu",
7903 .match_table = niu_match,
7904 .probe = niu_of_probe,
7905 .remove = __devexit_p(niu_of_remove),
7906};
7907
7908#endif /* CONFIG_SPARC64 */
7909
7910static int __init niu_init(void)
7911{
7912 int err = 0;
7913
Olof Johansson81429972007-10-21 16:32:58 -0700[diff] [blame]7914 BUILD_BUG_ON(PAGE_SIZE < 4 * 1024);
David S. Millera3138df2007-10-09 01:54:01 -0700[diff] [blame]7915
7916 niu_debug = netif_msg_init(debug, NIU_MSG_DEFAULT);
7917
7918#ifdef CONFIG_SPARC64
7919 err = of_register_driver(&niu_of_driver, &of_bus_type);
7920#endif
7921
7922 if (!err) {
7923 err = pci_register_driver(&niu_pci_driver);
7924#ifdef CONFIG_SPARC64
7925 if (err)
7926 of_unregister_driver(&niu_of_driver);
7927#endif
7928 }
7929
7930 return err;
7931}
7932
7933static void __exit niu_exit(void)
7934{
7935 pci_unregister_driver(&niu_pci_driver);
7936#ifdef CONFIG_SPARC64
7937 of_unregister_driver(&niu_of_driver);
7938#endif
7939}
7940
7941module_init(niu_init);
7942module_exit(niu_exit);