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Syed Mohammed, Khasimcc26b3b2008-10-09 17:51:41 +03001/*
2 * linux/arch/arm/mach-omap3/sram.S
3 *
4 * Omap3 specific functions that need to be run in internal SRAM
5 *
Paul Walmsley4267b5d2009-06-19 19:08:27 -06006 * Copyright (C) 2004, 2007, 2008 Texas Instruments, Inc.
7 * Copyright (C) 2008 Nokia Corporation
Syed Mohammed, Khasimcc26b3b2008-10-09 17:51:41 +03008 *
Paul Walmsley4267b5d2009-06-19 19:08:27 -06009 * Rajendra Nayak <rnayak@ti.com>
Syed Mohammed, Khasimcc26b3b2008-10-09 17:51:41 +030010 * Richard Woodruff <r-woodruff2@ti.com>
Paul Walmsley4267b5d2009-06-19 19:08:27 -060011 * Paul Walmsley
Syed Mohammed, Khasimcc26b3b2008-10-09 17:51:41 +030012 *
13 * This program is free software; you can redistribute it and/or
14 * modify it under the terms of the GNU General Public License as
15 * published by the Free Software Foundation; either version 2 of
16 * the License, or (at your option) any later version.
17 *
18 * This program is distributed in the hope that it will be useful,
19 * but WITHOUT ANY WARRANTY; without even the implied warranty of
20 * MERCHANTABILITY or FITNESS FOR A PARTICULAR /PURPOSE. See the
21 * GNU General Public License for more details.
22 *
23 * You should have received a copy of the GNU General Public License
24 * along with this program; if not, write to the Free Software
25 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
26 * MA 02111-1307 USA
27 */
28#include <linux/linkage.h>
29#include <asm/assembler.h>
30#include <mach/hardware.h>
31
32#include <mach/io.h>
33
34#include "sdrc.h"
35#include "cm.h"
36
37 .text
38
Paul Walmsleydf14e472009-06-19 19:08:28 -060039/* r4 parameters */
40#define SDRC_NO_UNLOCK_DLL 0x0
41#define SDRC_UNLOCK_DLL 0x1
42
43/* SDRC_DLLA_CTRL bit settings */
Paul Walmsley7b7bcef2009-06-19 19:08:29 -060044#define FIXEDDELAY_SHIFT 24
45#define FIXEDDELAY_MASK (0xff << FIXEDDELAY_SHIFT)
Paul Walmsleydf14e472009-06-19 19:08:28 -060046#define DLLIDLE_MASK 0x4
47
Paul Walmsley7b7bcef2009-06-19 19:08:29 -060048/*
49 * SDRC_DLLA_CTRL default values: TI hardware team indicates that
50 * FIXEDDELAY should be initialized to 0xf. This apparently was
51 * empirically determined during process testing, so no derivation
52 * was provided.
53 */
54#define FIXEDDELAY_DEFAULT (0x0f << FIXEDDELAY_SHIFT)
55
Paul Walmsleydf14e472009-06-19 19:08:28 -060056/* SDRC_DLLA_STATUS bit settings */
57#define LOCKSTATUS_MASK 0x4
58
59/* SDRC_POWER bit settings */
60#define SRFRONIDLEREQ_MASK 0x40
61#define PWDENA_MASK 0x4
62
63/* CM_IDLEST1_CORE bit settings */
64#define ST_SDRC_MASK 0x2
65
66/* CM_ICLKEN1_CORE bit settings */
67#define EN_SDRC_MASK 0x2
68
69/* CM_CLKSEL1_PLL bit settings */
70#define CORE_DPLL_CLKOUT_DIV_SHIFT 0x1b
71
Syed Mohammed, Khasimcc26b3b2008-10-09 17:51:41 +030072/*
Paul Walmsley4267b5d2009-06-19 19:08:27 -060073 * omap3_sram_configure_core_dpll - change DPLL3 M2 divider
74 * r0 = new SDRC_RFR_CTRL register contents
75 * r1 = new SDRC_ACTIM_CTRLA register contents
76 * r2 = new SDRC_ACTIM_CTRLB register contents
77 * r3 = new M2 divider setting (only 1 and 2 supported right now)
78 * r4 = unlock SDRC DLL? (1 = yes, 0 = no). Only unlock DLL for
Paul Walmsley4519c2b2009-05-12 17:26:32 -060079 * SDRC rates < 83MHz
Paul Walmsleyc9812d02009-06-19 19:08:26 -060080 * r5 = number of MPU cycles to wait for SDRC to stabilize after
81 * reprogramming the SDRC when switching to a slower MPU speed
Paul Walmsley4267b5d2009-06-19 19:08:27 -060082 * r6 = new SDRC_MR_0 register value
Tero Kristo3afec632009-06-19 19:08:29 -060083 * r7 = increasing SDRC rate? (1 = yes, 0 = no)
Paul Walmsleyc9812d02009-06-19 19:08:26 -060084 *
Syed Mohammed, Khasimcc26b3b2008-10-09 17:51:41 +030085 */
86ENTRY(omap3_sram_configure_core_dpll)
87 stmfd sp!, {r1-r12, lr} @ store regs to stack
Paul Walmsley4519c2b2009-05-12 17:26:32 -060088 ldr r4, [sp, #52] @ pull extra args off the stack
Paul Walmsleyc9812d02009-06-19 19:08:26 -060089 ldr r5, [sp, #56] @ load extra args from the stack
Paul Walmsleyd0ba3922009-06-19 19:08:27 -060090 ldr r6, [sp, #60] @ load extra args from the stack
Tero Kristo3afec632009-06-19 19:08:29 -060091 ldr r7, [sp, #64] @ load extra args from the stack
Paul Walmsley69d42552009-05-12 17:27:09 -060092 dsb @ flush buffered writes to interconnect
Tero Kristo3afec632009-06-19 19:08:29 -060093 cmp r7, #1 @ if increasing SDRC clk rate,
94 bleq configure_sdrc @ program the SDRC regs early (for RFR)
Paul Walmsleydf14e472009-06-19 19:08:28 -060095 cmp r4, #SDRC_UNLOCK_DLL @ set the intended DLL state
Paul Walmsley4519c2b2009-05-12 17:26:32 -060096 bleq unlock_dll
Syed Mohammed, Khasimcc26b3b2008-10-09 17:51:41 +030097 blne lock_dll
Paul Walmsley4267b5d2009-06-19 19:08:27 -060098 bl sdram_in_selfrefresh @ put SDRAM in self refresh, idle SDRC
99 bl configure_core_dpll @ change the DPLL3 M2 divider
100 bl enable_sdrc @ take SDRC out of idle
Paul Walmsleydf14e472009-06-19 19:08:28 -0600101 cmp r4, #SDRC_UNLOCK_DLL @ wait for DLL status to change
Paul Walmsley4519c2b2009-05-12 17:26:32 -0600102 bleq wait_dll_unlock
Syed Mohammed, Khasimcc26b3b2008-10-09 17:51:41 +0300103 blne wait_dll_lock
Tero Kristo3afec632009-06-19 19:08:29 -0600104 cmp r7, #1 @ if increasing SDRC clk rate,
Paul Walmsley4267b5d2009-06-19 19:08:27 -0600105 beq return_to_sdram @ return to SDRAM code, otherwise,
106 bl configure_sdrc @ reprogram SDRC regs now
107 mov r12, r5
108 bl wait_clk_stable @ wait for SDRC to stabilize
Paul Walmsleyc9812d02009-06-19 19:08:26 -0600109return_to_sdram:
Paul Walmsley69d42552009-05-12 17:27:09 -0600110 isb @ prevent speculative exec past here
Syed Mohammed, Khasimcc26b3b2008-10-09 17:51:41 +0300111 mov r0, #0 @ return value
112 ldmfd sp!, {r1-r12, pc} @ restore regs and return
113unlock_dll:
Paul Walmsleyb2abb272009-05-12 17:27:10 -0600114 ldr r11, omap3_sdrc_dlla_ctrl
115 ldr r12, [r11]
Paul Walmsley7b7bcef2009-06-19 19:08:29 -0600116 and r12, r12, #FIXEDDELAY_MASK
117 orr r12, r12, #FIXEDDELAY_DEFAULT
Paul Walmsleydf14e472009-06-19 19:08:28 -0600118 orr r12, r12, #DLLIDLE_MASK
Paul Walmsleyb2abb272009-05-12 17:27:10 -0600119 str r12, [r11] @ (no OCP barrier needed)
Syed Mohammed, Khasimcc26b3b2008-10-09 17:51:41 +0300120 bx lr
121lock_dll:
Paul Walmsleyb2abb272009-05-12 17:27:10 -0600122 ldr r11, omap3_sdrc_dlla_ctrl
123 ldr r12, [r11]
Paul Walmsleydf14e472009-06-19 19:08:28 -0600124 bic r12, r12, #DLLIDLE_MASK
Paul Walmsleyb2abb272009-05-12 17:27:10 -0600125 str r12, [r11] @ (no OCP barrier needed)
Syed Mohammed, Khasimcc26b3b2008-10-09 17:51:41 +0300126 bx lr
127sdram_in_selfrefresh:
Paul Walmsleyb2abb272009-05-12 17:27:10 -0600128 ldr r11, omap3_sdrc_power @ read the SDRC_POWER register
129 ldr r12, [r11] @ read the contents of SDRC_POWER
130 mov r9, r12 @ keep a copy of SDRC_POWER bits
Paul Walmsleydf14e472009-06-19 19:08:28 -0600131 orr r12, r12, #SRFRONIDLEREQ_MASK @ enable self refresh on idle
132 bic r12, r12, #PWDENA_MASK @ clear PWDENA
Paul Walmsleyb2abb272009-05-12 17:27:10 -0600133 str r12, [r11] @ write back to SDRC_POWER register
134 ldr r12, [r11] @ posted-write barrier for SDRC
Paul Walmsley4267b5d2009-06-19 19:08:27 -0600135idle_sdrc:
Paul Walmsleyb2abb272009-05-12 17:27:10 -0600136 ldr r11, omap3_cm_iclken1_core @ read the CM_ICLKEN1_CORE reg
137 ldr r12, [r11]
Paul Walmsleydf14e472009-06-19 19:08:28 -0600138 bic r12, r12, #EN_SDRC_MASK @ disable iclk bit for SDRC
Paul Walmsleyb2abb272009-05-12 17:27:10 -0600139 str r12, [r11]
Syed Mohammed, Khasimcc26b3b2008-10-09 17:51:41 +0300140wait_sdrc_idle:
Paul Walmsleyb2abb272009-05-12 17:27:10 -0600141 ldr r11, omap3_cm_idlest1_core
142 ldr r12, [r11]
Paul Walmsleydf14e472009-06-19 19:08:28 -0600143 and r12, r12, #ST_SDRC_MASK @ check for SDRC idle
144 cmp r12, #ST_SDRC_MASK
Syed Mohammed, Khasimcc26b3b2008-10-09 17:51:41 +0300145 bne wait_sdrc_idle
146 bx lr
147configure_core_dpll:
Paul Walmsleyb2abb272009-05-12 17:27:10 -0600148 ldr r11, omap3_cm_clksel1_pll
149 ldr r12, [r11]
150 ldr r10, core_m2_mask_val @ modify m2 for core dpll
151 and r12, r12, r10
Paul Walmsleydf14e472009-06-19 19:08:28 -0600152 orr r12, r12, r3, lsl #CORE_DPLL_CLKOUT_DIV_SHIFT
Paul Walmsleyb2abb272009-05-12 17:27:10 -0600153 str r12, [r11]
154 ldr r12, [r11] @ posted-write barrier for CM
Syed Mohammed, Khasimcc26b3b2008-10-09 17:51:41 +0300155 bx lr
156wait_clk_stable:
Paul Walmsleyb2abb272009-05-12 17:27:10 -0600157 subs r12, r12, #1
Syed Mohammed, Khasimcc26b3b2008-10-09 17:51:41 +0300158 bne wait_clk_stable
Syed Mohammed, Khasimcc26b3b2008-10-09 17:51:41 +0300159 bx lr
160enable_sdrc:
Paul Walmsleyb2abb272009-05-12 17:27:10 -0600161 ldr r11, omap3_cm_iclken1_core
162 ldr r12, [r11]
Paul Walmsleydf14e472009-06-19 19:08:28 -0600163 orr r12, r12, #EN_SDRC_MASK @ enable iclk bit for SDRC
Paul Walmsleyb2abb272009-05-12 17:27:10 -0600164 str r12, [r11]
Syed Mohammed, Khasimcc26b3b2008-10-09 17:51:41 +0300165wait_sdrc_idle1:
Paul Walmsleyb2abb272009-05-12 17:27:10 -0600166 ldr r11, omap3_cm_idlest1_core
167 ldr r12, [r11]
Paul Walmsleydf14e472009-06-19 19:08:28 -0600168 and r12, r12, #ST_SDRC_MASK
Paul Walmsleyb2abb272009-05-12 17:27:10 -0600169 cmp r12, #0
Syed Mohammed, Khasimcc26b3b2008-10-09 17:51:41 +0300170 bne wait_sdrc_idle1
Paul Walmsleyfa0406a2009-05-12 17:27:09 -0600171restore_sdrc_power_val:
Paul Walmsleyb2abb272009-05-12 17:27:10 -0600172 ldr r11, omap3_sdrc_power
173 str r9, [r11] @ restore SDRC_POWER, no barrier needed
Syed Mohammed, Khasimcc26b3b2008-10-09 17:51:41 +0300174 bx lr
175wait_dll_lock:
Paul Walmsleyb2abb272009-05-12 17:27:10 -0600176 ldr r11, omap3_sdrc_dlla_status
177 ldr r12, [r11]
Paul Walmsleydf14e472009-06-19 19:08:28 -0600178 and r12, r12, #LOCKSTATUS_MASK
179 cmp r12, #LOCKSTATUS_MASK
Syed Mohammed, Khasimcc26b3b2008-10-09 17:51:41 +0300180 bne wait_dll_lock
181 bx lr
182wait_dll_unlock:
Paul Walmsleyb2abb272009-05-12 17:27:10 -0600183 ldr r11, omap3_sdrc_dlla_status
184 ldr r12, [r11]
Paul Walmsleydf14e472009-06-19 19:08:28 -0600185 and r12, r12, #LOCKSTATUS_MASK
Paul Walmsleyb2abb272009-05-12 17:27:10 -0600186 cmp r12, #0x0
Syed Mohammed, Khasimcc26b3b2008-10-09 17:51:41 +0300187 bne wait_dll_unlock
188 bx lr
189configure_sdrc:
Paul Walmsleyb2abb272009-05-12 17:27:10 -0600190 ldr r11, omap3_sdrc_rfr_ctrl
191 str r0, [r11]
192 ldr r11, omap3_sdrc_actim_ctrla
193 str r1, [r11]
194 ldr r11, omap3_sdrc_actim_ctrlb
195 str r2, [r11]
Paul Walmsleyd0ba3922009-06-19 19:08:27 -0600196 ldr r11, omap3_sdrc_mr_0
197 str r6, [r11]
198 ldr r6, [r11] @ posted-write barrier for SDRC
Syed Mohammed, Khasimcc26b3b2008-10-09 17:51:41 +0300199 bx lr
200
201omap3_sdrc_power:
202 .word OMAP34XX_SDRC_REGADDR(SDRC_POWER)
203omap3_cm_clksel1_pll:
204 .word OMAP34XX_CM_REGADDR(PLL_MOD, CM_CLKSEL1)
205omap3_cm_idlest1_core:
206 .word OMAP34XX_CM_REGADDR(CORE_MOD, CM_IDLEST)
207omap3_cm_iclken1_core:
208 .word OMAP34XX_CM_REGADDR(CORE_MOD, CM_ICLKEN1)
209omap3_sdrc_rfr_ctrl:
210 .word OMAP34XX_SDRC_REGADDR(SDRC_RFR_CTRL_0)
211omap3_sdrc_actim_ctrla:
212 .word OMAP34XX_SDRC_REGADDR(SDRC_ACTIM_CTRL_A_0)
213omap3_sdrc_actim_ctrlb:
214 .word OMAP34XX_SDRC_REGADDR(SDRC_ACTIM_CTRL_B_0)
Paul Walmsleyd0ba3922009-06-19 19:08:27 -0600215omap3_sdrc_mr_0:
216 .word OMAP34XX_SDRC_REGADDR(SDRC_MR_0)
Syed Mohammed, Khasimcc26b3b2008-10-09 17:51:41 +0300217omap3_sdrc_dlla_status:
218 .word OMAP34XX_SDRC_REGADDR(SDRC_DLLA_STATUS)
219omap3_sdrc_dlla_ctrl:
220 .word OMAP34XX_SDRC_REGADDR(SDRC_DLLA_CTRL)
221core_m2_mask_val:
222 .word 0x07FFFFFF
223
224ENTRY(omap3_sram_configure_core_dpll_sz)
225 .word . - omap3_sram_configure_core_dpll