Syed Mohammed, Khasim | cc26b3b | 2008-10-09 17:51:41 +0300 | [diff] [blame] | 1 | /* |
| 2 | * linux/arch/arm/mach-omap3/sram.S |
| 3 | * |
| 4 | * Omap3 specific functions that need to be run in internal SRAM |
| 5 | * |
Paul Walmsley | 4267b5d | 2009-06-19 19:08:27 -0600 | [diff] [blame] | 6 | * Copyright (C) 2004, 2007, 2008 Texas Instruments, Inc. |
| 7 | * Copyright (C) 2008 Nokia Corporation |
Syed Mohammed, Khasim | cc26b3b | 2008-10-09 17:51:41 +0300 | [diff] [blame] | 8 | * |
Paul Walmsley | 4267b5d | 2009-06-19 19:08:27 -0600 | [diff] [blame] | 9 | * Rajendra Nayak <rnayak@ti.com> |
Syed Mohammed, Khasim | cc26b3b | 2008-10-09 17:51:41 +0300 | [diff] [blame] | 10 | * Richard Woodruff <r-woodruff2@ti.com> |
Paul Walmsley | 4267b5d | 2009-06-19 19:08:27 -0600 | [diff] [blame] | 11 | * Paul Walmsley |
Syed Mohammed, Khasim | cc26b3b | 2008-10-09 17:51:41 +0300 | [diff] [blame] | 12 | * |
| 13 | * This program is free software; you can redistribute it and/or |
| 14 | * modify it under the terms of the GNU General Public License as |
| 15 | * published by the Free Software Foundation; either version 2 of |
| 16 | * the License, or (at your option) any later version. |
| 17 | * |
| 18 | * This program is distributed in the hope that it will be useful, |
| 19 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 20 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR /PURPOSE. See the |
| 21 | * GNU General Public License for more details. |
| 22 | * |
| 23 | * You should have received a copy of the GNU General Public License |
| 24 | * along with this program; if not, write to the Free Software |
| 25 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
| 26 | * MA 02111-1307 USA |
| 27 | */ |
| 28 | #include <linux/linkage.h> |
| 29 | #include <asm/assembler.h> |
| 30 | #include <mach/hardware.h> |
| 31 | |
| 32 | #include <mach/io.h> |
| 33 | |
| 34 | #include "sdrc.h" |
| 35 | #include "cm.h" |
| 36 | |
| 37 | .text |
| 38 | |
Paul Walmsley | df14e47 | 2009-06-19 19:08:28 -0600 | [diff] [blame] | 39 | /* r4 parameters */ |
| 40 | #define SDRC_NO_UNLOCK_DLL 0x0 |
| 41 | #define SDRC_UNLOCK_DLL 0x1 |
| 42 | |
| 43 | /* SDRC_DLLA_CTRL bit settings */ |
Paul Walmsley | 7b7bcef | 2009-06-19 19:08:29 -0600 | [diff] [blame^] | 44 | #define FIXEDDELAY_SHIFT 24 |
| 45 | #define FIXEDDELAY_MASK (0xff << FIXEDDELAY_SHIFT) |
Paul Walmsley | df14e47 | 2009-06-19 19:08:28 -0600 | [diff] [blame] | 46 | #define DLLIDLE_MASK 0x4 |
| 47 | |
Paul Walmsley | 7b7bcef | 2009-06-19 19:08:29 -0600 | [diff] [blame^] | 48 | /* |
| 49 | * SDRC_DLLA_CTRL default values: TI hardware team indicates that |
| 50 | * FIXEDDELAY should be initialized to 0xf. This apparently was |
| 51 | * empirically determined during process testing, so no derivation |
| 52 | * was provided. |
| 53 | */ |
| 54 | #define FIXEDDELAY_DEFAULT (0x0f << FIXEDDELAY_SHIFT) |
| 55 | |
Paul Walmsley | df14e47 | 2009-06-19 19:08:28 -0600 | [diff] [blame] | 56 | /* SDRC_DLLA_STATUS bit settings */ |
| 57 | #define LOCKSTATUS_MASK 0x4 |
| 58 | |
| 59 | /* SDRC_POWER bit settings */ |
| 60 | #define SRFRONIDLEREQ_MASK 0x40 |
| 61 | #define PWDENA_MASK 0x4 |
| 62 | |
| 63 | /* CM_IDLEST1_CORE bit settings */ |
| 64 | #define ST_SDRC_MASK 0x2 |
| 65 | |
| 66 | /* CM_ICLKEN1_CORE bit settings */ |
| 67 | #define EN_SDRC_MASK 0x2 |
| 68 | |
| 69 | /* CM_CLKSEL1_PLL bit settings */ |
| 70 | #define CORE_DPLL_CLKOUT_DIV_SHIFT 0x1b |
| 71 | |
Syed Mohammed, Khasim | cc26b3b | 2008-10-09 17:51:41 +0300 | [diff] [blame] | 72 | /* |
Paul Walmsley | 4267b5d | 2009-06-19 19:08:27 -0600 | [diff] [blame] | 73 | * omap3_sram_configure_core_dpll - change DPLL3 M2 divider |
| 74 | * r0 = new SDRC_RFR_CTRL register contents |
| 75 | * r1 = new SDRC_ACTIM_CTRLA register contents |
| 76 | * r2 = new SDRC_ACTIM_CTRLB register contents |
| 77 | * r3 = new M2 divider setting (only 1 and 2 supported right now) |
| 78 | * r4 = unlock SDRC DLL? (1 = yes, 0 = no). Only unlock DLL for |
Paul Walmsley | 4519c2b | 2009-05-12 17:26:32 -0600 | [diff] [blame] | 79 | * SDRC rates < 83MHz |
Paul Walmsley | c9812d0 | 2009-06-19 19:08:26 -0600 | [diff] [blame] | 80 | * r5 = number of MPU cycles to wait for SDRC to stabilize after |
| 81 | * reprogramming the SDRC when switching to a slower MPU speed |
Paul Walmsley | 4267b5d | 2009-06-19 19:08:27 -0600 | [diff] [blame] | 82 | * r6 = new SDRC_MR_0 register value |
Tero Kristo | 3afec63 | 2009-06-19 19:08:29 -0600 | [diff] [blame] | 83 | * r7 = increasing SDRC rate? (1 = yes, 0 = no) |
Paul Walmsley | c9812d0 | 2009-06-19 19:08:26 -0600 | [diff] [blame] | 84 | * |
Syed Mohammed, Khasim | cc26b3b | 2008-10-09 17:51:41 +0300 | [diff] [blame] | 85 | */ |
| 86 | ENTRY(omap3_sram_configure_core_dpll) |
| 87 | stmfd sp!, {r1-r12, lr} @ store regs to stack |
Paul Walmsley | 4519c2b | 2009-05-12 17:26:32 -0600 | [diff] [blame] | 88 | ldr r4, [sp, #52] @ pull extra args off the stack |
Paul Walmsley | c9812d0 | 2009-06-19 19:08:26 -0600 | [diff] [blame] | 89 | ldr r5, [sp, #56] @ load extra args from the stack |
Paul Walmsley | d0ba392 | 2009-06-19 19:08:27 -0600 | [diff] [blame] | 90 | ldr r6, [sp, #60] @ load extra args from the stack |
Tero Kristo | 3afec63 | 2009-06-19 19:08:29 -0600 | [diff] [blame] | 91 | ldr r7, [sp, #64] @ load extra args from the stack |
Paul Walmsley | 69d4255 | 2009-05-12 17:27:09 -0600 | [diff] [blame] | 92 | dsb @ flush buffered writes to interconnect |
Tero Kristo | 3afec63 | 2009-06-19 19:08:29 -0600 | [diff] [blame] | 93 | cmp r7, #1 @ if increasing SDRC clk rate, |
| 94 | bleq configure_sdrc @ program the SDRC regs early (for RFR) |
Paul Walmsley | df14e47 | 2009-06-19 19:08:28 -0600 | [diff] [blame] | 95 | cmp r4, #SDRC_UNLOCK_DLL @ set the intended DLL state |
Paul Walmsley | 4519c2b | 2009-05-12 17:26:32 -0600 | [diff] [blame] | 96 | bleq unlock_dll |
Syed Mohammed, Khasim | cc26b3b | 2008-10-09 17:51:41 +0300 | [diff] [blame] | 97 | blne lock_dll |
Paul Walmsley | 4267b5d | 2009-06-19 19:08:27 -0600 | [diff] [blame] | 98 | bl sdram_in_selfrefresh @ put SDRAM in self refresh, idle SDRC |
| 99 | bl configure_core_dpll @ change the DPLL3 M2 divider |
| 100 | bl enable_sdrc @ take SDRC out of idle |
Paul Walmsley | df14e47 | 2009-06-19 19:08:28 -0600 | [diff] [blame] | 101 | cmp r4, #SDRC_UNLOCK_DLL @ wait for DLL status to change |
Paul Walmsley | 4519c2b | 2009-05-12 17:26:32 -0600 | [diff] [blame] | 102 | bleq wait_dll_unlock |
Syed Mohammed, Khasim | cc26b3b | 2008-10-09 17:51:41 +0300 | [diff] [blame] | 103 | blne wait_dll_lock |
Tero Kristo | 3afec63 | 2009-06-19 19:08:29 -0600 | [diff] [blame] | 104 | cmp r7, #1 @ if increasing SDRC clk rate, |
Paul Walmsley | 4267b5d | 2009-06-19 19:08:27 -0600 | [diff] [blame] | 105 | beq return_to_sdram @ return to SDRAM code, otherwise, |
| 106 | bl configure_sdrc @ reprogram SDRC regs now |
| 107 | mov r12, r5 |
| 108 | bl wait_clk_stable @ wait for SDRC to stabilize |
Paul Walmsley | c9812d0 | 2009-06-19 19:08:26 -0600 | [diff] [blame] | 109 | return_to_sdram: |
Paul Walmsley | 69d4255 | 2009-05-12 17:27:09 -0600 | [diff] [blame] | 110 | isb @ prevent speculative exec past here |
Syed Mohammed, Khasim | cc26b3b | 2008-10-09 17:51:41 +0300 | [diff] [blame] | 111 | mov r0, #0 @ return value |
| 112 | ldmfd sp!, {r1-r12, pc} @ restore regs and return |
| 113 | unlock_dll: |
Paul Walmsley | b2abb27 | 2009-05-12 17:27:10 -0600 | [diff] [blame] | 114 | ldr r11, omap3_sdrc_dlla_ctrl |
| 115 | ldr r12, [r11] |
Paul Walmsley | 7b7bcef | 2009-06-19 19:08:29 -0600 | [diff] [blame^] | 116 | and r12, r12, #FIXEDDELAY_MASK |
| 117 | orr r12, r12, #FIXEDDELAY_DEFAULT |
Paul Walmsley | df14e47 | 2009-06-19 19:08:28 -0600 | [diff] [blame] | 118 | orr r12, r12, #DLLIDLE_MASK |
Paul Walmsley | b2abb27 | 2009-05-12 17:27:10 -0600 | [diff] [blame] | 119 | str r12, [r11] @ (no OCP barrier needed) |
Syed Mohammed, Khasim | cc26b3b | 2008-10-09 17:51:41 +0300 | [diff] [blame] | 120 | bx lr |
| 121 | lock_dll: |
Paul Walmsley | b2abb27 | 2009-05-12 17:27:10 -0600 | [diff] [blame] | 122 | ldr r11, omap3_sdrc_dlla_ctrl |
| 123 | ldr r12, [r11] |
Paul Walmsley | df14e47 | 2009-06-19 19:08:28 -0600 | [diff] [blame] | 124 | bic r12, r12, #DLLIDLE_MASK |
Paul Walmsley | b2abb27 | 2009-05-12 17:27:10 -0600 | [diff] [blame] | 125 | str r12, [r11] @ (no OCP barrier needed) |
Syed Mohammed, Khasim | cc26b3b | 2008-10-09 17:51:41 +0300 | [diff] [blame] | 126 | bx lr |
| 127 | sdram_in_selfrefresh: |
Paul Walmsley | b2abb27 | 2009-05-12 17:27:10 -0600 | [diff] [blame] | 128 | ldr r11, omap3_sdrc_power @ read the SDRC_POWER register |
| 129 | ldr r12, [r11] @ read the contents of SDRC_POWER |
| 130 | mov r9, r12 @ keep a copy of SDRC_POWER bits |
Paul Walmsley | df14e47 | 2009-06-19 19:08:28 -0600 | [diff] [blame] | 131 | orr r12, r12, #SRFRONIDLEREQ_MASK @ enable self refresh on idle |
| 132 | bic r12, r12, #PWDENA_MASK @ clear PWDENA |
Paul Walmsley | b2abb27 | 2009-05-12 17:27:10 -0600 | [diff] [blame] | 133 | str r12, [r11] @ write back to SDRC_POWER register |
| 134 | ldr r12, [r11] @ posted-write barrier for SDRC |
Paul Walmsley | 4267b5d | 2009-06-19 19:08:27 -0600 | [diff] [blame] | 135 | idle_sdrc: |
Paul Walmsley | b2abb27 | 2009-05-12 17:27:10 -0600 | [diff] [blame] | 136 | ldr r11, omap3_cm_iclken1_core @ read the CM_ICLKEN1_CORE reg |
| 137 | ldr r12, [r11] |
Paul Walmsley | df14e47 | 2009-06-19 19:08:28 -0600 | [diff] [blame] | 138 | bic r12, r12, #EN_SDRC_MASK @ disable iclk bit for SDRC |
Paul Walmsley | b2abb27 | 2009-05-12 17:27:10 -0600 | [diff] [blame] | 139 | str r12, [r11] |
Syed Mohammed, Khasim | cc26b3b | 2008-10-09 17:51:41 +0300 | [diff] [blame] | 140 | wait_sdrc_idle: |
Paul Walmsley | b2abb27 | 2009-05-12 17:27:10 -0600 | [diff] [blame] | 141 | ldr r11, omap3_cm_idlest1_core |
| 142 | ldr r12, [r11] |
Paul Walmsley | df14e47 | 2009-06-19 19:08:28 -0600 | [diff] [blame] | 143 | and r12, r12, #ST_SDRC_MASK @ check for SDRC idle |
| 144 | cmp r12, #ST_SDRC_MASK |
Syed Mohammed, Khasim | cc26b3b | 2008-10-09 17:51:41 +0300 | [diff] [blame] | 145 | bne wait_sdrc_idle |
| 146 | bx lr |
| 147 | configure_core_dpll: |
Paul Walmsley | b2abb27 | 2009-05-12 17:27:10 -0600 | [diff] [blame] | 148 | ldr r11, omap3_cm_clksel1_pll |
| 149 | ldr r12, [r11] |
| 150 | ldr r10, core_m2_mask_val @ modify m2 for core dpll |
| 151 | and r12, r12, r10 |
Paul Walmsley | df14e47 | 2009-06-19 19:08:28 -0600 | [diff] [blame] | 152 | orr r12, r12, r3, lsl #CORE_DPLL_CLKOUT_DIV_SHIFT |
Paul Walmsley | b2abb27 | 2009-05-12 17:27:10 -0600 | [diff] [blame] | 153 | str r12, [r11] |
| 154 | ldr r12, [r11] @ posted-write barrier for CM |
Syed Mohammed, Khasim | cc26b3b | 2008-10-09 17:51:41 +0300 | [diff] [blame] | 155 | bx lr |
| 156 | wait_clk_stable: |
Paul Walmsley | b2abb27 | 2009-05-12 17:27:10 -0600 | [diff] [blame] | 157 | subs r12, r12, #1 |
Syed Mohammed, Khasim | cc26b3b | 2008-10-09 17:51:41 +0300 | [diff] [blame] | 158 | bne wait_clk_stable |
Syed Mohammed, Khasim | cc26b3b | 2008-10-09 17:51:41 +0300 | [diff] [blame] | 159 | bx lr |
| 160 | enable_sdrc: |
Paul Walmsley | b2abb27 | 2009-05-12 17:27:10 -0600 | [diff] [blame] | 161 | ldr r11, omap3_cm_iclken1_core |
| 162 | ldr r12, [r11] |
Paul Walmsley | df14e47 | 2009-06-19 19:08:28 -0600 | [diff] [blame] | 163 | orr r12, r12, #EN_SDRC_MASK @ enable iclk bit for SDRC |
Paul Walmsley | b2abb27 | 2009-05-12 17:27:10 -0600 | [diff] [blame] | 164 | str r12, [r11] |
Syed Mohammed, Khasim | cc26b3b | 2008-10-09 17:51:41 +0300 | [diff] [blame] | 165 | wait_sdrc_idle1: |
Paul Walmsley | b2abb27 | 2009-05-12 17:27:10 -0600 | [diff] [blame] | 166 | ldr r11, omap3_cm_idlest1_core |
| 167 | ldr r12, [r11] |
Paul Walmsley | df14e47 | 2009-06-19 19:08:28 -0600 | [diff] [blame] | 168 | and r12, r12, #ST_SDRC_MASK |
Paul Walmsley | b2abb27 | 2009-05-12 17:27:10 -0600 | [diff] [blame] | 169 | cmp r12, #0 |
Syed Mohammed, Khasim | cc26b3b | 2008-10-09 17:51:41 +0300 | [diff] [blame] | 170 | bne wait_sdrc_idle1 |
Paul Walmsley | fa0406a | 2009-05-12 17:27:09 -0600 | [diff] [blame] | 171 | restore_sdrc_power_val: |
Paul Walmsley | b2abb27 | 2009-05-12 17:27:10 -0600 | [diff] [blame] | 172 | ldr r11, omap3_sdrc_power |
| 173 | str r9, [r11] @ restore SDRC_POWER, no barrier needed |
Syed Mohammed, Khasim | cc26b3b | 2008-10-09 17:51:41 +0300 | [diff] [blame] | 174 | bx lr |
| 175 | wait_dll_lock: |
Paul Walmsley | b2abb27 | 2009-05-12 17:27:10 -0600 | [diff] [blame] | 176 | ldr r11, omap3_sdrc_dlla_status |
| 177 | ldr r12, [r11] |
Paul Walmsley | df14e47 | 2009-06-19 19:08:28 -0600 | [diff] [blame] | 178 | and r12, r12, #LOCKSTATUS_MASK |
| 179 | cmp r12, #LOCKSTATUS_MASK |
Syed Mohammed, Khasim | cc26b3b | 2008-10-09 17:51:41 +0300 | [diff] [blame] | 180 | bne wait_dll_lock |
| 181 | bx lr |
| 182 | wait_dll_unlock: |
Paul Walmsley | b2abb27 | 2009-05-12 17:27:10 -0600 | [diff] [blame] | 183 | ldr r11, omap3_sdrc_dlla_status |
| 184 | ldr r12, [r11] |
Paul Walmsley | df14e47 | 2009-06-19 19:08:28 -0600 | [diff] [blame] | 185 | and r12, r12, #LOCKSTATUS_MASK |
Paul Walmsley | b2abb27 | 2009-05-12 17:27:10 -0600 | [diff] [blame] | 186 | cmp r12, #0x0 |
Syed Mohammed, Khasim | cc26b3b | 2008-10-09 17:51:41 +0300 | [diff] [blame] | 187 | bne wait_dll_unlock |
| 188 | bx lr |
| 189 | configure_sdrc: |
Paul Walmsley | b2abb27 | 2009-05-12 17:27:10 -0600 | [diff] [blame] | 190 | ldr r11, omap3_sdrc_rfr_ctrl |
| 191 | str r0, [r11] |
| 192 | ldr r11, omap3_sdrc_actim_ctrla |
| 193 | str r1, [r11] |
| 194 | ldr r11, omap3_sdrc_actim_ctrlb |
| 195 | str r2, [r11] |
Paul Walmsley | d0ba392 | 2009-06-19 19:08:27 -0600 | [diff] [blame] | 196 | ldr r11, omap3_sdrc_mr_0 |
| 197 | str r6, [r11] |
| 198 | ldr r6, [r11] @ posted-write barrier for SDRC |
Syed Mohammed, Khasim | cc26b3b | 2008-10-09 17:51:41 +0300 | [diff] [blame] | 199 | bx lr |
| 200 | |
| 201 | omap3_sdrc_power: |
| 202 | .word OMAP34XX_SDRC_REGADDR(SDRC_POWER) |
| 203 | omap3_cm_clksel1_pll: |
| 204 | .word OMAP34XX_CM_REGADDR(PLL_MOD, CM_CLKSEL1) |
| 205 | omap3_cm_idlest1_core: |
| 206 | .word OMAP34XX_CM_REGADDR(CORE_MOD, CM_IDLEST) |
| 207 | omap3_cm_iclken1_core: |
| 208 | .word OMAP34XX_CM_REGADDR(CORE_MOD, CM_ICLKEN1) |
| 209 | omap3_sdrc_rfr_ctrl: |
| 210 | .word OMAP34XX_SDRC_REGADDR(SDRC_RFR_CTRL_0) |
| 211 | omap3_sdrc_actim_ctrla: |
| 212 | .word OMAP34XX_SDRC_REGADDR(SDRC_ACTIM_CTRL_A_0) |
| 213 | omap3_sdrc_actim_ctrlb: |
| 214 | .word OMAP34XX_SDRC_REGADDR(SDRC_ACTIM_CTRL_B_0) |
Paul Walmsley | d0ba392 | 2009-06-19 19:08:27 -0600 | [diff] [blame] | 215 | omap3_sdrc_mr_0: |
| 216 | .word OMAP34XX_SDRC_REGADDR(SDRC_MR_0) |
Syed Mohammed, Khasim | cc26b3b | 2008-10-09 17:51:41 +0300 | [diff] [blame] | 217 | omap3_sdrc_dlla_status: |
| 218 | .word OMAP34XX_SDRC_REGADDR(SDRC_DLLA_STATUS) |
| 219 | omap3_sdrc_dlla_ctrl: |
| 220 | .word OMAP34XX_SDRC_REGADDR(SDRC_DLLA_CTRL) |
| 221 | core_m2_mask_val: |
| 222 | .word 0x07FFFFFF |
| 223 | |
| 224 | ENTRY(omap3_sram_configure_core_dpll_sz) |
| 225 | .word . - omap3_sram_configure_core_dpll |