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Paolo Ciarrocchi8b45b722008-02-19 23:43:25 +01001/*
Linus Torvalds1da177e2005-04-16 15:20:36 -07002 * @file op_model_ppro.h
Andi Kleenb9917022008-08-18 14:50:31 +02003 * Family 6 perfmon and architectural perfmon MSR operations
Linus Torvalds1da177e2005-04-16 15:20:36 -07004 *
5 * @remark Copyright 2002 OProfile authors
Andi Kleenb9917022008-08-18 14:50:31 +02006 * @remark Copyright 2008 Intel Corporation
Linus Torvalds1da177e2005-04-16 15:20:36 -07007 * @remark Read the file COPYING
8 *
9 * @author John Levon
10 * @author Philippe Elie
11 * @author Graydon Hoare
Andi Kleenb9917022008-08-18 14:50:31 +020012 * @author Andi Kleen
Linus Torvalds1da177e2005-04-16 15:20:36 -070013 */
14
15#include <linux/oprofile.h>
Andi Kleenb9917022008-08-18 14:50:31 +020016#include <linux/slab.h>
Linus Torvalds1da177e2005-04-16 15:20:36 -070017#include <asm/ptrace.h>
18#include <asm/msr.h>
19#include <asm/apic.h>
Don Zickus3e4ff112006-06-26 13:57:01 +020020#include <asm/nmi.h>
Andi Kleenb9917022008-08-18 14:50:31 +020021#include <asm/intel_arch_perfmon.h>
Paolo Ciarrocchi8b45b722008-02-19 23:43:25 +010022
Linus Torvalds1da177e2005-04-16 15:20:36 -070023#include "op_x86_model.h"
24#include "op_counter.h"
25
Andi Kleenb9917022008-08-18 14:50:31 +020026static int num_counters = 2;
27static int counter_width = 32;
Linus Torvalds1da177e2005-04-16 15:20:36 -070028
Paolo Ciarrocchi8b45b722008-02-19 23:43:25 +010029#define CTR_IS_RESERVED(msrs, c) (msrs->counters[(c)].addr ? 1 : 0)
Andi Kleen7c64ade2008-11-07 14:02:49 +010030#define CTR_OVERFLOWED(n) (!((n) & (1ULL<<(counter_width-1))))
Linus Torvalds1da177e2005-04-16 15:20:36 -070031
Paolo Ciarrocchi8b45b722008-02-19 23:43:25 +010032#define CTRL_IS_RESERVED(msrs, c) (msrs->controls[(c)].addr ? 1 : 0)
33#define CTRL_READ(l, h, msrs, c) do {rdmsr((msrs->controls[(c)].addr), (l), (h)); } while (0)
34#define CTRL_WRITE(l, h, msrs, c) do {wrmsr((msrs->controls[(c)].addr), (l), (h)); } while (0)
Linus Torvalds1da177e2005-04-16 15:20:36 -070035#define CTRL_SET_ACTIVE(n) (n |= (1<<22))
36#define CTRL_SET_INACTIVE(n) (n &= ~(1<<22))
37#define CTRL_CLEAR(x) (x &= (1<<21))
38#define CTRL_SET_ENABLE(val) (val |= 1<<20)
Paolo Ciarrocchi8b45b722008-02-19 23:43:25 +010039#define CTRL_SET_USR(val, u) (val |= ((u & 1) << 16))
40#define CTRL_SET_KERN(val, k) (val |= ((k & 1) << 17))
Linus Torvalds1da177e2005-04-16 15:20:36 -070041#define CTRL_SET_UM(val, m) (val |= (m << 8))
42#define CTRL_SET_EVENT(val, e) (val |= e)
43
Andi Kleenb9917022008-08-18 14:50:31 +020044static u64 *reset_value;
Paolo Ciarrocchi8b45b722008-02-19 23:43:25 +010045
Linus Torvalds1da177e2005-04-16 15:20:36 -070046static void ppro_fill_in_addresses(struct op_msrs * const msrs)
47{
Don Zickuscb9c4482006-09-26 10:52:26 +020048 int i;
49
Andi Kleenb9917022008-08-18 14:50:31 +020050 for (i = 0; i < num_counters; i++) {
Don Zickuscb9c4482006-09-26 10:52:26 +020051 if (reserve_perfctr_nmi(MSR_P6_PERFCTR0 + i))
52 msrs->counters[i].addr = MSR_P6_PERFCTR0 + i;
53 else
54 msrs->counters[i].addr = 0;
55 }
Paolo Ciarrocchi8b45b722008-02-19 23:43:25 +010056
Andi Kleenb9917022008-08-18 14:50:31 +020057 for (i = 0; i < num_counters; i++) {
Don Zickuscb9c4482006-09-26 10:52:26 +020058 if (reserve_evntsel_nmi(MSR_P6_EVNTSEL0 + i))
59 msrs->controls[i].addr = MSR_P6_EVNTSEL0 + i;
60 else
61 msrs->controls[i].addr = 0;
62 }
Linus Torvalds1da177e2005-04-16 15:20:36 -070063}
64
65
66static void ppro_setup_ctrs(struct op_msrs const * const msrs)
67{
68 unsigned int low, high;
69 int i;
70
Andi Kleenb9917022008-08-18 14:50:31 +020071 if (!reset_value) {
72 reset_value = kmalloc(sizeof(unsigned) * num_counters,
73 GFP_ATOMIC);
74 if (!reset_value)
75 return;
76 }
77
78 if (cpu_has_arch_perfmon) {
79 union cpuid10_eax eax;
80 eax.full = cpuid_eax(0xa);
81 if (counter_width < eax.split.bit_width)
82 counter_width = eax.split.bit_width;
83 }
84
Linus Torvalds1da177e2005-04-16 15:20:36 -070085 /* clear all counters */
Andi Kleenb9917022008-08-18 14:50:31 +020086 for (i = 0 ; i < num_counters; ++i) {
Paolo Ciarrocchi8b45b722008-02-19 23:43:25 +010087 if (unlikely(!CTRL_IS_RESERVED(msrs, i)))
Don Zickuscb9c4482006-09-26 10:52:26 +020088 continue;
Linus Torvalds1da177e2005-04-16 15:20:36 -070089 CTRL_READ(low, high, msrs, i);
90 CTRL_CLEAR(low);
91 CTRL_WRITE(low, high, msrs, i);
92 }
Paolo Ciarrocchi8b45b722008-02-19 23:43:25 +010093
Linus Torvalds1da177e2005-04-16 15:20:36 -070094 /* avoid a false detection of ctr overflows in NMI handler */
Andi Kleenb9917022008-08-18 14:50:31 +020095 for (i = 0; i < num_counters; ++i) {
Paolo Ciarrocchi8b45b722008-02-19 23:43:25 +010096 if (unlikely(!CTR_IS_RESERVED(msrs, i)))
Don Zickuscb9c4482006-09-26 10:52:26 +020097 continue;
Andi Kleenb9917022008-08-18 14:50:31 +020098 wrmsrl(msrs->counters[i].addr, -1LL);
Linus Torvalds1da177e2005-04-16 15:20:36 -070099 }
100
101 /* enable active counters */
Andi Kleenb9917022008-08-18 14:50:31 +0200102 for (i = 0; i < num_counters; ++i) {
Paolo Ciarrocchi8b45b722008-02-19 23:43:25 +0100103 if ((counter_config[i].enabled) && (CTR_IS_RESERVED(msrs, i))) {
Linus Torvalds1da177e2005-04-16 15:20:36 -0700104 reset_value[i] = counter_config[i].count;
105
Andi Kleenb9917022008-08-18 14:50:31 +0200106 wrmsrl(msrs->counters[i].addr, -reset_value[i]);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700107
108 CTRL_READ(low, high, msrs, i);
109 CTRL_CLEAR(low);
110 CTRL_SET_ENABLE(low);
111 CTRL_SET_USR(low, counter_config[i].user);
112 CTRL_SET_KERN(low, counter_config[i].kernel);
113 CTRL_SET_UM(low, counter_config[i].unit_mask);
114 CTRL_SET_EVENT(low, counter_config[i].event);
115 CTRL_WRITE(low, high, msrs, i);
Don Zickuscb9c4482006-09-26 10:52:26 +0200116 } else {
117 reset_value[i] = 0;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700118 }
119 }
120}
121
Paolo Ciarrocchi8b45b722008-02-19 23:43:25 +0100122
Linus Torvalds1da177e2005-04-16 15:20:36 -0700123static int ppro_check_ctrs(struct pt_regs * const regs,
124 struct op_msrs const * const msrs)
125{
Andi Kleen7c64ade2008-11-07 14:02:49 +0100126 u64 val;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700127 int i;
Paolo Ciarrocchi8b45b722008-02-19 23:43:25 +0100128
Andi Kleenb9917022008-08-18 14:50:31 +0200129 for (i = 0 ; i < num_counters; ++i) {
Don Zickuscb9c4482006-09-26 10:52:26 +0200130 if (!reset_value[i])
131 continue;
Andi Kleen7c64ade2008-11-07 14:02:49 +0100132 rdmsrl(msrs->counters[i].addr, val);
133 if (CTR_OVERFLOWED(val)) {
Linus Torvalds1da177e2005-04-16 15:20:36 -0700134 oprofile_add_sample(regs, i);
Andi Kleenb9917022008-08-18 14:50:31 +0200135 wrmsrl(msrs->counters[i].addr, -reset_value[i]);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700136 }
137 }
138
139 /* Only P6 based Pentium M need to re-unmask the apic vector but it
140 * doesn't hurt other P6 variant */
141 apic_write(APIC_LVTPC, apic_read(APIC_LVTPC) & ~APIC_LVT_MASKED);
142
143 /* We can't work out if we really handled an interrupt. We
144 * might have caught a *second* counter just after overflowing
145 * the interrupt for this counter then arrives
146 * and we don't find a counter that's overflowed, so we
147 * would return 0 and get dazed + confused. Instead we always
148 * assume we found an overflow. This sucks.
149 */
150 return 1;
151}
152
Paolo Ciarrocchi8b45b722008-02-19 23:43:25 +0100153
Linus Torvalds1da177e2005-04-16 15:20:36 -0700154static void ppro_start(struct op_msrs const * const msrs)
155{
Paolo Ciarrocchi8b45b722008-02-19 23:43:25 +0100156 unsigned int low, high;
Arun Sharma6b77df02006-09-29 02:00:01 -0700157 int i;
Don Zickuscb9c4482006-09-26 10:52:26 +0200158
Andi Kleenb9917022008-08-18 14:50:31 +0200159 for (i = 0; i < num_counters; ++i) {
Arun Sharma6b77df02006-09-29 02:00:01 -0700160 if (reset_value[i]) {
161 CTRL_READ(low, high, msrs, i);
162 CTRL_SET_ACTIVE(low);
163 CTRL_WRITE(low, high, msrs, i);
164 }
Don Zickuscb9c4482006-09-26 10:52:26 +0200165 }
Linus Torvalds1da177e2005-04-16 15:20:36 -0700166}
167
168
169static void ppro_stop(struct op_msrs const * const msrs)
170{
Paolo Ciarrocchi8b45b722008-02-19 23:43:25 +0100171 unsigned int low, high;
Arun Sharma6b77df02006-09-29 02:00:01 -0700172 int i;
Don Zickuscb9c4482006-09-26 10:52:26 +0200173
Andi Kleenb9917022008-08-18 14:50:31 +0200174 for (i = 0; i < num_counters; ++i) {
Arun Sharma6b77df02006-09-29 02:00:01 -0700175 if (!reset_value[i])
176 continue;
177 CTRL_READ(low, high, msrs, i);
Don Zickuscb9c4482006-09-26 10:52:26 +0200178 CTRL_SET_INACTIVE(low);
Arun Sharma6b77df02006-09-29 02:00:01 -0700179 CTRL_WRITE(low, high, msrs, i);
Don Zickuscb9c4482006-09-26 10:52:26 +0200180 }
181}
182
183static void ppro_shutdown(struct op_msrs const * const msrs)
184{
185 int i;
186
Andi Kleenb9917022008-08-18 14:50:31 +0200187 for (i = 0 ; i < num_counters ; ++i) {
Paolo Ciarrocchi8b45b722008-02-19 23:43:25 +0100188 if (CTR_IS_RESERVED(msrs, i))
Don Zickuscb9c4482006-09-26 10:52:26 +0200189 release_perfctr_nmi(MSR_P6_PERFCTR0 + i);
190 }
Andi Kleenb9917022008-08-18 14:50:31 +0200191 for (i = 0 ; i < num_counters ; ++i) {
Paolo Ciarrocchi8b45b722008-02-19 23:43:25 +0100192 if (CTRL_IS_RESERVED(msrs, i))
Don Zickuscb9c4482006-09-26 10:52:26 +0200193 release_evntsel_nmi(MSR_P6_EVNTSEL0 + i);
194 }
Andi Kleenb9917022008-08-18 14:50:31 +0200195 if (reset_value) {
196 kfree(reset_value);
197 reset_value = NULL;
198 }
Linus Torvalds1da177e2005-04-16 15:20:36 -0700199}
200
201
Andi Kleen59512902008-09-29 22:23:33 +0200202struct op_x86_model_spec op_ppro_spec = {
Robert Richter5a289392008-10-15 22:19:41 +0200203 .num_counters = 2, /* can be overriden */
204 .num_controls = 2, /* dito */
Robert Richterc92960f2008-09-05 17:12:36 +0200205 .fill_in_addresses = &ppro_fill_in_addresses,
206 .setup_ctrs = &ppro_setup_ctrs,
207 .check_ctrs = &ppro_check_ctrs,
208 .start = &ppro_start,
209 .stop = &ppro_stop,
210 .shutdown = &ppro_shutdown
Linus Torvalds1da177e2005-04-16 15:20:36 -0700211};
Andi Kleenb9917022008-08-18 14:50:31 +0200212
213/*
214 * Architectural performance monitoring.
215 *
216 * Newer Intel CPUs (Core1+) have support for architectural
217 * events described in CPUID 0xA. See the IA32 SDM Vol3b.18 for details.
218 * The advantage of this is that it can be done without knowing about
219 * the specific CPU.
220 */
221
222void arch_perfmon_setup_counters(void)
223{
224 union cpuid10_eax eax;
225
226 eax.full = cpuid_eax(0xa);
227
228 /* Workaround for BIOS bugs in 6/15. Taken from perfmon2 */
229 if (eax.split.version_id == 0 && current_cpu_data.x86 == 6 &&
230 current_cpu_data.x86_model == 15) {
231 eax.split.version_id = 2;
232 eax.split.num_counters = 2;
233 eax.split.bit_width = 40;
234 }
235
236 num_counters = eax.split.num_counters;
237
238 op_arch_perfmon_spec.num_counters = num_counters;
239 op_arch_perfmon_spec.num_controls = num_counters;
Andi Kleen59512902008-09-29 22:23:33 +0200240 op_ppro_spec.num_counters = num_counters;
241 op_ppro_spec.num_controls = num_counters;
Andi Kleenb9917022008-08-18 14:50:31 +0200242}
243
244struct op_x86_model_spec op_arch_perfmon_spec = {
245 /* num_counters/num_controls filled in at runtime */
Robert Richter5a289392008-10-15 22:19:41 +0200246 .fill_in_addresses = &ppro_fill_in_addresses,
Andi Kleenb9917022008-08-18 14:50:31 +0200247 /* user space does the cpuid check for available events */
Robert Richter5a289392008-10-15 22:19:41 +0200248 .setup_ctrs = &ppro_setup_ctrs,
249 .check_ctrs = &ppro_check_ctrs,
250 .start = &ppro_start,
251 .stop = &ppro_stop,
252 .shutdown = &ppro_shutdown
Andi Kleenb9917022008-08-18 14:50:31 +0200253};