Sameer Thalappil | f106a68 | 2013-02-16 20:41:11 -0800 | [diff] [blame] | 1 | /* Copyright (c) 2011-2013, The Linux Foundation. All rights reserved. |
Sameer Thalappil | 8d686d4 | 2012-08-24 10:07:31 -0700 | [diff] [blame] | 2 | * |
| 3 | * This program is free software; you can redistribute it and/or modify |
| 4 | * it under the terms of the GNU General Public License version 2 and |
| 5 | * only version 2 as published by the Free Software Foundation. |
| 6 | * |
| 7 | * This program is distributed in the hope that it will be useful, |
| 8 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 9 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 10 | * GNU General Public License for more details. |
| 11 | */ |
| 12 | #include <linux/module.h> |
| 13 | #include <linux/slab.h> |
| 14 | #include <linux/err.h> |
| 15 | #include <linux/io.h> |
| 16 | #include <linux/gpio.h> |
| 17 | #include <linux/delay.h> |
| 18 | #include <linux/regulator/consumer.h> |
| 19 | #include <linux/mfd/pm8xxx/pm8921.h> |
| 20 | #include <linux/mfd/pm8xxx/gpio.h> |
| 21 | #include <linux/wcnss_wlan.h> |
| 22 | #include <linux/semaphore.h> |
| 23 | #include <linux/list.h> |
| 24 | #include <linux/slab.h> |
| 25 | #include <linux/clk.h> |
| 26 | #include <mach/msm_xo.h> |
| 27 | #include <mach/msm_iomap.h> |
| 28 | |
| 29 | |
| 30 | static void __iomem *msm_wcnss_base; |
Sameer Thalappil | 8d686d4 | 2012-08-24 10:07:31 -0700 | [diff] [blame] | 31 | static LIST_HEAD(power_on_lock_list); |
| 32 | static DEFINE_MUTEX(list_lock); |
| 33 | static DEFINE_SEMAPHORE(wcnss_power_on_lock); |
| 34 | |
| 35 | #define MSM_RIVA_PHYS 0x03204000 |
| 36 | #define MSM_PRONTO_PHYS 0xfb21b000 |
| 37 | |
| 38 | #define RIVA_PMU_OFFSET 0x28 |
| 39 | #define PRONTO_PMU_OFFSET 0x1004 |
| 40 | |
Sameer Thalappil | f106a68 | 2013-02-16 20:41:11 -0800 | [diff] [blame] | 41 | #define RIVA_SPARE_OFFSET 0x0b4 |
| 42 | #define PRONTO_SPARE_OFFSET 0x1088 |
| 43 | #define NVBIN_DLND_BIT BIT(25) |
| 44 | |
Sameer Thalappil | 8d686d4 | 2012-08-24 10:07:31 -0700 | [diff] [blame] | 45 | #define WCNSS_PMU_CFG_IRIS_XO_CFG BIT(3) |
| 46 | #define WCNSS_PMU_CFG_IRIS_XO_EN BIT(4) |
| 47 | #define WCNSS_PMU_CFG_GC_BUS_MUX_SEL_TOP BIT(5) |
| 48 | #define WCNSS_PMU_CFG_IRIS_XO_CFG_STS BIT(6) /* 1: in progress, 0: done */ |
| 49 | |
| 50 | #define WCNSS_PMU_CFG_IRIS_XO_MODE 0x6 |
| 51 | #define WCNSS_PMU_CFG_IRIS_XO_MODE_48 (3 << 1) |
| 52 | |
| 53 | #define VREG_NULL_CONFIG 0x0000 |
| 54 | #define VREG_GET_REGULATOR_MASK 0x0001 |
| 55 | #define VREG_SET_VOLTAGE_MASK 0x0002 |
| 56 | #define VREG_OPTIMUM_MODE_MASK 0x0004 |
| 57 | #define VREG_ENABLE_MASK 0x0008 |
| 58 | |
| 59 | struct vregs_info { |
| 60 | const char * const name; |
| 61 | int state; |
| 62 | const int nominal_min; |
| 63 | const int low_power_min; |
| 64 | const int max_voltage; |
| 65 | const int uA_load; |
| 66 | struct regulator *regulator; |
| 67 | }; |
| 68 | |
| 69 | /* IRIS regulators for Riva hardware */ |
| 70 | static struct vregs_info iris_vregs_riva[] = { |
| 71 | {"iris_vddxo", VREG_NULL_CONFIG, 1800000, 0, 1800000, 10000, NULL}, |
| 72 | {"iris_vddrfa", VREG_NULL_CONFIG, 1300000, 0, 1300000, 100000, NULL}, |
| 73 | {"iris_vddpa", VREG_NULL_CONFIG, 2900000, 0, 3000000, 515000, NULL}, |
| 74 | {"iris_vdddig", VREG_NULL_CONFIG, 1200000, 0, 1225000, 10000, NULL}, |
| 75 | }; |
| 76 | |
| 77 | /* WCNSS regulators for Riva hardware */ |
| 78 | static struct vregs_info riva_vregs[] = { |
| 79 | /* Riva */ |
| 80 | {"riva_vddmx", VREG_NULL_CONFIG, 1050000, 0, 1150000, 0, NULL}, |
| 81 | {"riva_vddcx", VREG_NULL_CONFIG, 1050000, 0, 1150000, 0, NULL}, |
| 82 | {"riva_vddpx", VREG_NULL_CONFIG, 1800000, 0, 1800000, 0, NULL}, |
| 83 | }; |
| 84 | |
| 85 | /* IRIS regulators for Pronto hardware */ |
| 86 | static struct vregs_info iris_vregs_pronto[] = { |
| 87 | {"qcom,iris-vddxo", VREG_NULL_CONFIG, 1800000, 0, |
| 88 | 1800000, 10000, NULL}, |
| 89 | {"qcom,iris-vddrfa", VREG_NULL_CONFIG, 1300000, 0, |
| 90 | 1300000, 100000, NULL}, |
| 91 | {"qcom,iris-vddpa", VREG_NULL_CONFIG, 2900000, 0, |
| 92 | 3000000, 515000, NULL}, |
| 93 | {"qcom,iris-vdddig", VREG_NULL_CONFIG, 1225000, 0, |
Sheng Fang | 7575a4c | 2013-03-19 08:13:19 +0800 | [diff] [blame] | 94 | 1300000, 10000, NULL}, |
Sameer Thalappil | 8d686d4 | 2012-08-24 10:07:31 -0700 | [diff] [blame] | 95 | }; |
| 96 | |
| 97 | /* WCNSS regulators for Pronto hardware */ |
| 98 | static struct vregs_info pronto_vregs[] = { |
| 99 | {"qcom,pronto-vddmx", VREG_NULL_CONFIG, 950000, 0, |
| 100 | 1150000, 0, NULL}, |
| 101 | {"qcom,pronto-vddcx", VREG_NULL_CONFIG, 900000, 0, |
| 102 | 1150000, 0, NULL}, |
| 103 | {"qcom,pronto-vddpx", VREG_NULL_CONFIG, 1800000, 0, |
| 104 | 1800000, 0, NULL}, |
| 105 | }; |
| 106 | |
| 107 | |
| 108 | struct host_driver { |
| 109 | char name[20]; |
| 110 | struct list_head list; |
| 111 | }; |
| 112 | |
| 113 | |
| 114 | static int configure_iris_xo(struct device *dev, bool use_48mhz_xo, int on) |
| 115 | { |
| 116 | u32 reg = 0; |
| 117 | int rc = 0; |
| 118 | int size = 0; |
| 119 | int pmu_offset = 0; |
Sameer Thalappil | f106a68 | 2013-02-16 20:41:11 -0800 | [diff] [blame] | 120 | int spare_offset = 0; |
Sameer Thalappil | 8d686d4 | 2012-08-24 10:07:31 -0700 | [diff] [blame] | 121 | unsigned long wcnss_phys_addr; |
| 122 | void __iomem *pmu_conf_reg; |
Sameer Thalappil | f106a68 | 2013-02-16 20:41:11 -0800 | [diff] [blame] | 123 | void __iomem *spare_reg; |
Sameer Thalappil | 8d686d4 | 2012-08-24 10:07:31 -0700 | [diff] [blame] | 124 | struct clk *clk; |
Sheng Fang | bb42167 | 2013-03-19 08:27:28 +0800 | [diff] [blame] | 125 | struct clk *clk_rf = NULL; |
Sameer Thalappil | 8d686d4 | 2012-08-24 10:07:31 -0700 | [diff] [blame] | 126 | |
| 127 | if (wcnss_hardware_type() == WCNSS_PRONTO_HW) { |
| 128 | wcnss_phys_addr = MSM_PRONTO_PHYS; |
| 129 | pmu_offset = PRONTO_PMU_OFFSET; |
Sameer Thalappil | f106a68 | 2013-02-16 20:41:11 -0800 | [diff] [blame] | 130 | spare_offset = PRONTO_SPARE_OFFSET; |
Sameer Thalappil | 8d686d4 | 2012-08-24 10:07:31 -0700 | [diff] [blame] | 131 | size = 0x3000; |
| 132 | |
| 133 | clk = clk_get(dev, "xo"); |
| 134 | if (IS_ERR(clk)) { |
| 135 | pr_err("Couldn't get xo clock\n"); |
| 136 | return PTR_ERR(clk); |
| 137 | } |
Sheng Fang | bb42167 | 2013-03-19 08:27:28 +0800 | [diff] [blame] | 138 | |
| 139 | if (!use_48mhz_xo) { |
| 140 | clk_rf = clk_get(dev, "rf_clk"); |
| 141 | if (IS_ERR(clk_rf)) { |
| 142 | pr_err("Couldn't get rf_clk\n"); |
| 143 | clk_put(clk); |
| 144 | return PTR_ERR(clk_rf); |
| 145 | } |
| 146 | } |
Sameer Thalappil | 8d686d4 | 2012-08-24 10:07:31 -0700 | [diff] [blame] | 147 | } else { |
| 148 | wcnss_phys_addr = MSM_RIVA_PHYS; |
| 149 | pmu_offset = RIVA_PMU_OFFSET; |
Sameer Thalappil | f106a68 | 2013-02-16 20:41:11 -0800 | [diff] [blame] | 150 | spare_offset = RIVA_SPARE_OFFSET; |
Sameer Thalappil | 8d686d4 | 2012-08-24 10:07:31 -0700 | [diff] [blame] | 151 | size = SZ_256; |
| 152 | |
| 153 | clk = clk_get(dev, "cxo"); |
| 154 | if (IS_ERR(clk)) { |
| 155 | pr_err("Couldn't get cxo clock\n"); |
| 156 | return PTR_ERR(clk); |
| 157 | } |
| 158 | } |
| 159 | |
| 160 | if (on) { |
| 161 | msm_wcnss_base = ioremap(wcnss_phys_addr, size); |
| 162 | if (!msm_wcnss_base) { |
| 163 | pr_err("ioremap wcnss physical failed\n"); |
| 164 | goto fail; |
| 165 | } |
Sameer Thalappil | f106a68 | 2013-02-16 20:41:11 -0800 | [diff] [blame] | 166 | |
Sameer Thalappil | e7d58e9 | 2013-03-06 14:45:58 -0800 | [diff] [blame] | 167 | /* Enable IRIS XO */ |
| 168 | rc = clk_prepare_enable(clk); |
| 169 | if (rc) { |
| 170 | pr_err("clk enable failed\n"); |
| 171 | goto fail; |
| 172 | } |
Sheng Fang | bb42167 | 2013-03-19 08:27:28 +0800 | [diff] [blame] | 173 | |
Sameer Thalappil | e7d58e9 | 2013-03-06 14:45:58 -0800 | [diff] [blame] | 174 | /* NV bit is set to indicate that platform driver is capable |
| 175 | * of doing NV download. SSR should not set NV bit; during |
| 176 | * SSR NV bin is downloaded by WLAN driver. |
Sameer Thalappil | cf566bb | 2013-02-26 17:10:25 -0800 | [diff] [blame] | 177 | */ |
| 178 | if (!wcnss_cold_boot_done()) { |
| 179 | pr_debug("wcnss: Indicate NV bin download\n"); |
| 180 | spare_reg = msm_wcnss_base + spare_offset; |
| 181 | reg = readl_relaxed(spare_reg); |
| 182 | reg |= NVBIN_DLND_BIT; |
| 183 | writel_relaxed(reg, spare_reg); |
| 184 | } |
Sameer Thalappil | f106a68 | 2013-02-16 20:41:11 -0800 | [diff] [blame] | 185 | |
Sameer Thalappil | 8d686d4 | 2012-08-24 10:07:31 -0700 | [diff] [blame] | 186 | pmu_conf_reg = msm_wcnss_base + pmu_offset; |
Sameer Thalappil | 8d686d4 | 2012-08-24 10:07:31 -0700 | [diff] [blame] | 187 | writel_relaxed(0, pmu_conf_reg); |
| 188 | reg = readl_relaxed(pmu_conf_reg); |
| 189 | reg |= WCNSS_PMU_CFG_GC_BUS_MUX_SEL_TOP | |
| 190 | WCNSS_PMU_CFG_IRIS_XO_EN; |
| 191 | writel_relaxed(reg, pmu_conf_reg); |
| 192 | |
| 193 | /* Clear XO_MODE[b2:b1] bits. Clear implies 19.2 MHz TCXO */ |
| 194 | reg &= ~(WCNSS_PMU_CFG_IRIS_XO_MODE); |
| 195 | |
| 196 | if (use_48mhz_xo) |
| 197 | reg |= WCNSS_PMU_CFG_IRIS_XO_MODE_48; |
| 198 | |
| 199 | writel_relaxed(reg, pmu_conf_reg); |
| 200 | |
| 201 | /* Start IRIS XO configuration */ |
| 202 | reg |= WCNSS_PMU_CFG_IRIS_XO_CFG; |
| 203 | writel_relaxed(reg, pmu_conf_reg); |
| 204 | |
| 205 | /* Wait for XO configuration to finish */ |
| 206 | while (readl_relaxed(pmu_conf_reg) & |
| 207 | WCNSS_PMU_CFG_IRIS_XO_CFG_STS) |
| 208 | cpu_relax(); |
| 209 | |
| 210 | /* Stop IRIS XO configuration */ |
| 211 | reg &= ~(WCNSS_PMU_CFG_GC_BUS_MUX_SEL_TOP | |
| 212 | WCNSS_PMU_CFG_IRIS_XO_CFG); |
| 213 | writel_relaxed(reg, pmu_conf_reg); |
| 214 | clk_disable_unprepare(clk); |
| 215 | |
| 216 | if (!use_48mhz_xo) { |
Sheng Fang | bb42167 | 2013-03-19 08:27:28 +0800 | [diff] [blame] | 217 | rc = clk_prepare_enable(clk_rf); |
| 218 | if (rc) { |
| 219 | pr_err("clk_rf enable failed\n"); |
Sameer Thalappil | 8d686d4 | 2012-08-24 10:07:31 -0700 | [diff] [blame] | 220 | goto fail; |
| 221 | } |
Sameer Thalappil | 8d686d4 | 2012-08-24 10:07:31 -0700 | [diff] [blame] | 222 | } |
Sheng Fang | bb42167 | 2013-03-19 08:27:28 +0800 | [diff] [blame] | 223 | } else if (clk_rf != NULL && !use_48mhz_xo) |
| 224 | clk_disable_unprepare(clk_rf); |
Sameer Thalappil | 8d686d4 | 2012-08-24 10:07:31 -0700 | [diff] [blame] | 225 | /* Add some delay for XO to settle */ |
| 226 | msleep(20); |
| 227 | |
| 228 | clk_put(clk); |
Sheng Fang | bb42167 | 2013-03-19 08:27:28 +0800 | [diff] [blame] | 229 | |
| 230 | if (wcnss_hardware_type() == WCNSS_PRONTO_HW) { |
| 231 | if (!use_48mhz_xo) |
| 232 | clk_put(clk_rf); |
| 233 | } |
| 234 | |
Sameer Thalappil | 8d686d4 | 2012-08-24 10:07:31 -0700 | [diff] [blame] | 235 | return rc; |
Sameer Thalappil | 8d686d4 | 2012-08-24 10:07:31 -0700 | [diff] [blame] | 236 | fail: |
Sheng Fang | bb42167 | 2013-03-19 08:27:28 +0800 | [diff] [blame] | 237 | if (clk_rf != NULL) |
| 238 | clk_put(clk_rf); |
Sameer Thalappil | 8d686d4 | 2012-08-24 10:07:31 -0700 | [diff] [blame] | 239 | clk_put(clk); |
| 240 | return rc; |
| 241 | } |
| 242 | |
| 243 | /* Helper routine to turn off all WCNSS & IRIS vregs */ |
| 244 | static void wcnss_vregs_off(struct vregs_info regulators[], uint size) |
| 245 | { |
| 246 | int i, rc = 0; |
| 247 | |
| 248 | /* Regulators need to be turned off in the reverse order */ |
| 249 | for (i = (size-1); i >= 0; i--) { |
| 250 | if (regulators[i].state == VREG_NULL_CONFIG) |
| 251 | continue; |
| 252 | |
| 253 | /* Remove PWM mode */ |
| 254 | if (regulators[i].state & VREG_OPTIMUM_MODE_MASK) { |
| 255 | rc = regulator_set_optimum_mode( |
| 256 | regulators[i].regulator, 0); |
| 257 | if (rc < 0) |
| 258 | pr_err("regulator_set_optimum_mode(%s) failed (%d)\n", |
| 259 | regulators[i].name, rc); |
| 260 | } |
| 261 | |
| 262 | /* Set voltage to lowest level */ |
| 263 | if (regulators[i].state & VREG_SET_VOLTAGE_MASK) { |
| 264 | rc = regulator_set_voltage(regulators[i].regulator, |
| 265 | regulators[i].low_power_min, |
| 266 | regulators[i].max_voltage); |
| 267 | if (rc) |
| 268 | pr_err("regulator_set_voltage(%s) failed (%d)\n", |
| 269 | regulators[i].name, rc); |
| 270 | } |
| 271 | |
| 272 | /* Disable regulator */ |
| 273 | if (regulators[i].state & VREG_ENABLE_MASK) { |
| 274 | rc = regulator_disable(regulators[i].regulator); |
| 275 | if (rc < 0) |
| 276 | pr_err("vreg %s disable failed (%d)\n", |
| 277 | regulators[i].name, rc); |
| 278 | } |
| 279 | |
| 280 | /* Free the regulator source */ |
| 281 | if (regulators[i].state & VREG_GET_REGULATOR_MASK) |
| 282 | regulator_put(regulators[i].regulator); |
| 283 | |
| 284 | regulators[i].state = VREG_NULL_CONFIG; |
| 285 | } |
| 286 | } |
| 287 | |
| 288 | /* Common helper routine to turn on all WCNSS & IRIS vregs */ |
| 289 | static int wcnss_vregs_on(struct device *dev, |
| 290 | struct vregs_info regulators[], uint size) |
| 291 | { |
| 292 | int i, rc = 0, reg_cnt; |
| 293 | |
| 294 | for (i = 0; i < size; i++) { |
| 295 | /* Get regulator source */ |
| 296 | regulators[i].regulator = |
| 297 | regulator_get(dev, regulators[i].name); |
| 298 | if (IS_ERR(regulators[i].regulator)) { |
| 299 | rc = PTR_ERR(regulators[i].regulator); |
| 300 | pr_err("regulator get of %s failed (%d)\n", |
| 301 | regulators[i].name, rc); |
| 302 | goto fail; |
| 303 | } |
| 304 | regulators[i].state |= VREG_GET_REGULATOR_MASK; |
| 305 | reg_cnt = regulator_count_voltages(regulators[i].regulator); |
| 306 | /* Set voltage to nominal. Exclude swtiches e.g. LVS */ |
| 307 | if ((regulators[i].nominal_min || regulators[i].max_voltage) |
| 308 | && (reg_cnt > 0)) { |
| 309 | rc = regulator_set_voltage(regulators[i].regulator, |
| 310 | regulators[i].nominal_min, |
| 311 | regulators[i].max_voltage); |
| 312 | if (rc) { |
| 313 | pr_err("regulator_set_voltage(%s) failed (%d)\n", |
| 314 | regulators[i].name, rc); |
| 315 | goto fail; |
| 316 | } |
| 317 | regulators[i].state |= VREG_SET_VOLTAGE_MASK; |
| 318 | } |
| 319 | |
| 320 | /* Vote for PWM/PFM mode if needed */ |
| 321 | if (regulators[i].uA_load && (reg_cnt > 0)) { |
| 322 | rc = regulator_set_optimum_mode(regulators[i].regulator, |
| 323 | regulators[i].uA_load); |
| 324 | if (rc < 0) { |
| 325 | pr_err("regulator_set_optimum_mode(%s) failed (%d)\n", |
| 326 | regulators[i].name, rc); |
| 327 | goto fail; |
| 328 | } |
| 329 | regulators[i].state |= VREG_OPTIMUM_MODE_MASK; |
| 330 | } |
| 331 | |
| 332 | /* Enable the regulator */ |
| 333 | rc = regulator_enable(regulators[i].regulator); |
| 334 | if (rc) { |
| 335 | pr_err("vreg %s enable failed (%d)\n", |
| 336 | regulators[i].name, rc); |
| 337 | goto fail; |
| 338 | } |
| 339 | regulators[i].state |= VREG_ENABLE_MASK; |
| 340 | } |
| 341 | |
| 342 | return rc; |
| 343 | |
| 344 | fail: |
| 345 | wcnss_vregs_off(regulators, size); |
| 346 | return rc; |
| 347 | |
| 348 | } |
| 349 | |
| 350 | static void wcnss_iris_vregs_off(enum wcnss_hw_type hw_type) |
| 351 | { |
| 352 | switch (hw_type) { |
| 353 | case WCNSS_RIVA_HW: |
| 354 | wcnss_vregs_off(iris_vregs_riva, ARRAY_SIZE(iris_vregs_riva)); |
| 355 | break; |
| 356 | case WCNSS_PRONTO_HW: |
| 357 | wcnss_vregs_off(iris_vregs_pronto, |
| 358 | ARRAY_SIZE(iris_vregs_pronto)); |
| 359 | break; |
| 360 | default: |
| 361 | pr_err("%s invalid hardware %d\n", __func__, hw_type); |
| 362 | |
| 363 | } |
| 364 | } |
| 365 | |
| 366 | static int wcnss_iris_vregs_on(struct device *dev, enum wcnss_hw_type hw_type) |
| 367 | { |
| 368 | int ret = -1; |
| 369 | |
| 370 | switch (hw_type) { |
| 371 | case WCNSS_RIVA_HW: |
| 372 | ret = wcnss_vregs_on(dev, iris_vregs_riva, |
| 373 | ARRAY_SIZE(iris_vregs_riva)); |
| 374 | break; |
| 375 | case WCNSS_PRONTO_HW: |
| 376 | ret = wcnss_vregs_on(dev, iris_vregs_pronto, |
| 377 | ARRAY_SIZE(iris_vregs_pronto)); |
| 378 | break; |
| 379 | default: |
| 380 | pr_err("%s invalid hardware %d\n", __func__, hw_type); |
| 381 | } |
| 382 | return ret; |
| 383 | } |
| 384 | |
| 385 | static void wcnss_core_vregs_off(enum wcnss_hw_type hw_type) |
| 386 | { |
| 387 | switch (hw_type) { |
| 388 | case WCNSS_RIVA_HW: |
| 389 | wcnss_vregs_off(riva_vregs, ARRAY_SIZE(riva_vregs)); |
| 390 | break; |
| 391 | case WCNSS_PRONTO_HW: |
| 392 | wcnss_vregs_off(pronto_vregs, ARRAY_SIZE(pronto_vregs)); |
| 393 | break; |
| 394 | default: |
| 395 | pr_err("%s invalid hardware %d\n", __func__, hw_type); |
| 396 | } |
| 397 | |
| 398 | } |
| 399 | |
| 400 | static int wcnss_core_vregs_on(struct device *dev, enum wcnss_hw_type hw_type) |
| 401 | { |
| 402 | int ret = -1; |
| 403 | |
| 404 | switch (hw_type) { |
| 405 | case WCNSS_RIVA_HW: |
| 406 | ret = wcnss_vregs_on(dev, riva_vregs, ARRAY_SIZE(riva_vregs)); |
| 407 | break; |
| 408 | case WCNSS_PRONTO_HW: |
| 409 | ret = wcnss_vregs_on(dev, pronto_vregs, |
| 410 | ARRAY_SIZE(pronto_vregs)); |
| 411 | break; |
| 412 | default: |
| 413 | pr_err("%s invalid hardware %d\n", __func__, hw_type); |
| 414 | } |
| 415 | |
| 416 | return ret; |
| 417 | |
| 418 | } |
| 419 | |
| 420 | int wcnss_wlan_power(struct device *dev, |
| 421 | struct wcnss_wlan_config *cfg, |
| 422 | enum wcnss_opcode on) |
| 423 | { |
| 424 | int rc = 0; |
| 425 | enum wcnss_hw_type hw_type = wcnss_hardware_type(); |
| 426 | |
| 427 | if (on) { |
| 428 | down(&wcnss_power_on_lock); |
| 429 | /* RIVA regulator settings */ |
| 430 | rc = wcnss_core_vregs_on(dev, hw_type); |
| 431 | if (rc) |
| 432 | goto fail_wcnss_on; |
| 433 | |
| 434 | /* IRIS regulator settings */ |
| 435 | rc = wcnss_iris_vregs_on(dev, hw_type); |
| 436 | if (rc) |
| 437 | goto fail_iris_on; |
| 438 | |
| 439 | /* Configure IRIS XO */ |
| 440 | rc = configure_iris_xo(dev, cfg->use_48mhz_xo, |
| 441 | WCNSS_WLAN_SWITCH_ON); |
| 442 | if (rc) |
| 443 | goto fail_iris_xo; |
| 444 | up(&wcnss_power_on_lock); |
| 445 | |
| 446 | } else { |
| 447 | configure_iris_xo(dev, cfg->use_48mhz_xo, |
| 448 | WCNSS_WLAN_SWITCH_OFF); |
| 449 | wcnss_iris_vregs_off(hw_type); |
| 450 | wcnss_core_vregs_off(hw_type); |
| 451 | } |
| 452 | |
| 453 | return rc; |
| 454 | |
| 455 | fail_iris_xo: |
| 456 | wcnss_iris_vregs_off(hw_type); |
| 457 | |
| 458 | fail_iris_on: |
| 459 | wcnss_core_vregs_off(hw_type); |
| 460 | |
| 461 | fail_wcnss_on: |
| 462 | up(&wcnss_power_on_lock); |
| 463 | return rc; |
| 464 | } |
| 465 | EXPORT_SYMBOL(wcnss_wlan_power); |
| 466 | |
| 467 | /* |
| 468 | * During SSR WCNSS should not be 'powered on' until all the host drivers |
| 469 | * finish their shutdown routines. Host drivers use below APIs to |
| 470 | * synchronize power-on. WCNSS will not be 'powered on' until all the |
| 471 | * requests(to lock power-on) are freed. |
| 472 | */ |
| 473 | int wcnss_req_power_on_lock(char *driver_name) |
| 474 | { |
| 475 | struct host_driver *node; |
| 476 | |
| 477 | if (!driver_name) |
| 478 | goto err; |
| 479 | |
| 480 | node = kmalloc(sizeof(struct host_driver), GFP_KERNEL); |
| 481 | if (!node) |
| 482 | goto err; |
| 483 | strlcpy(node->name, driver_name, sizeof(node->name)); |
| 484 | |
| 485 | mutex_lock(&list_lock); |
| 486 | /* Lock when the first request is added */ |
| 487 | if (list_empty(&power_on_lock_list)) |
| 488 | down(&wcnss_power_on_lock); |
| 489 | list_add(&node->list, &power_on_lock_list); |
| 490 | mutex_unlock(&list_lock); |
| 491 | |
| 492 | return 0; |
| 493 | |
| 494 | err: |
| 495 | return -EINVAL; |
| 496 | } |
| 497 | EXPORT_SYMBOL(wcnss_req_power_on_lock); |
| 498 | |
| 499 | int wcnss_free_power_on_lock(char *driver_name) |
| 500 | { |
| 501 | int ret = -1; |
| 502 | struct host_driver *node; |
| 503 | |
| 504 | mutex_lock(&list_lock); |
| 505 | list_for_each_entry(node, &power_on_lock_list, list) { |
| 506 | if (!strncmp(node->name, driver_name, sizeof(node->name))) { |
| 507 | list_del(&node->list); |
| 508 | kfree(node); |
| 509 | ret = 0; |
| 510 | break; |
| 511 | } |
| 512 | } |
| 513 | /* unlock when the last host driver frees the lock */ |
| 514 | if (list_empty(&power_on_lock_list)) |
| 515 | up(&wcnss_power_on_lock); |
| 516 | mutex_unlock(&list_lock); |
| 517 | |
| 518 | return ret; |
| 519 | } |
| 520 | EXPORT_SYMBOL(wcnss_free_power_on_lock); |