blob: 499d67e7ecc6424951e8ebf8d67725241cbd280e [file] [log] [blame]
David Collins88365302012-07-17 09:34:57 -07001/*
2 * Copyright (c) 2011-2012, The Linux Foundation. All rights reserved.
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 and
6 * only version 2 as published by the Free Software Foundation.
7 *
8 * This program is distributed in the hope that it will be useful,
9 * but WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
11 * GNU General Public License for more details.
12 */
13
14#define pr_fmt(fmt) "%s: " fmt, __func__
15
16#include <linux/module.h>
17#include <linux/delay.h>
18#include <linux/err.h>
19#include <linux/string.h>
20#include <linux/interrupt.h>
21#include <linux/kernel.h>
22#include <linux/slab.h>
23#include <linux/spmi.h>
24#include <linux/of.h>
25#include <linux/of_device.h>
26#include <linux/thermal.h>
27#include <linux/qpnp/qpnp-adc.h>
28
29#define QPNP_TM_DRIVER_NAME "qcom,qpnp-temp-alarm"
30
31enum qpnp_tm_registers {
32 QPNP_TM_REG_TYPE = 0x04,
33 QPNP_TM_REG_SUBTYPE = 0x05,
34 QPNP_TM_REG_STATUS = 0x08,
35 QPNP_TM_REG_SHUTDOWN_CTRL1 = 0x40,
36 QPNP_TM_REG_SHUTDOWN_CTRL2 = 0x42,
37 QPNP_TM_REG_ALARM_CTRL = 0x46,
38};
39
40#define QPNP_TM_TYPE 0x09
41#define QPNP_TM_SUBTYPE 0x08
42
43#define STATUS_STAGE_MASK 0x03
44
45#define SHUTDOWN_CTRL1_OVERRIDE_STAGE3 0x80
46#define SHUTDOWN_CTRL1_OVERRIDE_STAGE2 0x40
47#define SHUTDOWN_CTRL1_THRESHOLD_MASK 0x03
48
49#define SHUTDOWN_CTRL2_CLEAR_STAGE3 0x80
50#define SHUTDOWN_CTRL2_CLEAR_STAGE2 0x40
51
52#define ALARM_CTRL_FORCE_ENABLE 0x80
53#define ALARM_CTRL_FOLLOW_HW_ENABLE 0x01
54
55#define TEMP_STAGE_STEP 20000 /* Stage step: 20.000 C */
56#define TEMP_STAGE_HYSTERESIS 2000
57
58#define TEMP_THRESH_MIN 105000 /* Threshold Min: 105 C */
59#define TEMP_THRESH_STEP 5000 /* Threshold step: 5 C */
60
61#define THRESH_MIN 0
62#define THRESH_MAX 3
63
64/* Trip points from most critical to least critical */
65#define TRIP_STAGE3 0
66#define TRIP_STAGE2 1
67#define TRIP_STAGE1 2
68#define TRIP_NUM 3
69
70enum qpnp_tm_adc_type {
71 QPNP_TM_ADC_NONE, /* Estimates temp based on overload level. */
72 QPNP_TM_ADC_QPNP_ADC,
73};
74
75/*
76 * Temperature in millicelcius reported during stage 0 if no ADC is present and
77 * no value has been specified via device tree.
78 */
79#define DEFAULT_NO_ADC_TEMP 37000
80
81struct qpnp_tm_chip {
82 struct delayed_work irq_work;
83 struct spmi_device *spmi_dev;
84 struct thermal_zone_device *tz_dev;
85 const char *tm_name;
86 enum qpnp_tm_adc_type adc_type;
87 unsigned long temperature;
88 enum thermal_device_mode mode;
89 unsigned int thresh;
90 unsigned int stage;
91 unsigned int prev_stage;
92 int irq;
93 enum qpnp_vadc_channels adc_channel;
94 u16 base_addr;
95 bool allow_software_override;
96};
97
98/* Delay between TEMP_STAT IRQ going high and status value changing in ms. */
99#define STATUS_REGISTER_DELAY_MS 40
100
101enum pmic_thermal_override_mode {
102 SOFTWARE_OVERRIDE_DISABLED = 0,
103 SOFTWARE_OVERRIDE_ENABLED,
104};
105
106static inline int qpnp_tm_read(struct qpnp_tm_chip *chip, u16 addr, u8 *buf,
107 int len)
108{
109 int rc;
110
111 rc = spmi_ext_register_readl(chip->spmi_dev->ctrl,
112 chip->spmi_dev->sid, chip->base_addr + addr, buf, len);
113
114 if (rc)
115 dev_err(&chip->spmi_dev->dev, "%s: spmi_ext_register_readl() failed. sid=%d, addr=%04X, len=%d, rc=%d\n",
116 __func__, chip->spmi_dev->sid, chip->base_addr + addr,
117 len, rc);
118
119 return rc;
120}
121
122static inline int qpnp_tm_write(struct qpnp_tm_chip *chip, u16 addr, u8 *buf,
123 int len)
124{
125 int rc;
126
127 rc = spmi_ext_register_writel(chip->spmi_dev->ctrl,
128 chip->spmi_dev->sid, chip->base_addr + addr, buf, len);
129
130 if (rc)
131 dev_err(&chip->spmi_dev->dev, "%s: spmi_ext_register_writel() failed. sid=%d, addr=%04X, len=%d, rc=%d\n",
132 __func__, chip->spmi_dev->sid, chip->base_addr + addr,
133 len, rc);
134
135 return rc;
136}
137
138
139static inline int qpnp_tm_shutdown_override(struct qpnp_tm_chip *chip,
140 enum pmic_thermal_override_mode mode)
141{
142 int rc = 0;
143 u8 reg;
144
145 if (chip->allow_software_override) {
146 reg = chip->thresh & SHUTDOWN_CTRL1_THRESHOLD_MASK;
147
148 if (mode == SOFTWARE_OVERRIDE_ENABLED)
149 reg |= SHUTDOWN_CTRL1_OVERRIDE_STAGE2
150 | SHUTDOWN_CTRL1_OVERRIDE_STAGE3;
151
152 rc = qpnp_tm_write(chip, QPNP_TM_REG_SHUTDOWN_CTRL1, &reg, 1);
153 }
154
155 return rc;
156}
157
158static int qpnp_tm_update_temp(struct qpnp_tm_chip *chip)
159{
160 struct qpnp_vadc_result adc_result;
161 int rc;
162
163 rc = qpnp_vadc_read(chip->adc_channel, &adc_result);
164 if (!rc)
165 chip->temperature = adc_result.physical;
166 else
167 dev_err(&chip->spmi_dev->dev, "%s: qpnp_vadc_read(%d) failed, rc=%d\n",
168 __func__, chip->adc_channel, rc);
169
170 return rc;
171}
172
173/*
174 * This function initializes the internal temperature value based on only the
175 * current thermal stage and threshold.
176 */
177static int qpnp_tm_init_temp_no_adc(struct qpnp_tm_chip *chip)
178{
179 int rc;
180 u8 reg;
181
182 rc = qpnp_tm_read(chip, QPNP_TM_REG_STATUS, &reg, 1);
183 if (rc < 0)
184 return rc;
185
186 chip->stage = reg & STATUS_STAGE_MASK;
187
188 if (chip->stage)
189 chip->temperature = chip->thresh * TEMP_THRESH_STEP +
190 (chip->stage - 1) * TEMP_STAGE_STEP +
191 TEMP_THRESH_MIN;
192
193 return 0;
194}
195
196/*
197 * This function updates the internal temperature value based on the
198 * current thermal stage and threshold as well as the previous stage
199 */
200static int qpnp_tm_update_temp_no_adc(struct qpnp_tm_chip *chip)
201{
202 unsigned int stage;
203 int rc;
204 u8 reg;
205
206 rc = qpnp_tm_read(chip, QPNP_TM_REG_STATUS, &reg, 1);
207 if (rc < 0)
208 return rc;
209
210 stage = reg & STATUS_STAGE_MASK;
211
212 if (stage > chip->stage) {
213 /* increasing stage, use lower bound */
214 chip->temperature = (stage - 1) * TEMP_STAGE_STEP
215 + chip->thresh * TEMP_THRESH_STEP
216 + TEMP_STAGE_HYSTERESIS + TEMP_THRESH_MIN;
217 } else if (stage < chip->stage) {
218 /* decreasing stage, use upper bound */
219 chip->temperature = stage * TEMP_STAGE_STEP
220 + chip->thresh * TEMP_THRESH_STEP
221 - TEMP_STAGE_HYSTERESIS + TEMP_THRESH_MIN;
222 }
223
224 chip->stage = stage;
225
226 return 0;
227}
228
229static int qpnp_tz_get_temp_no_adc(struct thermal_zone_device *thermal,
230 unsigned long *temperature)
231{
232 struct qpnp_tm_chip *chip = thermal->devdata;
233 int rc;
234
235 if (!temperature)
236 return -EINVAL;
237
238 rc = qpnp_tm_update_temp_no_adc(chip);
239 if (rc < 0)
240 return rc;
241
242 *temperature = chip->temperature;
243
244 return 0;
245}
246
247static int qpnp_tz_get_temp_qpnp_adc(struct thermal_zone_device *thermal,
248 unsigned long *temperature)
249{
250 struct qpnp_tm_chip *chip = thermal->devdata;
251 int rc;
252
253 if (!temperature)
254 return -EINVAL;
255
256 rc = qpnp_tm_update_temp(chip);
257 if (rc < 0) {
258 dev_err(&chip->spmi_dev->dev, "%s: %s: adc read failed, rc = %d\n",
259 __func__, chip->tm_name, rc);
260 return rc;
261 }
262
263 *temperature = chip->temperature;
264
265 return 0;
266}
267
268static int qpnp_tz_get_mode(struct thermal_zone_device *thermal,
269 enum thermal_device_mode *mode)
270{
271 struct qpnp_tm_chip *chip = thermal->devdata;
272
273 if (!mode)
274 return -EINVAL;
275
276 *mode = chip->mode;
277
278 return 0;
279}
280
281static int qpnp_tz_set_mode(struct thermal_zone_device *thermal,
282 enum thermal_device_mode mode)
283{
284 struct qpnp_tm_chip *chip = thermal->devdata;
285 int rc = 0;
286
287 if (mode != chip->mode) {
288 if (mode == THERMAL_DEVICE_ENABLED)
289 rc = qpnp_tm_shutdown_override(chip,
290 SOFTWARE_OVERRIDE_ENABLED);
291 else
292 rc = qpnp_tm_shutdown_override(chip,
293 SOFTWARE_OVERRIDE_DISABLED);
294
295 chip->mode = mode;
296 }
297
298 return rc;
299}
300
301static int qpnp_tz_get_trip_type(struct thermal_zone_device *thermal,
302 int trip, enum thermal_trip_type *type)
303{
304 if (trip < 0 || !type)
305 return -EINVAL;
306
307 switch (trip) {
308 case TRIP_STAGE3:
309 *type = THERMAL_TRIP_CRITICAL;
310 break;
311 case TRIP_STAGE2:
312 *type = THERMAL_TRIP_HOT;
313 break;
314 case TRIP_STAGE1:
315 *type = THERMAL_TRIP_HOT;
316 break;
317 default:
318 return -EINVAL;
319 }
320
321 return 0;
322}
323
324static int qpnp_tz_get_trip_temp(struct thermal_zone_device *thermal,
325 int trip, unsigned long *temperature)
326{
327 struct qpnp_tm_chip *chip = thermal->devdata;
328 int thresh_temperature;
329
330 if (trip < 0 || !temperature)
331 return -EINVAL;
332
333 thresh_temperature = chip->thresh * TEMP_THRESH_STEP + TEMP_THRESH_MIN;
334
335 switch (trip) {
336 case TRIP_STAGE3:
337 thresh_temperature += 2 * TEMP_STAGE_STEP;
338 break;
339 case TRIP_STAGE2:
340 thresh_temperature += TEMP_STAGE_STEP;
341 break;
342 case TRIP_STAGE1:
343 break;
344 default:
345 return -EINVAL;
346 }
347
348 *temperature = thresh_temperature;
349
350 return 0;
351}
352
353static int qpnp_tz_get_crit_temp(struct thermal_zone_device *thermal,
354 unsigned long *temperature)
355{
356 struct qpnp_tm_chip *chip = thermal->devdata;
357
358 if (!temperature)
359 return -EINVAL;
360
361 *temperature = chip->thresh * TEMP_THRESH_STEP + TEMP_THRESH_MIN +
362 2 * TEMP_STAGE_STEP;
363
364 return 0;
365}
366
367static struct thermal_zone_device_ops qpnp_thermal_zone_ops_no_adc = {
368 .get_temp = qpnp_tz_get_temp_no_adc,
369 .get_mode = qpnp_tz_get_mode,
370 .set_mode = qpnp_tz_set_mode,
371 .get_trip_type = qpnp_tz_get_trip_type,
372 .get_trip_temp = qpnp_tz_get_trip_temp,
373 .get_crit_temp = qpnp_tz_get_crit_temp,
374};
375
376static struct thermal_zone_device_ops qpnp_thermal_zone_ops_qpnp_adc = {
377 .get_temp = qpnp_tz_get_temp_qpnp_adc,
378 .get_mode = qpnp_tz_get_mode,
379 .set_mode = qpnp_tz_set_mode,
380 .get_trip_type = qpnp_tz_get_trip_type,
381 .get_trip_temp = qpnp_tz_get_trip_temp,
382 .get_crit_temp = qpnp_tz_get_crit_temp,
383};
384
385static void qpnp_tm_work(struct work_struct *work)
386{
387 struct delayed_work *dwork
388 = container_of(work, struct delayed_work, work);
389 struct qpnp_tm_chip *chip
390 = container_of(dwork, struct qpnp_tm_chip, irq_work);
391 int rc;
392 u8 reg;
393
394 if (chip->adc_type == QPNP_TM_ADC_NONE) {
395 rc = qpnp_tm_update_temp_no_adc(chip);
396 if (rc < 0)
397 goto bail;
398 } else {
399 rc = qpnp_tm_read(chip, QPNP_TM_REG_STATUS, &reg, 1);
400 if (rc < 0)
401 goto bail;
402
403 chip->stage = reg & STATUS_STAGE_MASK;
404
405 rc = qpnp_tm_update_temp(chip);
406 if (rc < 0)
407 goto bail;
408 }
409
410 if (chip->stage != chip->prev_stage) {
411 chip->prev_stage = chip->stage;
412
413 pr_crit("%s: PMIC Temp Alarm - stage=%u, threshold=%u, temperature=%lu mC\n",
414 chip->tm_name, chip->stage, chip->thresh,
415 chip->temperature);
416
417 thermal_zone_device_update(chip->tz_dev);
418
419 /* Notify user space */
420 sysfs_notify(&chip->tz_dev->device.kobj, NULL, "type");
421 }
422
423bail:
424 return;
425}
426
427static irqreturn_t qpnp_tm_isr(int irq, void *data)
428{
429 struct qpnp_tm_chip *chip = data;
430
431 schedule_delayed_work(&chip->irq_work,
432 msecs_to_jiffies(STATUS_REGISTER_DELAY_MS) + 1);
433
434 return IRQ_HANDLED;
435}
436
437static int qpnp_tm_init_reg(struct qpnp_tm_chip *chip)
438{
439 int rc = 0;
440 u8 reg;
441
442 if (chip->thresh < THRESH_MIN || chip->thresh > THRESH_MAX) {
443 /* Read hardware threshold value if configuration is invalid. */
444 rc = qpnp_tm_read(chip, QPNP_TM_REG_SHUTDOWN_CTRL1, &reg, 1);
445 if (rc < 0)
446 return rc;
447 chip->thresh = reg & SHUTDOWN_CTRL1_THRESHOLD_MASK;
448 }
449
450 /*
451 * Set threshold and disable software override of stage 2 and 3
452 * shutdowns.
453 */
454 reg = chip->thresh & SHUTDOWN_CTRL1_THRESHOLD_MASK;
455 rc = qpnp_tm_write(chip, QPNP_TM_REG_SHUTDOWN_CTRL1, &reg, 1);
456 if (rc < 0)
457 return rc;
458
459 /* Enable the thermal alarm PMIC module in always-on mode. */
460 reg = ALARM_CTRL_FORCE_ENABLE;
461 rc = qpnp_tm_write(chip, QPNP_TM_REG_ALARM_CTRL, &reg, 1);
462
463 return rc;
464}
465
466static int __devinit qpnp_tm_probe(struct spmi_device *spmi)
467{
468 struct device_node *node;
469 struct resource *res;
470 struct qpnp_tm_chip *chip;
471 struct thermal_zone_device_ops *tz_ops;
472 char *tm_name;
473 u32 default_temperature;
474 int rc = 0;
475 u8 raw_type[2], type, subtype;
476
477 if (!spmi || !(&spmi->dev) || !spmi->dev.of_node) {
478 dev_err(&spmi->dev, "%s: device tree node not found\n",
479 __func__);
480 return -EINVAL;
481 }
482
483 node = spmi->dev.of_node;
484
485 chip = kzalloc(sizeof(struct qpnp_tm_chip), GFP_KERNEL);
486 if (!chip) {
487 dev_err(&spmi->dev, "%s: Can't allocate qpnp_tm_chip\n",
488 __func__);
489 return -ENOMEM;
490 }
491
492 dev_set_drvdata(&spmi->dev, chip);
493
494 res = spmi_get_resource(spmi, NULL, IORESOURCE_MEM, 0);
495 if (!res) {
496 dev_err(&spmi->dev, "%s: node is missing base address\n",
497 __func__);
498 rc = -EINVAL;
499 goto free_chip;
500 }
501 chip->base_addr = res->start;
502 chip->spmi_dev = spmi;
503
504 chip->irq = spmi_get_irq(spmi, NULL, 0);
505 if (chip->irq < 0) {
506 rc = chip->irq;
507 dev_err(&spmi->dev, "%s: node is missing irq, rc=%d\n",
508 __func__, rc);
509 goto free_chip;
510 }
511
512 chip->tm_name = of_get_property(node, "label", NULL);
513 if (chip->tm_name == NULL) {
514 dev_err(&spmi->dev, "%s: node is missing label\n",
515 __func__);
516 rc = -EINVAL;
517 goto free_chip;
518 }
519
520 tm_name = kstrdup(chip->tm_name, GFP_KERNEL);
521 if (tm_name == NULL) {
522 dev_err(&spmi->dev, "%s: could not allocate memory for label\n",
523 __func__);
524 rc = -ENOMEM;
525 goto free_chip;
526 }
527 chip->tm_name = tm_name;
528
529 INIT_DELAYED_WORK(&chip->irq_work, qpnp_tm_work);
530
531 /* These bindings are optional, so it is okay if they are not found. */
532 chip->thresh = THRESH_MAX + 1;
533 rc = of_property_read_u32(node, "qcom,threshold-set", &chip->thresh);
534 if (!rc && (chip->thresh < THRESH_MIN || chip->thresh > THRESH_MAX))
535 dev_err(&spmi->dev, "%s: invalid qcom,threshold-set=%u specified\n",
536 __func__, chip->thresh);
537
538 chip->adc_type = QPNP_TM_ADC_NONE;
539 rc = of_property_read_u32(node, "qcom,channel-num", &chip->adc_channel);
540 if (!rc) {
541 if (chip->adc_channel < 0 || chip->adc_channel >= ADC_MAX_NUM) {
542 dev_err(&spmi->dev, "%s: invalid qcom,channel-num=%d specified\n",
543 __func__, chip->adc_channel);
544 } else {
545 chip->adc_type = QPNP_TM_ADC_QPNP_ADC;
546 rc = qpnp_vadc_is_ready();
547 if (rc) {
548 /* Probe retry, do not print an error message */
549 goto err_cancel_work;
550 }
551 }
552 }
553
554 if (chip->adc_type == QPNP_TM_ADC_QPNP_ADC)
555 tz_ops = &qpnp_thermal_zone_ops_qpnp_adc;
556 else
557 tz_ops = &qpnp_thermal_zone_ops_no_adc;
558
559 chip->allow_software_override
560 = of_property_read_bool(node, "qcom,allow-override");
561
562 default_temperature = DEFAULT_NO_ADC_TEMP;
563 rc = of_property_read_u32(node, "qcom,default-temp",
564 &default_temperature);
565 chip->temperature = default_temperature;
566
567 rc = qpnp_tm_read(chip, QPNP_TM_REG_TYPE, raw_type, 2);
568 if (rc) {
569 dev_err(&spmi->dev, "%s: could not read type register, rc=%d\n",
570 __func__, rc);
571 goto err_cancel_work;
572 }
573 type = raw_type[0];
574 subtype = raw_type[1];
575
576 if (type != QPNP_TM_TYPE || subtype != QPNP_TM_SUBTYPE) {
577 dev_err(&spmi->dev, "%s: invalid type=%02X or subtype=%02X register value\n",
578 __func__, type, subtype);
579 rc = -ENODEV;
580 goto err_cancel_work;
581 }
582
583 rc = qpnp_tm_init_reg(chip);
584 if (rc) {
585 dev_err(&spmi->dev, "%s: qpnp_tm_init_reg() failed, rc=%d\n",
586 __func__, rc);
587 goto err_cancel_work;
588 }
589
590 if (chip->adc_type == QPNP_TM_ADC_NONE) {
591 rc = qpnp_tm_init_temp_no_adc(chip);
592 if (rc) {
593 dev_err(&spmi->dev, "%s: qpnp_tm_init_temp_no_adc() failed, rc=%d\n",
594 __func__, rc);
595 goto err_cancel_work;
596 }
597 }
598
599 /* Start in HW control; switch to SW control when user changes mode. */
600 chip->mode = THERMAL_DEVICE_DISABLED;
601 rc = qpnp_tm_shutdown_override(chip, SOFTWARE_OVERRIDE_DISABLED);
602 if (rc) {
603 dev_err(&spmi->dev, "%s: qpnp_tm_shutdown_override() failed, rc=%d\n",
604 __func__, rc);
605 goto err_cancel_work;
606 }
607
608 chip->tz_dev = thermal_zone_device_register(tm_name, TRIP_NUM, chip,
609 tz_ops, 0, 0, 0, 0);
610 if (chip->tz_dev == NULL) {
611 dev_err(&spmi->dev, "%s: thermal_zone_device_register() failed.\n",
612 __func__);
613 rc = -ENODEV;
614 goto err_cancel_work;
615 }
616
617 rc = request_irq(chip->irq, qpnp_tm_isr, IRQF_TRIGGER_RISING, tm_name,
618 chip);
619 if (rc < 0) {
620 dev_err(&spmi->dev, "%s: request_irq(%d) failed: %d\n",
621 __func__, chip->irq, rc);
622 goto err_free_tz;
623 }
624
625 return 0;
626
627err_free_tz:
628 thermal_zone_device_unregister(chip->tz_dev);
629err_cancel_work:
630 cancel_delayed_work_sync(&chip->irq_work);
631 kfree(chip->tm_name);
632free_chip:
633 dev_set_drvdata(&spmi->dev, NULL);
634 kfree(chip);
635 return rc;
636}
637
638static int __devexit qpnp_tm_remove(struct spmi_device *spmi)
639{
640 struct qpnp_tm_chip *chip = dev_get_drvdata(&spmi->dev);
641
642 dev_set_drvdata(&spmi->dev, NULL);
643 thermal_zone_device_unregister(chip->tz_dev);
644 kfree(chip->tm_name);
645 qpnp_tm_shutdown_override(chip, SOFTWARE_OVERRIDE_DISABLED);
646 free_irq(chip->irq, chip);
647 cancel_delayed_work_sync(&chip->irq_work);
648 kfree(chip);
649
650 return 0;
651}
652
653#ifdef CONFIG_PM
654static int qpnp_tm_suspend(struct device *dev)
655{
656 struct qpnp_tm_chip *chip = dev_get_drvdata(dev);
657
658 /* Clear override bits in suspend to allow hardware control */
659 qpnp_tm_shutdown_override(chip, SOFTWARE_OVERRIDE_DISABLED);
660
661 return 0;
662}
663
664static int qpnp_tm_resume(struct device *dev)
665{
666 struct qpnp_tm_chip *chip = dev_get_drvdata(dev);
667
668 /* Override hardware actions so software can control */
669 if (chip->mode == THERMAL_DEVICE_ENABLED)
670 qpnp_tm_shutdown_override(chip, SOFTWARE_OVERRIDE_ENABLED);
671
672 return 0;
673}
674
675static const struct dev_pm_ops qpnp_tm_pm_ops = {
676 .suspend = qpnp_tm_suspend,
677 .resume = qpnp_tm_resume,
678};
679
680#define QPNP_TM_PM_OPS (&qpnp_tm_pm_ops)
681#else
682#define QPNP_TM_PM_OPS NULL
683#endif
684
685static struct of_device_id qpnp_tm_match_table[] = {
686 { .compatible = QPNP_TM_DRIVER_NAME, },
687 {}
688};
689
690static const struct spmi_device_id qpnp_tm_id[] = {
691 { QPNP_TM_DRIVER_NAME, 0 },
692 {}
693};
694
695static struct spmi_driver qpnp_tm_driver = {
696 .driver = {
697 .name = QPNP_TM_DRIVER_NAME,
698 .of_match_table = qpnp_tm_match_table,
699 .owner = THIS_MODULE,
700 .pm = QPNP_TM_PM_OPS,
701 },
702 .probe = qpnp_tm_probe,
703 .remove = __devexit_p(qpnp_tm_remove),
704 .id_table = qpnp_tm_id,
705};
706
707int __init qpnp_tm_init(void)
708{
709 return spmi_driver_register(&qpnp_tm_driver);
710}
711
712static void __exit qpnp_tm_exit(void)
713{
714 spmi_driver_unregister(&qpnp_tm_driver);
715}
716
717module_init(qpnp_tm_init);
718module_exit(qpnp_tm_exit);
719
720MODULE_DESCRIPTION("QPNP PMIC Temperature Alarm driver");
721MODULE_LICENSE("GPL v2");