Ivo van Doorn | a9b3a9f | 2009-10-15 22:04:14 +0200 | [diff] [blame] | 1 | /* |
| 2 | Copyright (C) 2004 - 2009 rt2x00 SourceForge Project |
| 3 | <http://rt2x00.serialmonkey.com> |
| 4 | |
| 5 | This program is free software; you can redistribute it and/or modify |
| 6 | it under the terms of the GNU General Public License as published by |
| 7 | the Free Software Foundation; either version 2 of the License, or |
| 8 | (at your option) any later version. |
| 9 | |
| 10 | This program is distributed in the hope that it will be useful, |
| 11 | but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 12 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 13 | GNU General Public License for more details. |
| 14 | |
| 15 | You should have received a copy of the GNU General Public License |
| 16 | along with this program; if not, write to the |
| 17 | Free Software Foundation, Inc., |
| 18 | 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. |
| 19 | */ |
| 20 | |
| 21 | /* |
| 22 | Module: rt2800pci |
| 23 | Abstract: rt2800pci device specific routines. |
| 24 | Supported chipsets: RT2800E & RT2800ED. |
| 25 | */ |
| 26 | |
| 27 | #include <linux/crc-ccitt.h> |
| 28 | #include <linux/delay.h> |
| 29 | #include <linux/etherdevice.h> |
| 30 | #include <linux/init.h> |
| 31 | #include <linux/kernel.h> |
| 32 | #include <linux/module.h> |
| 33 | #include <linux/pci.h> |
| 34 | #include <linux/platform_device.h> |
| 35 | #include <linux/eeprom_93cx6.h> |
| 36 | |
| 37 | #include "rt2x00.h" |
| 38 | #include "rt2x00pci.h" |
| 39 | #include "rt2x00soc.h" |
Bartlomiej Zolnierkiewicz | 7ef5cc9 | 2009-11-04 18:35:32 +0100 | [diff] [blame^] | 40 | #include "rt2800lib.h" |
Ivo van Doorn | a9b3a9f | 2009-10-15 22:04:14 +0200 | [diff] [blame] | 41 | #include "rt2800pci.h" |
| 42 | |
| 43 | #ifdef CONFIG_RT2800PCI_PCI_MODULE |
| 44 | #define CONFIG_RT2800PCI_PCI |
| 45 | #endif |
| 46 | |
| 47 | #ifdef CONFIG_RT2800PCI_WISOC_MODULE |
| 48 | #define CONFIG_RT2800PCI_WISOC |
| 49 | #endif |
| 50 | |
| 51 | /* |
| 52 | * Allow hardware encryption to be disabled. |
| 53 | */ |
| 54 | static int modparam_nohwcrypt = 1; |
| 55 | module_param_named(nohwcrypt, modparam_nohwcrypt, bool, S_IRUGO); |
| 56 | MODULE_PARM_DESC(nohwcrypt, "Disable hardware encryption."); |
| 57 | |
| 58 | /* |
| 59 | * Register access. |
Bartlomiej Zolnierkiewicz | 8807bb8 | 2009-11-04 18:32:32 +0100 | [diff] [blame] | 60 | * All access to the CSR registers will go through the methods |
Bartlomiej Zolnierkiewicz | 9ca21eb | 2009-11-04 18:33:13 +0100 | [diff] [blame] | 61 | * rt2800_register_read and rt2800_register_write. |
Ivo van Doorn | a9b3a9f | 2009-10-15 22:04:14 +0200 | [diff] [blame] | 62 | * BBP and RF register require indirect register access, |
Bartlomiej Zolnierkiewicz | 8807bb8 | 2009-11-04 18:32:32 +0100 | [diff] [blame] | 63 | * and use the CSR registers BBPCSR and RFCSR to achieve this. |
Ivo van Doorn | a9b3a9f | 2009-10-15 22:04:14 +0200 | [diff] [blame] | 64 | * These indirect registers work with busy bits, |
| 65 | * and we will try maximal REGISTER_BUSY_COUNT times to access |
| 66 | * the register while taking a REGISTER_BUSY_DELAY us delay |
| 67 | * between each attampt. When the busy bit is still set at that time, |
| 68 | * the access attempt is considered to have failed, |
| 69 | * and we will print an error. |
Bartlomiej Zolnierkiewicz | 9ca21eb | 2009-11-04 18:33:13 +0100 | [diff] [blame] | 70 | * The _lock versions must be used if you already hold the csr_mutex |
Ivo van Doorn | a9b3a9f | 2009-10-15 22:04:14 +0200 | [diff] [blame] | 71 | */ |
| 72 | #define WAIT_FOR_BBP(__dev, __reg) \ |
Bartlomiej Zolnierkiewicz | b4a77d0 | 2009-11-04 18:33:41 +0100 | [diff] [blame] | 73 | rt2800_regbusy_read((__dev), BBP_CSR_CFG, BBP_CSR_CFG_BUSY, (__reg)) |
Ivo van Doorn | a9b3a9f | 2009-10-15 22:04:14 +0200 | [diff] [blame] | 74 | #define WAIT_FOR_RFCSR(__dev, __reg) \ |
Bartlomiej Zolnierkiewicz | b4a77d0 | 2009-11-04 18:33:41 +0100 | [diff] [blame] | 75 | rt2800_regbusy_read((__dev), RF_CSR_CFG, RF_CSR_CFG_BUSY, (__reg)) |
Ivo van Doorn | a9b3a9f | 2009-10-15 22:04:14 +0200 | [diff] [blame] | 76 | #define WAIT_FOR_RF(__dev, __reg) \ |
Bartlomiej Zolnierkiewicz | b4a77d0 | 2009-11-04 18:33:41 +0100 | [diff] [blame] | 77 | rt2800_regbusy_read((__dev), RF_CSR_CFG0, RF_CSR_CFG0_BUSY, (__reg)) |
Ivo van Doorn | a9b3a9f | 2009-10-15 22:04:14 +0200 | [diff] [blame] | 78 | #define WAIT_FOR_MCU(__dev, __reg) \ |
Bartlomiej Zolnierkiewicz | b4a77d0 | 2009-11-04 18:33:41 +0100 | [diff] [blame] | 79 | rt2800_regbusy_read((__dev), H2M_MAILBOX_CSR, \ |
| 80 | H2M_MAILBOX_CSR_OWNER, (__reg)) |
Ivo van Doorn | a9b3a9f | 2009-10-15 22:04:14 +0200 | [diff] [blame] | 81 | |
| 82 | static void rt2800pci_bbp_write(struct rt2x00_dev *rt2x00dev, |
| 83 | const unsigned int word, const u8 value) |
| 84 | { |
| 85 | u32 reg; |
| 86 | |
| 87 | mutex_lock(&rt2x00dev->csr_mutex); |
| 88 | |
| 89 | /* |
| 90 | * Wait until the BBP becomes available, afterwards we |
| 91 | * can safely write the new data into the register. |
| 92 | */ |
| 93 | if (WAIT_FOR_BBP(rt2x00dev, ®)) { |
| 94 | reg = 0; |
| 95 | rt2x00_set_field32(®, BBP_CSR_CFG_VALUE, value); |
| 96 | rt2x00_set_field32(®, BBP_CSR_CFG_REGNUM, word); |
| 97 | rt2x00_set_field32(®, BBP_CSR_CFG_BUSY, 1); |
| 98 | rt2x00_set_field32(®, BBP_CSR_CFG_READ_CONTROL, 0); |
| 99 | rt2x00_set_field32(®, BBP_CSR_CFG_BBP_RW_MODE, 1); |
| 100 | |
Bartlomiej Zolnierkiewicz | 9ca21eb | 2009-11-04 18:33:13 +0100 | [diff] [blame] | 101 | rt2800_register_write_lock(rt2x00dev, BBP_CSR_CFG, reg); |
Ivo van Doorn | a9b3a9f | 2009-10-15 22:04:14 +0200 | [diff] [blame] | 102 | } |
| 103 | |
| 104 | mutex_unlock(&rt2x00dev->csr_mutex); |
| 105 | } |
| 106 | |
| 107 | static void rt2800pci_bbp_read(struct rt2x00_dev *rt2x00dev, |
| 108 | const unsigned int word, u8 *value) |
| 109 | { |
| 110 | u32 reg; |
| 111 | |
| 112 | mutex_lock(&rt2x00dev->csr_mutex); |
| 113 | |
| 114 | /* |
| 115 | * Wait until the BBP becomes available, afterwards we |
| 116 | * can safely write the read request into the register. |
| 117 | * After the data has been written, we wait until hardware |
| 118 | * returns the correct value, if at any time the register |
| 119 | * doesn't become available in time, reg will be 0xffffffff |
| 120 | * which means we return 0xff to the caller. |
| 121 | */ |
| 122 | if (WAIT_FOR_BBP(rt2x00dev, ®)) { |
| 123 | reg = 0; |
| 124 | rt2x00_set_field32(®, BBP_CSR_CFG_REGNUM, word); |
| 125 | rt2x00_set_field32(®, BBP_CSR_CFG_BUSY, 1); |
| 126 | rt2x00_set_field32(®, BBP_CSR_CFG_READ_CONTROL, 1); |
| 127 | rt2x00_set_field32(®, BBP_CSR_CFG_BBP_RW_MODE, 1); |
| 128 | |
Bartlomiej Zolnierkiewicz | 9ca21eb | 2009-11-04 18:33:13 +0100 | [diff] [blame] | 129 | rt2800_register_write_lock(rt2x00dev, BBP_CSR_CFG, reg); |
Ivo van Doorn | a9b3a9f | 2009-10-15 22:04:14 +0200 | [diff] [blame] | 130 | |
| 131 | WAIT_FOR_BBP(rt2x00dev, ®); |
| 132 | } |
| 133 | |
| 134 | *value = rt2x00_get_field32(reg, BBP_CSR_CFG_VALUE); |
| 135 | |
| 136 | mutex_unlock(&rt2x00dev->csr_mutex); |
| 137 | } |
| 138 | |
Bartlomiej Zolnierkiewicz | 3e2c9df | 2009-11-04 18:33:57 +0100 | [diff] [blame] | 139 | static inline void rt2800_bbp_write(struct rt2x00_dev *rt2x00dev, |
| 140 | const unsigned int word, const u8 value) |
| 141 | { |
| 142 | rt2800pci_bbp_write(rt2x00dev, word, value); |
| 143 | } |
| 144 | |
| 145 | static inline void rt2800_bbp_read(struct rt2x00_dev *rt2x00dev, |
| 146 | const unsigned int word, u8 *value) |
| 147 | { |
| 148 | rt2800pci_bbp_read(rt2x00dev, word, value); |
| 149 | } |
| 150 | |
Ivo van Doorn | a9b3a9f | 2009-10-15 22:04:14 +0200 | [diff] [blame] | 151 | static void rt2800pci_rfcsr_write(struct rt2x00_dev *rt2x00dev, |
| 152 | const unsigned int word, const u8 value) |
| 153 | { |
| 154 | u32 reg; |
| 155 | |
| 156 | mutex_lock(&rt2x00dev->csr_mutex); |
| 157 | |
| 158 | /* |
| 159 | * Wait until the RFCSR becomes available, afterwards we |
| 160 | * can safely write the new data into the register. |
| 161 | */ |
| 162 | if (WAIT_FOR_RFCSR(rt2x00dev, ®)) { |
| 163 | reg = 0; |
| 164 | rt2x00_set_field32(®, RF_CSR_CFG_DATA, value); |
| 165 | rt2x00_set_field32(®, RF_CSR_CFG_REGNUM, word); |
| 166 | rt2x00_set_field32(®, RF_CSR_CFG_WRITE, 1); |
| 167 | rt2x00_set_field32(®, RF_CSR_CFG_BUSY, 1); |
| 168 | |
Bartlomiej Zolnierkiewicz | 9ca21eb | 2009-11-04 18:33:13 +0100 | [diff] [blame] | 169 | rt2800_register_write_lock(rt2x00dev, RF_CSR_CFG, reg); |
Ivo van Doorn | a9b3a9f | 2009-10-15 22:04:14 +0200 | [diff] [blame] | 170 | } |
| 171 | |
| 172 | mutex_unlock(&rt2x00dev->csr_mutex); |
| 173 | } |
| 174 | |
| 175 | static void rt2800pci_rfcsr_read(struct rt2x00_dev *rt2x00dev, |
| 176 | const unsigned int word, u8 *value) |
| 177 | { |
| 178 | u32 reg; |
| 179 | |
| 180 | mutex_lock(&rt2x00dev->csr_mutex); |
| 181 | |
| 182 | /* |
| 183 | * Wait until the RFCSR becomes available, afterwards we |
| 184 | * can safely write the read request into the register. |
| 185 | * After the data has been written, we wait until hardware |
| 186 | * returns the correct value, if at any time the register |
| 187 | * doesn't become available in time, reg will be 0xffffffff |
| 188 | * which means we return 0xff to the caller. |
| 189 | */ |
| 190 | if (WAIT_FOR_RFCSR(rt2x00dev, ®)) { |
| 191 | reg = 0; |
| 192 | rt2x00_set_field32(®, RF_CSR_CFG_REGNUM, word); |
| 193 | rt2x00_set_field32(®, RF_CSR_CFG_WRITE, 0); |
| 194 | rt2x00_set_field32(®, RF_CSR_CFG_BUSY, 1); |
| 195 | |
Bartlomiej Zolnierkiewicz | 9ca21eb | 2009-11-04 18:33:13 +0100 | [diff] [blame] | 196 | rt2800_register_write_lock(rt2x00dev, RF_CSR_CFG, reg); |
Ivo van Doorn | a9b3a9f | 2009-10-15 22:04:14 +0200 | [diff] [blame] | 197 | |
| 198 | WAIT_FOR_RFCSR(rt2x00dev, ®); |
| 199 | } |
| 200 | |
| 201 | *value = rt2x00_get_field32(reg, RF_CSR_CFG_DATA); |
| 202 | |
| 203 | mutex_unlock(&rt2x00dev->csr_mutex); |
| 204 | } |
| 205 | |
Bartlomiej Zolnierkiewicz | 1af68f7 | 2009-11-04 18:34:11 +0100 | [diff] [blame] | 206 | static inline void rt2800_rfcsr_write(struct rt2x00_dev *rt2x00dev, |
| 207 | const unsigned int word, const u8 value) |
| 208 | { |
| 209 | rt2800pci_rfcsr_write(rt2x00dev, word, value); |
| 210 | } |
| 211 | |
| 212 | static inline void rt2800_rfcsr_read(struct rt2x00_dev *rt2x00dev, |
| 213 | const unsigned int word, u8 *value) |
| 214 | { |
| 215 | rt2800pci_rfcsr_read(rt2x00dev, word, value); |
| 216 | } |
| 217 | |
Ivo van Doorn | a9b3a9f | 2009-10-15 22:04:14 +0200 | [diff] [blame] | 218 | static void rt2800pci_rf_write(struct rt2x00_dev *rt2x00dev, |
| 219 | const unsigned int word, const u32 value) |
| 220 | { |
| 221 | u32 reg; |
| 222 | |
| 223 | mutex_lock(&rt2x00dev->csr_mutex); |
| 224 | |
| 225 | /* |
| 226 | * Wait until the RF becomes available, afterwards we |
| 227 | * can safely write the new data into the register. |
| 228 | */ |
| 229 | if (WAIT_FOR_RF(rt2x00dev, ®)) { |
| 230 | reg = 0; |
| 231 | rt2x00_set_field32(®, RF_CSR_CFG0_REG_VALUE_BW, value); |
| 232 | rt2x00_set_field32(®, RF_CSR_CFG0_STANDBYMODE, 0); |
| 233 | rt2x00_set_field32(®, RF_CSR_CFG0_SEL, 0); |
| 234 | rt2x00_set_field32(®, RF_CSR_CFG0_BUSY, 1); |
| 235 | |
Bartlomiej Zolnierkiewicz | 9ca21eb | 2009-11-04 18:33:13 +0100 | [diff] [blame] | 236 | rt2800_register_write_lock(rt2x00dev, RF_CSR_CFG0, reg); |
Ivo van Doorn | a9b3a9f | 2009-10-15 22:04:14 +0200 | [diff] [blame] | 237 | rt2x00_rf_write(rt2x00dev, word, value); |
| 238 | } |
| 239 | |
| 240 | mutex_unlock(&rt2x00dev->csr_mutex); |
| 241 | } |
| 242 | |
Bartlomiej Zolnierkiewicz | ada0394 | 2009-11-04 18:34:25 +0100 | [diff] [blame] | 243 | static inline void rt2800_rf_write(struct rt2x00_dev *rt2x00dev, |
| 244 | const unsigned int word, const u32 value) |
| 245 | { |
| 246 | rt2800pci_rf_write(rt2x00dev, word, value); |
| 247 | } |
| 248 | |
Ivo van Doorn | a9b3a9f | 2009-10-15 22:04:14 +0200 | [diff] [blame] | 249 | static void rt2800pci_mcu_request(struct rt2x00_dev *rt2x00dev, |
| 250 | const u8 command, const u8 token, |
| 251 | const u8 arg0, const u8 arg1) |
| 252 | { |
| 253 | u32 reg; |
| 254 | |
| 255 | /* |
| 256 | * RT2880 and RT3052 don't support MCU requests. |
| 257 | */ |
| 258 | if (rt2x00_rt(&rt2x00dev->chip, RT2880) || |
| 259 | rt2x00_rt(&rt2x00dev->chip, RT3052)) |
| 260 | return; |
| 261 | |
| 262 | mutex_lock(&rt2x00dev->csr_mutex); |
| 263 | |
| 264 | /* |
| 265 | * Wait until the MCU becomes available, afterwards we |
| 266 | * can safely write the new data into the register. |
| 267 | */ |
| 268 | if (WAIT_FOR_MCU(rt2x00dev, ®)) { |
| 269 | rt2x00_set_field32(®, H2M_MAILBOX_CSR_OWNER, 1); |
| 270 | rt2x00_set_field32(®, H2M_MAILBOX_CSR_CMD_TOKEN, token); |
| 271 | rt2x00_set_field32(®, H2M_MAILBOX_CSR_ARG0, arg0); |
| 272 | rt2x00_set_field32(®, H2M_MAILBOX_CSR_ARG1, arg1); |
Bartlomiej Zolnierkiewicz | 9ca21eb | 2009-11-04 18:33:13 +0100 | [diff] [blame] | 273 | rt2800_register_write_lock(rt2x00dev, H2M_MAILBOX_CSR, reg); |
Ivo van Doorn | a9b3a9f | 2009-10-15 22:04:14 +0200 | [diff] [blame] | 274 | |
| 275 | reg = 0; |
| 276 | rt2x00_set_field32(®, HOST_CMD_CSR_HOST_COMMAND, command); |
Bartlomiej Zolnierkiewicz | 9ca21eb | 2009-11-04 18:33:13 +0100 | [diff] [blame] | 277 | rt2800_register_write_lock(rt2x00dev, HOST_CMD_CSR, reg); |
Ivo van Doorn | a9b3a9f | 2009-10-15 22:04:14 +0200 | [diff] [blame] | 278 | } |
| 279 | |
| 280 | mutex_unlock(&rt2x00dev->csr_mutex); |
| 281 | } |
| 282 | |
Bartlomiej Zolnierkiewicz | 3a9e5b0 | 2009-11-04 18:34:39 +0100 | [diff] [blame] | 283 | static inline void rt2800_mcu_request(struct rt2x00_dev *rt2x00dev, |
| 284 | const u8 command, const u8 token, |
| 285 | const u8 arg0, const u8 arg1) |
| 286 | { |
| 287 | rt2800pci_mcu_request(rt2x00dev, command, token, arg0, arg1); |
| 288 | } |
| 289 | |
Ivo van Doorn | a9b3a9f | 2009-10-15 22:04:14 +0200 | [diff] [blame] | 290 | static void rt2800pci_mcu_status(struct rt2x00_dev *rt2x00dev, const u8 token) |
| 291 | { |
| 292 | unsigned int i; |
| 293 | u32 reg; |
| 294 | |
| 295 | for (i = 0; i < 200; i++) { |
Bartlomiej Zolnierkiewicz | 9ca21eb | 2009-11-04 18:33:13 +0100 | [diff] [blame] | 296 | rt2800_register_read(rt2x00dev, H2M_MAILBOX_CID, ®); |
Ivo van Doorn | a9b3a9f | 2009-10-15 22:04:14 +0200 | [diff] [blame] | 297 | |
| 298 | if ((rt2x00_get_field32(reg, H2M_MAILBOX_CID_CMD0) == token) || |
| 299 | (rt2x00_get_field32(reg, H2M_MAILBOX_CID_CMD1) == token) || |
| 300 | (rt2x00_get_field32(reg, H2M_MAILBOX_CID_CMD2) == token) || |
| 301 | (rt2x00_get_field32(reg, H2M_MAILBOX_CID_CMD3) == token)) |
| 302 | break; |
| 303 | |
| 304 | udelay(REGISTER_BUSY_DELAY); |
| 305 | } |
| 306 | |
| 307 | if (i == 200) |
| 308 | ERROR(rt2x00dev, "MCU request failed, no response from hardware\n"); |
| 309 | |
Bartlomiej Zolnierkiewicz | 9ca21eb | 2009-11-04 18:33:13 +0100 | [diff] [blame] | 310 | rt2800_register_write(rt2x00dev, H2M_MAILBOX_STATUS, ~0); |
| 311 | rt2800_register_write(rt2x00dev, H2M_MAILBOX_CID, ~0); |
Ivo van Doorn | a9b3a9f | 2009-10-15 22:04:14 +0200 | [diff] [blame] | 312 | } |
| 313 | |
| 314 | #ifdef CONFIG_RT2800PCI_WISOC |
| 315 | static void rt2800pci_read_eeprom_soc(struct rt2x00_dev *rt2x00dev) |
| 316 | { |
| 317 | u32 *base_addr = (u32 *) KSEG1ADDR(0x1F040000); /* XXX for RT3052 */ |
| 318 | |
| 319 | memcpy_fromio(rt2x00dev->eeprom, base_addr, EEPROM_SIZE); |
| 320 | } |
| 321 | #else |
| 322 | static inline void rt2800pci_read_eeprom_soc(struct rt2x00_dev *rt2x00dev) |
| 323 | { |
| 324 | } |
| 325 | #endif /* CONFIG_RT2800PCI_WISOC */ |
| 326 | |
| 327 | #ifdef CONFIG_RT2800PCI_PCI |
| 328 | static void rt2800pci_eepromregister_read(struct eeprom_93cx6 *eeprom) |
| 329 | { |
| 330 | struct rt2x00_dev *rt2x00dev = eeprom->data; |
| 331 | u32 reg; |
| 332 | |
Bartlomiej Zolnierkiewicz | 9ca21eb | 2009-11-04 18:33:13 +0100 | [diff] [blame] | 333 | rt2800_register_read(rt2x00dev, E2PROM_CSR, ®); |
Ivo van Doorn | a9b3a9f | 2009-10-15 22:04:14 +0200 | [diff] [blame] | 334 | |
| 335 | eeprom->reg_data_in = !!rt2x00_get_field32(reg, E2PROM_CSR_DATA_IN); |
| 336 | eeprom->reg_data_out = !!rt2x00_get_field32(reg, E2PROM_CSR_DATA_OUT); |
| 337 | eeprom->reg_data_clock = |
| 338 | !!rt2x00_get_field32(reg, E2PROM_CSR_DATA_CLOCK); |
| 339 | eeprom->reg_chip_select = |
| 340 | !!rt2x00_get_field32(reg, E2PROM_CSR_CHIP_SELECT); |
| 341 | } |
| 342 | |
| 343 | static void rt2800pci_eepromregister_write(struct eeprom_93cx6 *eeprom) |
| 344 | { |
| 345 | struct rt2x00_dev *rt2x00dev = eeprom->data; |
| 346 | u32 reg = 0; |
| 347 | |
| 348 | rt2x00_set_field32(®, E2PROM_CSR_DATA_IN, !!eeprom->reg_data_in); |
| 349 | rt2x00_set_field32(®, E2PROM_CSR_DATA_OUT, !!eeprom->reg_data_out); |
| 350 | rt2x00_set_field32(®, E2PROM_CSR_DATA_CLOCK, |
| 351 | !!eeprom->reg_data_clock); |
| 352 | rt2x00_set_field32(®, E2PROM_CSR_CHIP_SELECT, |
| 353 | !!eeprom->reg_chip_select); |
| 354 | |
Bartlomiej Zolnierkiewicz | 9ca21eb | 2009-11-04 18:33:13 +0100 | [diff] [blame] | 355 | rt2800_register_write(rt2x00dev, E2PROM_CSR, reg); |
Ivo van Doorn | a9b3a9f | 2009-10-15 22:04:14 +0200 | [diff] [blame] | 356 | } |
| 357 | |
| 358 | static void rt2800pci_read_eeprom_pci(struct rt2x00_dev *rt2x00dev) |
| 359 | { |
| 360 | struct eeprom_93cx6 eeprom; |
| 361 | u32 reg; |
| 362 | |
Bartlomiej Zolnierkiewicz | 9ca21eb | 2009-11-04 18:33:13 +0100 | [diff] [blame] | 363 | rt2800_register_read(rt2x00dev, E2PROM_CSR, ®); |
Ivo van Doorn | a9b3a9f | 2009-10-15 22:04:14 +0200 | [diff] [blame] | 364 | |
| 365 | eeprom.data = rt2x00dev; |
| 366 | eeprom.register_read = rt2800pci_eepromregister_read; |
| 367 | eeprom.register_write = rt2800pci_eepromregister_write; |
| 368 | eeprom.width = !rt2x00_get_field32(reg, E2PROM_CSR_TYPE) ? |
| 369 | PCI_EEPROM_WIDTH_93C46 : PCI_EEPROM_WIDTH_93C66; |
| 370 | eeprom.reg_data_in = 0; |
| 371 | eeprom.reg_data_out = 0; |
| 372 | eeprom.reg_data_clock = 0; |
| 373 | eeprom.reg_chip_select = 0; |
| 374 | |
| 375 | eeprom_93cx6_multiread(&eeprom, EEPROM_BASE, rt2x00dev->eeprom, |
| 376 | EEPROM_SIZE / sizeof(u16)); |
| 377 | } |
| 378 | |
| 379 | static void rt2800pci_efuse_read(struct rt2x00_dev *rt2x00dev, |
| 380 | unsigned int i) |
| 381 | { |
| 382 | u32 reg; |
| 383 | |
Bartlomiej Zolnierkiewicz | 9ca21eb | 2009-11-04 18:33:13 +0100 | [diff] [blame] | 384 | rt2800_register_read(rt2x00dev, EFUSE_CTRL, ®); |
Ivo van Doorn | a9b3a9f | 2009-10-15 22:04:14 +0200 | [diff] [blame] | 385 | rt2x00_set_field32(®, EFUSE_CTRL_ADDRESS_IN, i); |
| 386 | rt2x00_set_field32(®, EFUSE_CTRL_MODE, 0); |
| 387 | rt2x00_set_field32(®, EFUSE_CTRL_KICK, 1); |
Bartlomiej Zolnierkiewicz | 9ca21eb | 2009-11-04 18:33:13 +0100 | [diff] [blame] | 388 | rt2800_register_write(rt2x00dev, EFUSE_CTRL, reg); |
Ivo van Doorn | a9b3a9f | 2009-10-15 22:04:14 +0200 | [diff] [blame] | 389 | |
| 390 | /* Wait until the EEPROM has been loaded */ |
Bartlomiej Zolnierkiewicz | b4a77d0 | 2009-11-04 18:33:41 +0100 | [diff] [blame] | 391 | rt2800_regbusy_read(rt2x00dev, EFUSE_CTRL, EFUSE_CTRL_KICK, ®); |
Ivo van Doorn | a9b3a9f | 2009-10-15 22:04:14 +0200 | [diff] [blame] | 392 | |
| 393 | /* Apparently the data is read from end to start */ |
Bartlomiej Zolnierkiewicz | 9ca21eb | 2009-11-04 18:33:13 +0100 | [diff] [blame] | 394 | rt2800_register_read(rt2x00dev, EFUSE_DATA3, |
Ivo van Doorn | a9b3a9f | 2009-10-15 22:04:14 +0200 | [diff] [blame] | 395 | (u32 *)&rt2x00dev->eeprom[i]); |
Bartlomiej Zolnierkiewicz | 9ca21eb | 2009-11-04 18:33:13 +0100 | [diff] [blame] | 396 | rt2800_register_read(rt2x00dev, EFUSE_DATA2, |
Ivo van Doorn | a9b3a9f | 2009-10-15 22:04:14 +0200 | [diff] [blame] | 397 | (u32 *)&rt2x00dev->eeprom[i + 2]); |
Bartlomiej Zolnierkiewicz | 9ca21eb | 2009-11-04 18:33:13 +0100 | [diff] [blame] | 398 | rt2800_register_read(rt2x00dev, EFUSE_DATA1, |
Ivo van Doorn | a9b3a9f | 2009-10-15 22:04:14 +0200 | [diff] [blame] | 399 | (u32 *)&rt2x00dev->eeprom[i + 4]); |
Bartlomiej Zolnierkiewicz | 9ca21eb | 2009-11-04 18:33:13 +0100 | [diff] [blame] | 400 | rt2800_register_read(rt2x00dev, EFUSE_DATA0, |
Ivo van Doorn | a9b3a9f | 2009-10-15 22:04:14 +0200 | [diff] [blame] | 401 | (u32 *)&rt2x00dev->eeprom[i + 6]); |
| 402 | } |
| 403 | |
| 404 | static void rt2800pci_read_eeprom_efuse(struct rt2x00_dev *rt2x00dev) |
| 405 | { |
| 406 | unsigned int i; |
| 407 | |
| 408 | for (i = 0; i < EEPROM_SIZE / sizeof(u16); i += 8) |
| 409 | rt2800pci_efuse_read(rt2x00dev, i); |
| 410 | } |
| 411 | #else |
| 412 | static inline void rt2800pci_read_eeprom_pci(struct rt2x00_dev *rt2x00dev) |
| 413 | { |
| 414 | } |
| 415 | |
| 416 | static inline void rt2800pci_read_eeprom_efuse(struct rt2x00_dev *rt2x00dev) |
| 417 | { |
| 418 | } |
| 419 | #endif /* CONFIG_RT2800PCI_PCI */ |
| 420 | |
| 421 | #ifdef CONFIG_RT2X00_LIB_DEBUGFS |
| 422 | static const struct rt2x00debug rt2800pci_rt2x00debug = { |
| 423 | .owner = THIS_MODULE, |
| 424 | .csr = { |
Bartlomiej Zolnierkiewicz | 9ca21eb | 2009-11-04 18:33:13 +0100 | [diff] [blame] | 425 | .read = rt2800_register_read, |
| 426 | .write = rt2800_register_write, |
Ivo van Doorn | a9b3a9f | 2009-10-15 22:04:14 +0200 | [diff] [blame] | 427 | .flags = RT2X00DEBUGFS_OFFSET, |
| 428 | .word_base = CSR_REG_BASE, |
| 429 | .word_size = sizeof(u32), |
| 430 | .word_count = CSR_REG_SIZE / sizeof(u32), |
| 431 | }, |
| 432 | .eeprom = { |
| 433 | .read = rt2x00_eeprom_read, |
| 434 | .write = rt2x00_eeprom_write, |
| 435 | .word_base = EEPROM_BASE, |
| 436 | .word_size = sizeof(u16), |
| 437 | .word_count = EEPROM_SIZE / sizeof(u16), |
| 438 | }, |
| 439 | .bbp = { |
Bartlomiej Zolnierkiewicz | 3e2c9df | 2009-11-04 18:33:57 +0100 | [diff] [blame] | 440 | .read = rt2800_bbp_read, |
| 441 | .write = rt2800_bbp_write, |
Ivo van Doorn | a9b3a9f | 2009-10-15 22:04:14 +0200 | [diff] [blame] | 442 | .word_base = BBP_BASE, |
| 443 | .word_size = sizeof(u8), |
| 444 | .word_count = BBP_SIZE / sizeof(u8), |
| 445 | }, |
| 446 | .rf = { |
| 447 | .read = rt2x00_rf_read, |
Bartlomiej Zolnierkiewicz | ada0394 | 2009-11-04 18:34:25 +0100 | [diff] [blame] | 448 | .write = rt2800_rf_write, |
Ivo van Doorn | a9b3a9f | 2009-10-15 22:04:14 +0200 | [diff] [blame] | 449 | .word_base = RF_BASE, |
| 450 | .word_size = sizeof(u32), |
| 451 | .word_count = RF_SIZE / sizeof(u32), |
| 452 | }, |
| 453 | }; |
| 454 | #endif /* CONFIG_RT2X00_LIB_DEBUGFS */ |
| 455 | |
| 456 | static int rt2800pci_rfkill_poll(struct rt2x00_dev *rt2x00dev) |
| 457 | { |
| 458 | u32 reg; |
| 459 | |
Bartlomiej Zolnierkiewicz | 9ca21eb | 2009-11-04 18:33:13 +0100 | [diff] [blame] | 460 | rt2800_register_read(rt2x00dev, GPIO_CTRL_CFG, ®); |
Ivo van Doorn | a9b3a9f | 2009-10-15 22:04:14 +0200 | [diff] [blame] | 461 | return rt2x00_get_field32(reg, GPIO_CTRL_CFG_BIT2); |
| 462 | } |
| 463 | |
| 464 | #ifdef CONFIG_RT2X00_LIB_LEDS |
| 465 | static void rt2800pci_brightness_set(struct led_classdev *led_cdev, |
| 466 | enum led_brightness brightness) |
| 467 | { |
| 468 | struct rt2x00_led *led = |
| 469 | container_of(led_cdev, struct rt2x00_led, led_dev); |
| 470 | unsigned int enabled = brightness != LED_OFF; |
| 471 | unsigned int bg_mode = |
| 472 | (enabled && led->rt2x00dev->curr_band == IEEE80211_BAND_2GHZ); |
| 473 | unsigned int polarity = |
| 474 | rt2x00_get_field16(led->rt2x00dev->led_mcu_reg, |
| 475 | EEPROM_FREQ_LED_POLARITY); |
| 476 | unsigned int ledmode = |
| 477 | rt2x00_get_field16(led->rt2x00dev->led_mcu_reg, |
| 478 | EEPROM_FREQ_LED_MODE); |
| 479 | |
| 480 | if (led->type == LED_TYPE_RADIO) { |
Bartlomiej Zolnierkiewicz | 3a9e5b0 | 2009-11-04 18:34:39 +0100 | [diff] [blame] | 481 | rt2800_mcu_request(led->rt2x00dev, MCU_LED, 0xff, ledmode, |
Ivo van Doorn | a9b3a9f | 2009-10-15 22:04:14 +0200 | [diff] [blame] | 482 | enabled ? 0x20 : 0); |
| 483 | } else if (led->type == LED_TYPE_ASSOC) { |
Bartlomiej Zolnierkiewicz | 3a9e5b0 | 2009-11-04 18:34:39 +0100 | [diff] [blame] | 484 | rt2800_mcu_request(led->rt2x00dev, MCU_LED, 0xff, ledmode, |
Ivo van Doorn | a9b3a9f | 2009-10-15 22:04:14 +0200 | [diff] [blame] | 485 | enabled ? (bg_mode ? 0x60 : 0xa0) : 0x20); |
| 486 | } else if (led->type == LED_TYPE_QUALITY) { |
| 487 | /* |
| 488 | * The brightness is divided into 6 levels (0 - 5), |
| 489 | * The specs tell us the following levels: |
| 490 | * 0, 1 ,3, 7, 15, 31 |
| 491 | * to determine the level in a simple way we can simply |
| 492 | * work with bitshifting: |
| 493 | * (1 << level) - 1 |
| 494 | */ |
Bartlomiej Zolnierkiewicz | 3a9e5b0 | 2009-11-04 18:34:39 +0100 | [diff] [blame] | 495 | rt2800_mcu_request(led->rt2x00dev, MCU_LED_STRENGTH, 0xff, |
Ivo van Doorn | a9b3a9f | 2009-10-15 22:04:14 +0200 | [diff] [blame] | 496 | (1 << brightness / (LED_FULL / 6)) - 1, |
| 497 | polarity); |
| 498 | } |
| 499 | } |
| 500 | |
| 501 | static int rt2800pci_blink_set(struct led_classdev *led_cdev, |
| 502 | unsigned long *delay_on, |
| 503 | unsigned long *delay_off) |
| 504 | { |
| 505 | struct rt2x00_led *led = |
| 506 | container_of(led_cdev, struct rt2x00_led, led_dev); |
| 507 | u32 reg; |
| 508 | |
Bartlomiej Zolnierkiewicz | 9ca21eb | 2009-11-04 18:33:13 +0100 | [diff] [blame] | 509 | rt2800_register_read(led->rt2x00dev, LED_CFG, ®); |
Ivo van Doorn | a9b3a9f | 2009-10-15 22:04:14 +0200 | [diff] [blame] | 510 | rt2x00_set_field32(®, LED_CFG_ON_PERIOD, *delay_on); |
| 511 | rt2x00_set_field32(®, LED_CFG_OFF_PERIOD, *delay_off); |
| 512 | rt2x00_set_field32(®, LED_CFG_SLOW_BLINK_PERIOD, 3); |
| 513 | rt2x00_set_field32(®, LED_CFG_R_LED_MODE, 3); |
| 514 | rt2x00_set_field32(®, LED_CFG_G_LED_MODE, 12); |
| 515 | rt2x00_set_field32(®, LED_CFG_Y_LED_MODE, 3); |
| 516 | rt2x00_set_field32(®, LED_CFG_LED_POLAR, 1); |
Bartlomiej Zolnierkiewicz | 9ca21eb | 2009-11-04 18:33:13 +0100 | [diff] [blame] | 517 | rt2800_register_write(led->rt2x00dev, LED_CFG, reg); |
Ivo van Doorn | a9b3a9f | 2009-10-15 22:04:14 +0200 | [diff] [blame] | 518 | |
| 519 | return 0; |
| 520 | } |
| 521 | |
| 522 | static void rt2800pci_init_led(struct rt2x00_dev *rt2x00dev, |
| 523 | struct rt2x00_led *led, |
| 524 | enum led_type type) |
| 525 | { |
| 526 | led->rt2x00dev = rt2x00dev; |
| 527 | led->type = type; |
| 528 | led->led_dev.brightness_set = rt2800pci_brightness_set; |
| 529 | led->led_dev.blink_set = rt2800pci_blink_set; |
| 530 | led->flags = LED_INITIALIZED; |
| 531 | } |
| 532 | #endif /* CONFIG_RT2X00_LIB_LEDS */ |
| 533 | |
| 534 | /* |
| 535 | * Configuration handlers. |
| 536 | */ |
| 537 | static void rt2800pci_config_wcid_attr(struct rt2x00_dev *rt2x00dev, |
| 538 | struct rt2x00lib_crypto *crypto, |
| 539 | struct ieee80211_key_conf *key) |
| 540 | { |
| 541 | struct mac_wcid_entry wcid_entry; |
| 542 | struct mac_iveiv_entry iveiv_entry; |
| 543 | u32 offset; |
| 544 | u32 reg; |
| 545 | |
| 546 | offset = MAC_WCID_ATTR_ENTRY(key->hw_key_idx); |
| 547 | |
Bartlomiej Zolnierkiewicz | 9ca21eb | 2009-11-04 18:33:13 +0100 | [diff] [blame] | 548 | rt2800_register_read(rt2x00dev, offset, ®); |
Ivo van Doorn | a9b3a9f | 2009-10-15 22:04:14 +0200 | [diff] [blame] | 549 | rt2x00_set_field32(®, MAC_WCID_ATTRIBUTE_KEYTAB, |
| 550 | !!(key->flags & IEEE80211_KEY_FLAG_PAIRWISE)); |
| 551 | rt2x00_set_field32(®, MAC_WCID_ATTRIBUTE_CIPHER, |
| 552 | (crypto->cmd == SET_KEY) * crypto->cipher); |
| 553 | rt2x00_set_field32(®, MAC_WCID_ATTRIBUTE_BSS_IDX, |
| 554 | (crypto->cmd == SET_KEY) * crypto->bssidx); |
| 555 | rt2x00_set_field32(®, MAC_WCID_ATTRIBUTE_RX_WIUDF, crypto->cipher); |
Bartlomiej Zolnierkiewicz | 9ca21eb | 2009-11-04 18:33:13 +0100 | [diff] [blame] | 556 | rt2800_register_write(rt2x00dev, offset, reg); |
Ivo van Doorn | a9b3a9f | 2009-10-15 22:04:14 +0200 | [diff] [blame] | 557 | |
| 558 | offset = MAC_IVEIV_ENTRY(key->hw_key_idx); |
| 559 | |
| 560 | memset(&iveiv_entry, 0, sizeof(iveiv_entry)); |
| 561 | if ((crypto->cipher == CIPHER_TKIP) || |
| 562 | (crypto->cipher == CIPHER_TKIP_NO_MIC) || |
| 563 | (crypto->cipher == CIPHER_AES)) |
| 564 | iveiv_entry.iv[3] |= 0x20; |
| 565 | iveiv_entry.iv[3] |= key->keyidx << 6; |
Bartlomiej Zolnierkiewicz | 4f2732c | 2009-11-04 18:33:27 +0100 | [diff] [blame] | 566 | rt2800_register_multiwrite(rt2x00dev, offset, |
Ivo van Doorn | a9b3a9f | 2009-10-15 22:04:14 +0200 | [diff] [blame] | 567 | &iveiv_entry, sizeof(iveiv_entry)); |
| 568 | |
| 569 | offset = MAC_WCID_ENTRY(key->hw_key_idx); |
| 570 | |
| 571 | memset(&wcid_entry, 0, sizeof(wcid_entry)); |
| 572 | if (crypto->cmd == SET_KEY) |
| 573 | memcpy(&wcid_entry, crypto->address, ETH_ALEN); |
Bartlomiej Zolnierkiewicz | 4f2732c | 2009-11-04 18:33:27 +0100 | [diff] [blame] | 574 | rt2800_register_multiwrite(rt2x00dev, offset, |
Ivo van Doorn | a9b3a9f | 2009-10-15 22:04:14 +0200 | [diff] [blame] | 575 | &wcid_entry, sizeof(wcid_entry)); |
| 576 | } |
| 577 | |
| 578 | static int rt2800pci_config_shared_key(struct rt2x00_dev *rt2x00dev, |
| 579 | struct rt2x00lib_crypto *crypto, |
| 580 | struct ieee80211_key_conf *key) |
| 581 | { |
| 582 | struct hw_key_entry key_entry; |
| 583 | struct rt2x00_field32 field; |
| 584 | u32 offset; |
| 585 | u32 reg; |
| 586 | |
| 587 | if (crypto->cmd == SET_KEY) { |
| 588 | key->hw_key_idx = (4 * crypto->bssidx) + key->keyidx; |
| 589 | |
| 590 | memcpy(key_entry.key, crypto->key, |
| 591 | sizeof(key_entry.key)); |
| 592 | memcpy(key_entry.tx_mic, crypto->tx_mic, |
| 593 | sizeof(key_entry.tx_mic)); |
| 594 | memcpy(key_entry.rx_mic, crypto->rx_mic, |
| 595 | sizeof(key_entry.rx_mic)); |
| 596 | |
| 597 | offset = SHARED_KEY_ENTRY(key->hw_key_idx); |
Bartlomiej Zolnierkiewicz | 4f2732c | 2009-11-04 18:33:27 +0100 | [diff] [blame] | 598 | rt2800_register_multiwrite(rt2x00dev, offset, |
Ivo van Doorn | a9b3a9f | 2009-10-15 22:04:14 +0200 | [diff] [blame] | 599 | &key_entry, sizeof(key_entry)); |
| 600 | } |
| 601 | |
| 602 | /* |
| 603 | * The cipher types are stored over multiple registers |
| 604 | * starting with SHARED_KEY_MODE_BASE each word will have |
| 605 | * 32 bits and contains the cipher types for 2 bssidx each. |
| 606 | * Using the correct defines correctly will cause overhead, |
| 607 | * so just calculate the correct offset. |
| 608 | */ |
| 609 | field.bit_offset = 4 * (key->hw_key_idx % 8); |
| 610 | field.bit_mask = 0x7 << field.bit_offset; |
| 611 | |
| 612 | offset = SHARED_KEY_MODE_ENTRY(key->hw_key_idx / 8); |
| 613 | |
Bartlomiej Zolnierkiewicz | 9ca21eb | 2009-11-04 18:33:13 +0100 | [diff] [blame] | 614 | rt2800_register_read(rt2x00dev, offset, ®); |
Ivo van Doorn | a9b3a9f | 2009-10-15 22:04:14 +0200 | [diff] [blame] | 615 | rt2x00_set_field32(®, field, |
| 616 | (crypto->cmd == SET_KEY) * crypto->cipher); |
Bartlomiej Zolnierkiewicz | 9ca21eb | 2009-11-04 18:33:13 +0100 | [diff] [blame] | 617 | rt2800_register_write(rt2x00dev, offset, reg); |
Ivo van Doorn | a9b3a9f | 2009-10-15 22:04:14 +0200 | [diff] [blame] | 618 | |
| 619 | /* |
| 620 | * Update WCID information |
| 621 | */ |
| 622 | rt2800pci_config_wcid_attr(rt2x00dev, crypto, key); |
| 623 | |
| 624 | return 0; |
| 625 | } |
| 626 | |
| 627 | static int rt2800pci_config_pairwise_key(struct rt2x00_dev *rt2x00dev, |
| 628 | struct rt2x00lib_crypto *crypto, |
| 629 | struct ieee80211_key_conf *key) |
| 630 | { |
| 631 | struct hw_key_entry key_entry; |
| 632 | u32 offset; |
| 633 | |
| 634 | if (crypto->cmd == SET_KEY) { |
| 635 | /* |
| 636 | * 1 pairwise key is possible per AID, this means that the AID |
| 637 | * equals our hw_key_idx. Make sure the WCID starts _after_ the |
| 638 | * last possible shared key entry. |
| 639 | */ |
| 640 | if (crypto->aid > (256 - 32)) |
| 641 | return -ENOSPC; |
| 642 | |
| 643 | key->hw_key_idx = 32 + crypto->aid; |
| 644 | |
| 645 | |
| 646 | memcpy(key_entry.key, crypto->key, |
| 647 | sizeof(key_entry.key)); |
| 648 | memcpy(key_entry.tx_mic, crypto->tx_mic, |
| 649 | sizeof(key_entry.tx_mic)); |
| 650 | memcpy(key_entry.rx_mic, crypto->rx_mic, |
| 651 | sizeof(key_entry.rx_mic)); |
| 652 | |
| 653 | offset = PAIRWISE_KEY_ENTRY(key->hw_key_idx); |
Bartlomiej Zolnierkiewicz | 4f2732c | 2009-11-04 18:33:27 +0100 | [diff] [blame] | 654 | rt2800_register_multiwrite(rt2x00dev, offset, |
Ivo van Doorn | a9b3a9f | 2009-10-15 22:04:14 +0200 | [diff] [blame] | 655 | &key_entry, sizeof(key_entry)); |
| 656 | } |
| 657 | |
| 658 | /* |
| 659 | * Update WCID information |
| 660 | */ |
| 661 | rt2800pci_config_wcid_attr(rt2x00dev, crypto, key); |
| 662 | |
| 663 | return 0; |
| 664 | } |
| 665 | |
| 666 | static void rt2800pci_config_filter(struct rt2x00_dev *rt2x00dev, |
| 667 | const unsigned int filter_flags) |
| 668 | { |
| 669 | u32 reg; |
| 670 | |
| 671 | /* |
| 672 | * Start configuration steps. |
| 673 | * Note that the version error will always be dropped |
| 674 | * and broadcast frames will always be accepted since |
| 675 | * there is no filter for it at this time. |
| 676 | */ |
Bartlomiej Zolnierkiewicz | 9ca21eb | 2009-11-04 18:33:13 +0100 | [diff] [blame] | 677 | rt2800_register_read(rt2x00dev, RX_FILTER_CFG, ®); |
Ivo van Doorn | a9b3a9f | 2009-10-15 22:04:14 +0200 | [diff] [blame] | 678 | rt2x00_set_field32(®, RX_FILTER_CFG_DROP_CRC_ERROR, |
| 679 | !(filter_flags & FIF_FCSFAIL)); |
| 680 | rt2x00_set_field32(®, RX_FILTER_CFG_DROP_PHY_ERROR, |
| 681 | !(filter_flags & FIF_PLCPFAIL)); |
| 682 | rt2x00_set_field32(®, RX_FILTER_CFG_DROP_NOT_TO_ME, |
| 683 | !(filter_flags & FIF_PROMISC_IN_BSS)); |
| 684 | rt2x00_set_field32(®, RX_FILTER_CFG_DROP_NOT_MY_BSSD, 0); |
| 685 | rt2x00_set_field32(®, RX_FILTER_CFG_DROP_VER_ERROR, 1); |
| 686 | rt2x00_set_field32(®, RX_FILTER_CFG_DROP_MULTICAST, |
| 687 | !(filter_flags & FIF_ALLMULTI)); |
| 688 | rt2x00_set_field32(®, RX_FILTER_CFG_DROP_BROADCAST, 0); |
| 689 | rt2x00_set_field32(®, RX_FILTER_CFG_DROP_DUPLICATE, 1); |
| 690 | rt2x00_set_field32(®, RX_FILTER_CFG_DROP_CF_END_ACK, |
| 691 | !(filter_flags & FIF_CONTROL)); |
| 692 | rt2x00_set_field32(®, RX_FILTER_CFG_DROP_CF_END, |
| 693 | !(filter_flags & FIF_CONTROL)); |
| 694 | rt2x00_set_field32(®, RX_FILTER_CFG_DROP_ACK, |
| 695 | !(filter_flags & FIF_CONTROL)); |
| 696 | rt2x00_set_field32(®, RX_FILTER_CFG_DROP_CTS, |
| 697 | !(filter_flags & FIF_CONTROL)); |
| 698 | rt2x00_set_field32(®, RX_FILTER_CFG_DROP_RTS, |
| 699 | !(filter_flags & FIF_CONTROL)); |
| 700 | rt2x00_set_field32(®, RX_FILTER_CFG_DROP_PSPOLL, |
| 701 | !(filter_flags & FIF_PSPOLL)); |
| 702 | rt2x00_set_field32(®, RX_FILTER_CFG_DROP_BA, 1); |
| 703 | rt2x00_set_field32(®, RX_FILTER_CFG_DROP_BAR, 0); |
| 704 | rt2x00_set_field32(®, RX_FILTER_CFG_DROP_CNTL, |
| 705 | !(filter_flags & FIF_CONTROL)); |
Bartlomiej Zolnierkiewicz | 9ca21eb | 2009-11-04 18:33:13 +0100 | [diff] [blame] | 706 | rt2800_register_write(rt2x00dev, RX_FILTER_CFG, reg); |
Ivo van Doorn | a9b3a9f | 2009-10-15 22:04:14 +0200 | [diff] [blame] | 707 | } |
| 708 | |
| 709 | static void rt2800pci_config_intf(struct rt2x00_dev *rt2x00dev, |
| 710 | struct rt2x00_intf *intf, |
| 711 | struct rt2x00intf_conf *conf, |
| 712 | const unsigned int flags) |
| 713 | { |
| 714 | unsigned int beacon_base; |
| 715 | u32 reg; |
| 716 | |
| 717 | if (flags & CONFIG_UPDATE_TYPE) { |
| 718 | /* |
| 719 | * Clear current synchronisation setup. |
| 720 | * For the Beacon base registers we only need to clear |
| 721 | * the first byte since that byte contains the VALID and OWNER |
| 722 | * bits which (when set to 0) will invalidate the entire beacon. |
| 723 | */ |
| 724 | beacon_base = HW_BEACON_OFFSET(intf->beacon->entry_idx); |
Bartlomiej Zolnierkiewicz | 9ca21eb | 2009-11-04 18:33:13 +0100 | [diff] [blame] | 725 | rt2800_register_write(rt2x00dev, beacon_base, 0); |
Ivo van Doorn | a9b3a9f | 2009-10-15 22:04:14 +0200 | [diff] [blame] | 726 | |
| 727 | /* |
| 728 | * Enable synchronisation. |
| 729 | */ |
Bartlomiej Zolnierkiewicz | 9ca21eb | 2009-11-04 18:33:13 +0100 | [diff] [blame] | 730 | rt2800_register_read(rt2x00dev, BCN_TIME_CFG, ®); |
Ivo van Doorn | a9b3a9f | 2009-10-15 22:04:14 +0200 | [diff] [blame] | 731 | rt2x00_set_field32(®, BCN_TIME_CFG_TSF_TICKING, 1); |
| 732 | rt2x00_set_field32(®, BCN_TIME_CFG_TSF_SYNC, conf->sync); |
| 733 | rt2x00_set_field32(®, BCN_TIME_CFG_TBTT_ENABLE, 1); |
Bartlomiej Zolnierkiewicz | 9ca21eb | 2009-11-04 18:33:13 +0100 | [diff] [blame] | 734 | rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg); |
Ivo van Doorn | a9b3a9f | 2009-10-15 22:04:14 +0200 | [diff] [blame] | 735 | } |
| 736 | |
| 737 | if (flags & CONFIG_UPDATE_MAC) { |
| 738 | reg = le32_to_cpu(conf->mac[1]); |
| 739 | rt2x00_set_field32(®, MAC_ADDR_DW1_UNICAST_TO_ME_MASK, 0xff); |
| 740 | conf->mac[1] = cpu_to_le32(reg); |
| 741 | |
Bartlomiej Zolnierkiewicz | 4f2732c | 2009-11-04 18:33:27 +0100 | [diff] [blame] | 742 | rt2800_register_multiwrite(rt2x00dev, MAC_ADDR_DW0, |
Ivo van Doorn | a9b3a9f | 2009-10-15 22:04:14 +0200 | [diff] [blame] | 743 | conf->mac, sizeof(conf->mac)); |
| 744 | } |
| 745 | |
| 746 | if (flags & CONFIG_UPDATE_BSSID) { |
| 747 | reg = le32_to_cpu(conf->bssid[1]); |
| 748 | rt2x00_set_field32(®, MAC_BSSID_DW1_BSS_ID_MASK, 0); |
| 749 | rt2x00_set_field32(®, MAC_BSSID_DW1_BSS_BCN_NUM, 0); |
| 750 | conf->bssid[1] = cpu_to_le32(reg); |
| 751 | |
Bartlomiej Zolnierkiewicz | 4f2732c | 2009-11-04 18:33:27 +0100 | [diff] [blame] | 752 | rt2800_register_multiwrite(rt2x00dev, MAC_BSSID_DW0, |
Ivo van Doorn | a9b3a9f | 2009-10-15 22:04:14 +0200 | [diff] [blame] | 753 | conf->bssid, sizeof(conf->bssid)); |
| 754 | } |
| 755 | } |
| 756 | |
| 757 | static void rt2800pci_config_erp(struct rt2x00_dev *rt2x00dev, |
| 758 | struct rt2x00lib_erp *erp) |
| 759 | { |
| 760 | u32 reg; |
| 761 | |
Bartlomiej Zolnierkiewicz | 9ca21eb | 2009-11-04 18:33:13 +0100 | [diff] [blame] | 762 | rt2800_register_read(rt2x00dev, TX_TIMEOUT_CFG, ®); |
Ivo van Doorn | a9b3a9f | 2009-10-15 22:04:14 +0200 | [diff] [blame] | 763 | rt2x00_set_field32(®, TX_TIMEOUT_CFG_RX_ACK_TIMEOUT, 0x20); |
Bartlomiej Zolnierkiewicz | 9ca21eb | 2009-11-04 18:33:13 +0100 | [diff] [blame] | 764 | rt2800_register_write(rt2x00dev, TX_TIMEOUT_CFG, reg); |
Ivo van Doorn | a9b3a9f | 2009-10-15 22:04:14 +0200 | [diff] [blame] | 765 | |
Bartlomiej Zolnierkiewicz | 9ca21eb | 2009-11-04 18:33:13 +0100 | [diff] [blame] | 766 | rt2800_register_read(rt2x00dev, AUTO_RSP_CFG, ®); |
Ivo van Doorn | a9b3a9f | 2009-10-15 22:04:14 +0200 | [diff] [blame] | 767 | rt2x00_set_field32(®, AUTO_RSP_CFG_BAC_ACK_POLICY, |
| 768 | !!erp->short_preamble); |
| 769 | rt2x00_set_field32(®, AUTO_RSP_CFG_AR_PREAMBLE, |
| 770 | !!erp->short_preamble); |
Bartlomiej Zolnierkiewicz | 9ca21eb | 2009-11-04 18:33:13 +0100 | [diff] [blame] | 771 | rt2800_register_write(rt2x00dev, AUTO_RSP_CFG, reg); |
Ivo van Doorn | a9b3a9f | 2009-10-15 22:04:14 +0200 | [diff] [blame] | 772 | |
Bartlomiej Zolnierkiewicz | 9ca21eb | 2009-11-04 18:33:13 +0100 | [diff] [blame] | 773 | rt2800_register_read(rt2x00dev, OFDM_PROT_CFG, ®); |
Ivo van Doorn | a9b3a9f | 2009-10-15 22:04:14 +0200 | [diff] [blame] | 774 | rt2x00_set_field32(®, OFDM_PROT_CFG_PROTECT_CTRL, |
| 775 | erp->cts_protection ? 2 : 0); |
Bartlomiej Zolnierkiewicz | 9ca21eb | 2009-11-04 18:33:13 +0100 | [diff] [blame] | 776 | rt2800_register_write(rt2x00dev, OFDM_PROT_CFG, reg); |
Ivo van Doorn | a9b3a9f | 2009-10-15 22:04:14 +0200 | [diff] [blame] | 777 | |
Bartlomiej Zolnierkiewicz | 9ca21eb | 2009-11-04 18:33:13 +0100 | [diff] [blame] | 778 | rt2800_register_write(rt2x00dev, LEGACY_BASIC_RATE, |
Ivo van Doorn | a9b3a9f | 2009-10-15 22:04:14 +0200 | [diff] [blame] | 779 | erp->basic_rates); |
Bartlomiej Zolnierkiewicz | 9ca21eb | 2009-11-04 18:33:13 +0100 | [diff] [blame] | 780 | rt2800_register_write(rt2x00dev, HT_BASIC_RATE, 0x00008003); |
Ivo van Doorn | a9b3a9f | 2009-10-15 22:04:14 +0200 | [diff] [blame] | 781 | |
Bartlomiej Zolnierkiewicz | 9ca21eb | 2009-11-04 18:33:13 +0100 | [diff] [blame] | 782 | rt2800_register_read(rt2x00dev, BKOFF_SLOT_CFG, ®); |
Ivo van Doorn | a9b3a9f | 2009-10-15 22:04:14 +0200 | [diff] [blame] | 783 | rt2x00_set_field32(®, BKOFF_SLOT_CFG_SLOT_TIME, erp->slot_time); |
| 784 | rt2x00_set_field32(®, BKOFF_SLOT_CFG_CC_DELAY_TIME, 2); |
Bartlomiej Zolnierkiewicz | 9ca21eb | 2009-11-04 18:33:13 +0100 | [diff] [blame] | 785 | rt2800_register_write(rt2x00dev, BKOFF_SLOT_CFG, reg); |
Ivo van Doorn | a9b3a9f | 2009-10-15 22:04:14 +0200 | [diff] [blame] | 786 | |
Bartlomiej Zolnierkiewicz | 9ca21eb | 2009-11-04 18:33:13 +0100 | [diff] [blame] | 787 | rt2800_register_read(rt2x00dev, XIFS_TIME_CFG, ®); |
Ivo van Doorn | a9b3a9f | 2009-10-15 22:04:14 +0200 | [diff] [blame] | 788 | rt2x00_set_field32(®, XIFS_TIME_CFG_CCKM_SIFS_TIME, erp->sifs); |
| 789 | rt2x00_set_field32(®, XIFS_TIME_CFG_OFDM_SIFS_TIME, erp->sifs); |
| 790 | rt2x00_set_field32(®, XIFS_TIME_CFG_OFDM_XIFS_TIME, 4); |
| 791 | rt2x00_set_field32(®, XIFS_TIME_CFG_EIFS, erp->eifs); |
| 792 | rt2x00_set_field32(®, XIFS_TIME_CFG_BB_RXEND_ENABLE, 1); |
Bartlomiej Zolnierkiewicz | 9ca21eb | 2009-11-04 18:33:13 +0100 | [diff] [blame] | 793 | rt2800_register_write(rt2x00dev, XIFS_TIME_CFG, reg); |
Ivo van Doorn | a9b3a9f | 2009-10-15 22:04:14 +0200 | [diff] [blame] | 794 | |
Bartlomiej Zolnierkiewicz | 9ca21eb | 2009-11-04 18:33:13 +0100 | [diff] [blame] | 795 | rt2800_register_read(rt2x00dev, BCN_TIME_CFG, ®); |
Ivo van Doorn | a9b3a9f | 2009-10-15 22:04:14 +0200 | [diff] [blame] | 796 | rt2x00_set_field32(®, BCN_TIME_CFG_BEACON_INTERVAL, |
| 797 | erp->beacon_int * 16); |
Bartlomiej Zolnierkiewicz | 9ca21eb | 2009-11-04 18:33:13 +0100 | [diff] [blame] | 798 | rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg); |
Ivo van Doorn | a9b3a9f | 2009-10-15 22:04:14 +0200 | [diff] [blame] | 799 | } |
| 800 | |
| 801 | static void rt2800pci_config_ant(struct rt2x00_dev *rt2x00dev, |
| 802 | struct antenna_setup *ant) |
| 803 | { |
| 804 | u8 r1; |
| 805 | u8 r3; |
| 806 | |
Bartlomiej Zolnierkiewicz | 3e2c9df | 2009-11-04 18:33:57 +0100 | [diff] [blame] | 807 | rt2800_bbp_read(rt2x00dev, 1, &r1); |
| 808 | rt2800_bbp_read(rt2x00dev, 3, &r3); |
Ivo van Doorn | a9b3a9f | 2009-10-15 22:04:14 +0200 | [diff] [blame] | 809 | |
| 810 | /* |
| 811 | * Configure the TX antenna. |
| 812 | */ |
| 813 | switch ((int)ant->tx) { |
| 814 | case 1: |
| 815 | rt2x00_set_field8(&r1, BBP1_TX_ANTENNA, 0); |
| 816 | rt2x00_set_field8(&r3, BBP3_RX_ANTENNA, 0); |
| 817 | break; |
| 818 | case 2: |
| 819 | rt2x00_set_field8(&r1, BBP1_TX_ANTENNA, 2); |
| 820 | break; |
| 821 | case 3: |
| 822 | /* Do nothing */ |
| 823 | break; |
| 824 | } |
| 825 | |
| 826 | /* |
| 827 | * Configure the RX antenna. |
| 828 | */ |
| 829 | switch ((int)ant->rx) { |
| 830 | case 1: |
| 831 | rt2x00_set_field8(&r3, BBP3_RX_ANTENNA, 0); |
| 832 | break; |
| 833 | case 2: |
| 834 | rt2x00_set_field8(&r3, BBP3_RX_ANTENNA, 1); |
| 835 | break; |
| 836 | case 3: |
| 837 | rt2x00_set_field8(&r3, BBP3_RX_ANTENNA, 2); |
| 838 | break; |
| 839 | } |
| 840 | |
Bartlomiej Zolnierkiewicz | 3e2c9df | 2009-11-04 18:33:57 +0100 | [diff] [blame] | 841 | rt2800_bbp_write(rt2x00dev, 3, r3); |
| 842 | rt2800_bbp_write(rt2x00dev, 1, r1); |
Ivo van Doorn | a9b3a9f | 2009-10-15 22:04:14 +0200 | [diff] [blame] | 843 | } |
| 844 | |
| 845 | static void rt2800pci_config_lna_gain(struct rt2x00_dev *rt2x00dev, |
| 846 | struct rt2x00lib_conf *libconf) |
| 847 | { |
| 848 | u16 eeprom; |
| 849 | short lna_gain; |
| 850 | |
| 851 | if (libconf->rf.channel <= 14) { |
| 852 | rt2x00_eeprom_read(rt2x00dev, EEPROM_LNA, &eeprom); |
| 853 | lna_gain = rt2x00_get_field16(eeprom, EEPROM_LNA_BG); |
| 854 | } else if (libconf->rf.channel <= 64) { |
| 855 | rt2x00_eeprom_read(rt2x00dev, EEPROM_LNA, &eeprom); |
| 856 | lna_gain = rt2x00_get_field16(eeprom, EEPROM_LNA_A0); |
| 857 | } else if (libconf->rf.channel <= 128) { |
| 858 | rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_BG2, &eeprom); |
| 859 | lna_gain = rt2x00_get_field16(eeprom, EEPROM_RSSI_BG2_LNA_A1); |
| 860 | } else { |
| 861 | rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_A2, &eeprom); |
| 862 | lna_gain = rt2x00_get_field16(eeprom, EEPROM_RSSI_A2_LNA_A2); |
| 863 | } |
| 864 | |
| 865 | rt2x00dev->lna_gain = lna_gain; |
| 866 | } |
| 867 | |
| 868 | static void rt2800pci_config_channel_rt2x(struct rt2x00_dev *rt2x00dev, |
| 869 | struct ieee80211_conf *conf, |
| 870 | struct rf_channel *rf, |
| 871 | struct channel_info *info) |
| 872 | { |
| 873 | rt2x00_set_field32(&rf->rf4, RF4_FREQ_OFFSET, rt2x00dev->freq_offset); |
| 874 | |
| 875 | if (rt2x00dev->default_ant.tx == 1) |
| 876 | rt2x00_set_field32(&rf->rf2, RF2_ANTENNA_TX1, 1); |
| 877 | |
| 878 | if (rt2x00dev->default_ant.rx == 1) { |
| 879 | rt2x00_set_field32(&rf->rf2, RF2_ANTENNA_RX1, 1); |
| 880 | rt2x00_set_field32(&rf->rf2, RF2_ANTENNA_RX2, 1); |
| 881 | } else if (rt2x00dev->default_ant.rx == 2) |
| 882 | rt2x00_set_field32(&rf->rf2, RF2_ANTENNA_RX2, 1); |
| 883 | |
| 884 | if (rf->channel > 14) { |
| 885 | /* |
| 886 | * When TX power is below 0, we should increase it by 7 to |
| 887 | * make it a positive value (Minumum value is -7). |
| 888 | * However this means that values between 0 and 7 have |
| 889 | * double meaning, and we should set a 7DBm boost flag. |
| 890 | */ |
| 891 | rt2x00_set_field32(&rf->rf3, RF3_TXPOWER_A_7DBM_BOOST, |
| 892 | (info->tx_power1 >= 0)); |
| 893 | |
| 894 | if (info->tx_power1 < 0) |
| 895 | info->tx_power1 += 7; |
| 896 | |
| 897 | rt2x00_set_field32(&rf->rf3, RF3_TXPOWER_A, |
| 898 | TXPOWER_A_TO_DEV(info->tx_power1)); |
| 899 | |
| 900 | rt2x00_set_field32(&rf->rf4, RF4_TXPOWER_A_7DBM_BOOST, |
| 901 | (info->tx_power2 >= 0)); |
| 902 | |
| 903 | if (info->tx_power2 < 0) |
| 904 | info->tx_power2 += 7; |
| 905 | |
| 906 | rt2x00_set_field32(&rf->rf4, RF4_TXPOWER_A, |
| 907 | TXPOWER_A_TO_DEV(info->tx_power2)); |
| 908 | } else { |
| 909 | rt2x00_set_field32(&rf->rf3, RF3_TXPOWER_G, |
| 910 | TXPOWER_G_TO_DEV(info->tx_power1)); |
| 911 | rt2x00_set_field32(&rf->rf4, RF4_TXPOWER_G, |
| 912 | TXPOWER_G_TO_DEV(info->tx_power2)); |
| 913 | } |
| 914 | |
| 915 | rt2x00_set_field32(&rf->rf4, RF4_HT40, conf_is_ht40(conf)); |
| 916 | |
Bartlomiej Zolnierkiewicz | ada0394 | 2009-11-04 18:34:25 +0100 | [diff] [blame] | 917 | rt2800_rf_write(rt2x00dev, 1, rf->rf1); |
| 918 | rt2800_rf_write(rt2x00dev, 2, rf->rf2); |
| 919 | rt2800_rf_write(rt2x00dev, 3, rf->rf3 & ~0x00000004); |
| 920 | rt2800_rf_write(rt2x00dev, 4, rf->rf4); |
Ivo van Doorn | a9b3a9f | 2009-10-15 22:04:14 +0200 | [diff] [blame] | 921 | |
| 922 | udelay(200); |
| 923 | |
Bartlomiej Zolnierkiewicz | ada0394 | 2009-11-04 18:34:25 +0100 | [diff] [blame] | 924 | rt2800_rf_write(rt2x00dev, 1, rf->rf1); |
| 925 | rt2800_rf_write(rt2x00dev, 2, rf->rf2); |
| 926 | rt2800_rf_write(rt2x00dev, 3, rf->rf3 | 0x00000004); |
| 927 | rt2800_rf_write(rt2x00dev, 4, rf->rf4); |
Ivo van Doorn | a9b3a9f | 2009-10-15 22:04:14 +0200 | [diff] [blame] | 928 | |
| 929 | udelay(200); |
| 930 | |
Bartlomiej Zolnierkiewicz | ada0394 | 2009-11-04 18:34:25 +0100 | [diff] [blame] | 931 | rt2800_rf_write(rt2x00dev, 1, rf->rf1); |
| 932 | rt2800_rf_write(rt2x00dev, 2, rf->rf2); |
| 933 | rt2800_rf_write(rt2x00dev, 3, rf->rf3 & ~0x00000004); |
| 934 | rt2800_rf_write(rt2x00dev, 4, rf->rf4); |
Ivo van Doorn | a9b3a9f | 2009-10-15 22:04:14 +0200 | [diff] [blame] | 935 | } |
| 936 | |
| 937 | static void rt2800pci_config_channel_rt3x(struct rt2x00_dev *rt2x00dev, |
| 938 | struct ieee80211_conf *conf, |
| 939 | struct rf_channel *rf, |
| 940 | struct channel_info *info) |
| 941 | { |
| 942 | u8 rfcsr; |
| 943 | |
Bartlomiej Zolnierkiewicz | 1af68f7 | 2009-11-04 18:34:11 +0100 | [diff] [blame] | 944 | rt2800_rfcsr_write(rt2x00dev, 2, rf->rf1); |
| 945 | rt2800_rfcsr_write(rt2x00dev, 2, rf->rf3); |
Ivo van Doorn | a9b3a9f | 2009-10-15 22:04:14 +0200 | [diff] [blame] | 946 | |
Bartlomiej Zolnierkiewicz | 1af68f7 | 2009-11-04 18:34:11 +0100 | [diff] [blame] | 947 | rt2800_rfcsr_read(rt2x00dev, 6, &rfcsr); |
Ivo van Doorn | a9b3a9f | 2009-10-15 22:04:14 +0200 | [diff] [blame] | 948 | rt2x00_set_field8(&rfcsr, RFCSR6_R, rf->rf2); |
Bartlomiej Zolnierkiewicz | 1af68f7 | 2009-11-04 18:34:11 +0100 | [diff] [blame] | 949 | rt2800_rfcsr_write(rt2x00dev, 6, rfcsr); |
Ivo van Doorn | a9b3a9f | 2009-10-15 22:04:14 +0200 | [diff] [blame] | 950 | |
Bartlomiej Zolnierkiewicz | 1af68f7 | 2009-11-04 18:34:11 +0100 | [diff] [blame] | 951 | rt2800_rfcsr_read(rt2x00dev, 12, &rfcsr); |
Ivo van Doorn | a9b3a9f | 2009-10-15 22:04:14 +0200 | [diff] [blame] | 952 | rt2x00_set_field8(&rfcsr, RFCSR12_TX_POWER, |
| 953 | TXPOWER_G_TO_DEV(info->tx_power1)); |
Bartlomiej Zolnierkiewicz | 1af68f7 | 2009-11-04 18:34:11 +0100 | [diff] [blame] | 954 | rt2800_rfcsr_write(rt2x00dev, 12, rfcsr); |
Ivo van Doorn | a9b3a9f | 2009-10-15 22:04:14 +0200 | [diff] [blame] | 955 | |
Bartlomiej Zolnierkiewicz | 1af68f7 | 2009-11-04 18:34:11 +0100 | [diff] [blame] | 956 | rt2800_rfcsr_read(rt2x00dev, 23, &rfcsr); |
Ivo van Doorn | a9b3a9f | 2009-10-15 22:04:14 +0200 | [diff] [blame] | 957 | rt2x00_set_field8(&rfcsr, RFCSR23_FREQ_OFFSET, rt2x00dev->freq_offset); |
Bartlomiej Zolnierkiewicz | 1af68f7 | 2009-11-04 18:34:11 +0100 | [diff] [blame] | 958 | rt2800_rfcsr_write(rt2x00dev, 23, rfcsr); |
Ivo van Doorn | a9b3a9f | 2009-10-15 22:04:14 +0200 | [diff] [blame] | 959 | |
Bartlomiej Zolnierkiewicz | 1af68f7 | 2009-11-04 18:34:11 +0100 | [diff] [blame] | 960 | rt2800_rfcsr_write(rt2x00dev, 24, |
Ivo van Doorn | a9b3a9f | 2009-10-15 22:04:14 +0200 | [diff] [blame] | 961 | rt2x00dev->calibration[conf_is_ht40(conf)]); |
| 962 | |
Bartlomiej Zolnierkiewicz | 1af68f7 | 2009-11-04 18:34:11 +0100 | [diff] [blame] | 963 | rt2800_rfcsr_read(rt2x00dev, 23, &rfcsr); |
Ivo van Doorn | a9b3a9f | 2009-10-15 22:04:14 +0200 | [diff] [blame] | 964 | rt2x00_set_field8(&rfcsr, RFCSR7_RF_TUNING, 1); |
Bartlomiej Zolnierkiewicz | 1af68f7 | 2009-11-04 18:34:11 +0100 | [diff] [blame] | 965 | rt2800_rfcsr_write(rt2x00dev, 23, rfcsr); |
Ivo van Doorn | a9b3a9f | 2009-10-15 22:04:14 +0200 | [diff] [blame] | 966 | } |
| 967 | |
| 968 | static void rt2800pci_config_channel(struct rt2x00_dev *rt2x00dev, |
| 969 | struct ieee80211_conf *conf, |
| 970 | struct rf_channel *rf, |
| 971 | struct channel_info *info) |
| 972 | { |
| 973 | u32 reg; |
| 974 | unsigned int tx_pin; |
| 975 | u8 bbp; |
| 976 | |
| 977 | if (rt2x00_rev(&rt2x00dev->chip) != RT3070_VERSION) |
| 978 | rt2800pci_config_channel_rt2x(rt2x00dev, conf, rf, info); |
| 979 | else |
| 980 | rt2800pci_config_channel_rt3x(rt2x00dev, conf, rf, info); |
| 981 | |
| 982 | /* |
| 983 | * Change BBP settings |
| 984 | */ |
Bartlomiej Zolnierkiewicz | 3e2c9df | 2009-11-04 18:33:57 +0100 | [diff] [blame] | 985 | rt2800_bbp_write(rt2x00dev, 62, 0x37 - rt2x00dev->lna_gain); |
| 986 | rt2800_bbp_write(rt2x00dev, 63, 0x37 - rt2x00dev->lna_gain); |
| 987 | rt2800_bbp_write(rt2x00dev, 64, 0x37 - rt2x00dev->lna_gain); |
| 988 | rt2800_bbp_write(rt2x00dev, 86, 0); |
Ivo van Doorn | a9b3a9f | 2009-10-15 22:04:14 +0200 | [diff] [blame] | 989 | |
| 990 | if (rf->channel <= 14) { |
| 991 | if (test_bit(CONFIG_EXTERNAL_LNA_BG, &rt2x00dev->flags)) { |
Bartlomiej Zolnierkiewicz | 3e2c9df | 2009-11-04 18:33:57 +0100 | [diff] [blame] | 992 | rt2800_bbp_write(rt2x00dev, 82, 0x62); |
| 993 | rt2800_bbp_write(rt2x00dev, 75, 0x46); |
Ivo van Doorn | a9b3a9f | 2009-10-15 22:04:14 +0200 | [diff] [blame] | 994 | } else { |
Bartlomiej Zolnierkiewicz | 3e2c9df | 2009-11-04 18:33:57 +0100 | [diff] [blame] | 995 | rt2800_bbp_write(rt2x00dev, 82, 0x84); |
| 996 | rt2800_bbp_write(rt2x00dev, 75, 0x50); |
Ivo van Doorn | a9b3a9f | 2009-10-15 22:04:14 +0200 | [diff] [blame] | 997 | } |
| 998 | } else { |
Bartlomiej Zolnierkiewicz | 3e2c9df | 2009-11-04 18:33:57 +0100 | [diff] [blame] | 999 | rt2800_bbp_write(rt2x00dev, 82, 0xf2); |
Ivo van Doorn | a9b3a9f | 2009-10-15 22:04:14 +0200 | [diff] [blame] | 1000 | |
| 1001 | if (test_bit(CONFIG_EXTERNAL_LNA_A, &rt2x00dev->flags)) |
Bartlomiej Zolnierkiewicz | 3e2c9df | 2009-11-04 18:33:57 +0100 | [diff] [blame] | 1002 | rt2800_bbp_write(rt2x00dev, 75, 0x46); |
Ivo van Doorn | a9b3a9f | 2009-10-15 22:04:14 +0200 | [diff] [blame] | 1003 | else |
Bartlomiej Zolnierkiewicz | 3e2c9df | 2009-11-04 18:33:57 +0100 | [diff] [blame] | 1004 | rt2800_bbp_write(rt2x00dev, 75, 0x50); |
Ivo van Doorn | a9b3a9f | 2009-10-15 22:04:14 +0200 | [diff] [blame] | 1005 | } |
| 1006 | |
Bartlomiej Zolnierkiewicz | 9ca21eb | 2009-11-04 18:33:13 +0100 | [diff] [blame] | 1007 | rt2800_register_read(rt2x00dev, TX_BAND_CFG, ®); |
Ivo van Doorn | a9b3a9f | 2009-10-15 22:04:14 +0200 | [diff] [blame] | 1008 | rt2x00_set_field32(®, TX_BAND_CFG_HT40_PLUS, conf_is_ht40_plus(conf)); |
| 1009 | rt2x00_set_field32(®, TX_BAND_CFG_A, rf->channel > 14); |
| 1010 | rt2x00_set_field32(®, TX_BAND_CFG_BG, rf->channel <= 14); |
Bartlomiej Zolnierkiewicz | 9ca21eb | 2009-11-04 18:33:13 +0100 | [diff] [blame] | 1011 | rt2800_register_write(rt2x00dev, TX_BAND_CFG, reg); |
Ivo van Doorn | a9b3a9f | 2009-10-15 22:04:14 +0200 | [diff] [blame] | 1012 | |
| 1013 | tx_pin = 0; |
| 1014 | |
| 1015 | /* Turn on unused PA or LNA when not using 1T or 1R */ |
| 1016 | if (rt2x00dev->default_ant.tx != 1) { |
| 1017 | rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_A1_EN, 1); |
| 1018 | rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_G1_EN, 1); |
| 1019 | } |
| 1020 | |
| 1021 | /* Turn on unused PA or LNA when not using 1T or 1R */ |
| 1022 | if (rt2x00dev->default_ant.rx != 1) { |
| 1023 | rt2x00_set_field32(&tx_pin, TX_PIN_CFG_LNA_PE_A1_EN, 1); |
| 1024 | rt2x00_set_field32(&tx_pin, TX_PIN_CFG_LNA_PE_G1_EN, 1); |
| 1025 | } |
| 1026 | |
| 1027 | rt2x00_set_field32(&tx_pin, TX_PIN_CFG_LNA_PE_A0_EN, 1); |
| 1028 | rt2x00_set_field32(&tx_pin, TX_PIN_CFG_LNA_PE_G0_EN, 1); |
| 1029 | rt2x00_set_field32(&tx_pin, TX_PIN_CFG_RFTR_EN, 1); |
| 1030 | rt2x00_set_field32(&tx_pin, TX_PIN_CFG_TRSW_EN, 1); |
| 1031 | rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_G0_EN, rf->channel <= 14); |
| 1032 | rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_A0_EN, rf->channel > 14); |
| 1033 | |
Bartlomiej Zolnierkiewicz | 9ca21eb | 2009-11-04 18:33:13 +0100 | [diff] [blame] | 1034 | rt2800_register_write(rt2x00dev, TX_PIN_CFG, tx_pin); |
Ivo van Doorn | a9b3a9f | 2009-10-15 22:04:14 +0200 | [diff] [blame] | 1035 | |
Bartlomiej Zolnierkiewicz | 3e2c9df | 2009-11-04 18:33:57 +0100 | [diff] [blame] | 1036 | rt2800_bbp_read(rt2x00dev, 4, &bbp); |
Ivo van Doorn | a9b3a9f | 2009-10-15 22:04:14 +0200 | [diff] [blame] | 1037 | rt2x00_set_field8(&bbp, BBP4_BANDWIDTH, 2 * conf_is_ht40(conf)); |
Bartlomiej Zolnierkiewicz | 3e2c9df | 2009-11-04 18:33:57 +0100 | [diff] [blame] | 1038 | rt2800_bbp_write(rt2x00dev, 4, bbp); |
Ivo van Doorn | a9b3a9f | 2009-10-15 22:04:14 +0200 | [diff] [blame] | 1039 | |
Bartlomiej Zolnierkiewicz | 3e2c9df | 2009-11-04 18:33:57 +0100 | [diff] [blame] | 1040 | rt2800_bbp_read(rt2x00dev, 3, &bbp); |
Ivo van Doorn | a9b3a9f | 2009-10-15 22:04:14 +0200 | [diff] [blame] | 1041 | rt2x00_set_field8(&bbp, BBP3_HT40_PLUS, conf_is_ht40_plus(conf)); |
Bartlomiej Zolnierkiewicz | 3e2c9df | 2009-11-04 18:33:57 +0100 | [diff] [blame] | 1042 | rt2800_bbp_write(rt2x00dev, 3, bbp); |
Ivo van Doorn | a9b3a9f | 2009-10-15 22:04:14 +0200 | [diff] [blame] | 1043 | |
| 1044 | if (rt2x00_rev(&rt2x00dev->chip) == RT2860C_VERSION) { |
| 1045 | if (conf_is_ht40(conf)) { |
Bartlomiej Zolnierkiewicz | 3e2c9df | 2009-11-04 18:33:57 +0100 | [diff] [blame] | 1046 | rt2800_bbp_write(rt2x00dev, 69, 0x1a); |
| 1047 | rt2800_bbp_write(rt2x00dev, 70, 0x0a); |
| 1048 | rt2800_bbp_write(rt2x00dev, 73, 0x16); |
Ivo van Doorn | a9b3a9f | 2009-10-15 22:04:14 +0200 | [diff] [blame] | 1049 | } else { |
Bartlomiej Zolnierkiewicz | 3e2c9df | 2009-11-04 18:33:57 +0100 | [diff] [blame] | 1050 | rt2800_bbp_write(rt2x00dev, 69, 0x16); |
| 1051 | rt2800_bbp_write(rt2x00dev, 70, 0x08); |
| 1052 | rt2800_bbp_write(rt2x00dev, 73, 0x11); |
Ivo van Doorn | a9b3a9f | 2009-10-15 22:04:14 +0200 | [diff] [blame] | 1053 | } |
| 1054 | } |
| 1055 | |
| 1056 | msleep(1); |
| 1057 | } |
| 1058 | |
| 1059 | static void rt2800pci_config_txpower(struct rt2x00_dev *rt2x00dev, |
| 1060 | const int txpower) |
| 1061 | { |
| 1062 | u32 reg; |
| 1063 | u32 value = TXPOWER_G_TO_DEV(txpower); |
| 1064 | u8 r1; |
| 1065 | |
Bartlomiej Zolnierkiewicz | 3e2c9df | 2009-11-04 18:33:57 +0100 | [diff] [blame] | 1066 | rt2800_bbp_read(rt2x00dev, 1, &r1); |
Ivo van Doorn | a9b3a9f | 2009-10-15 22:04:14 +0200 | [diff] [blame] | 1067 | rt2x00_set_field8(®, BBP1_TX_POWER, 0); |
Bartlomiej Zolnierkiewicz | 3e2c9df | 2009-11-04 18:33:57 +0100 | [diff] [blame] | 1068 | rt2800_bbp_write(rt2x00dev, 1, r1); |
Ivo van Doorn | a9b3a9f | 2009-10-15 22:04:14 +0200 | [diff] [blame] | 1069 | |
Bartlomiej Zolnierkiewicz | 9ca21eb | 2009-11-04 18:33:13 +0100 | [diff] [blame] | 1070 | rt2800_register_read(rt2x00dev, TX_PWR_CFG_0, ®); |
Ivo van Doorn | a9b3a9f | 2009-10-15 22:04:14 +0200 | [diff] [blame] | 1071 | rt2x00_set_field32(®, TX_PWR_CFG_0_1MBS, value); |
| 1072 | rt2x00_set_field32(®, TX_PWR_CFG_0_2MBS, value); |
| 1073 | rt2x00_set_field32(®, TX_PWR_CFG_0_55MBS, value); |
| 1074 | rt2x00_set_field32(®, TX_PWR_CFG_0_11MBS, value); |
| 1075 | rt2x00_set_field32(®, TX_PWR_CFG_0_6MBS, value); |
| 1076 | rt2x00_set_field32(®, TX_PWR_CFG_0_9MBS, value); |
| 1077 | rt2x00_set_field32(®, TX_PWR_CFG_0_12MBS, value); |
| 1078 | rt2x00_set_field32(®, TX_PWR_CFG_0_18MBS, value); |
Bartlomiej Zolnierkiewicz | 9ca21eb | 2009-11-04 18:33:13 +0100 | [diff] [blame] | 1079 | rt2800_register_write(rt2x00dev, TX_PWR_CFG_0, reg); |
Ivo van Doorn | a9b3a9f | 2009-10-15 22:04:14 +0200 | [diff] [blame] | 1080 | |
Bartlomiej Zolnierkiewicz | 9ca21eb | 2009-11-04 18:33:13 +0100 | [diff] [blame] | 1081 | rt2800_register_read(rt2x00dev, TX_PWR_CFG_1, ®); |
Ivo van Doorn | a9b3a9f | 2009-10-15 22:04:14 +0200 | [diff] [blame] | 1082 | rt2x00_set_field32(®, TX_PWR_CFG_1_24MBS, value); |
| 1083 | rt2x00_set_field32(®, TX_PWR_CFG_1_36MBS, value); |
| 1084 | rt2x00_set_field32(®, TX_PWR_CFG_1_48MBS, value); |
| 1085 | rt2x00_set_field32(®, TX_PWR_CFG_1_54MBS, value); |
| 1086 | rt2x00_set_field32(®, TX_PWR_CFG_1_MCS0, value); |
| 1087 | rt2x00_set_field32(®, TX_PWR_CFG_1_MCS1, value); |
| 1088 | rt2x00_set_field32(®, TX_PWR_CFG_1_MCS2, value); |
| 1089 | rt2x00_set_field32(®, TX_PWR_CFG_1_MCS3, value); |
Bartlomiej Zolnierkiewicz | 9ca21eb | 2009-11-04 18:33:13 +0100 | [diff] [blame] | 1090 | rt2800_register_write(rt2x00dev, TX_PWR_CFG_1, reg); |
Ivo van Doorn | a9b3a9f | 2009-10-15 22:04:14 +0200 | [diff] [blame] | 1091 | |
Bartlomiej Zolnierkiewicz | 9ca21eb | 2009-11-04 18:33:13 +0100 | [diff] [blame] | 1092 | rt2800_register_read(rt2x00dev, TX_PWR_CFG_2, ®); |
Ivo van Doorn | a9b3a9f | 2009-10-15 22:04:14 +0200 | [diff] [blame] | 1093 | rt2x00_set_field32(®, TX_PWR_CFG_2_MCS4, value); |
| 1094 | rt2x00_set_field32(®, TX_PWR_CFG_2_MCS5, value); |
| 1095 | rt2x00_set_field32(®, TX_PWR_CFG_2_MCS6, value); |
| 1096 | rt2x00_set_field32(®, TX_PWR_CFG_2_MCS7, value); |
| 1097 | rt2x00_set_field32(®, TX_PWR_CFG_2_MCS8, value); |
| 1098 | rt2x00_set_field32(®, TX_PWR_CFG_2_MCS9, value); |
| 1099 | rt2x00_set_field32(®, TX_PWR_CFG_2_MCS10, value); |
| 1100 | rt2x00_set_field32(®, TX_PWR_CFG_2_MCS11, value); |
Bartlomiej Zolnierkiewicz | 9ca21eb | 2009-11-04 18:33:13 +0100 | [diff] [blame] | 1101 | rt2800_register_write(rt2x00dev, TX_PWR_CFG_2, reg); |
Ivo van Doorn | a9b3a9f | 2009-10-15 22:04:14 +0200 | [diff] [blame] | 1102 | |
Bartlomiej Zolnierkiewicz | 9ca21eb | 2009-11-04 18:33:13 +0100 | [diff] [blame] | 1103 | rt2800_register_read(rt2x00dev, TX_PWR_CFG_3, ®); |
Ivo van Doorn | a9b3a9f | 2009-10-15 22:04:14 +0200 | [diff] [blame] | 1104 | rt2x00_set_field32(®, TX_PWR_CFG_3_MCS12, value); |
| 1105 | rt2x00_set_field32(®, TX_PWR_CFG_3_MCS13, value); |
| 1106 | rt2x00_set_field32(®, TX_PWR_CFG_3_MCS14, value); |
| 1107 | rt2x00_set_field32(®, TX_PWR_CFG_3_MCS15, value); |
| 1108 | rt2x00_set_field32(®, TX_PWR_CFG_3_UKNOWN1, value); |
| 1109 | rt2x00_set_field32(®, TX_PWR_CFG_3_UKNOWN2, value); |
| 1110 | rt2x00_set_field32(®, TX_PWR_CFG_3_UKNOWN3, value); |
| 1111 | rt2x00_set_field32(®, TX_PWR_CFG_3_UKNOWN4, value); |
Bartlomiej Zolnierkiewicz | 9ca21eb | 2009-11-04 18:33:13 +0100 | [diff] [blame] | 1112 | rt2800_register_write(rt2x00dev, TX_PWR_CFG_3, reg); |
Ivo van Doorn | a9b3a9f | 2009-10-15 22:04:14 +0200 | [diff] [blame] | 1113 | |
Bartlomiej Zolnierkiewicz | 9ca21eb | 2009-11-04 18:33:13 +0100 | [diff] [blame] | 1114 | rt2800_register_read(rt2x00dev, TX_PWR_CFG_4, ®); |
Ivo van Doorn | a9b3a9f | 2009-10-15 22:04:14 +0200 | [diff] [blame] | 1115 | rt2x00_set_field32(®, TX_PWR_CFG_4_UKNOWN5, value); |
| 1116 | rt2x00_set_field32(®, TX_PWR_CFG_4_UKNOWN6, value); |
| 1117 | rt2x00_set_field32(®, TX_PWR_CFG_4_UKNOWN7, value); |
| 1118 | rt2x00_set_field32(®, TX_PWR_CFG_4_UKNOWN8, value); |
Bartlomiej Zolnierkiewicz | 9ca21eb | 2009-11-04 18:33:13 +0100 | [diff] [blame] | 1119 | rt2800_register_write(rt2x00dev, TX_PWR_CFG_4, reg); |
Ivo van Doorn | a9b3a9f | 2009-10-15 22:04:14 +0200 | [diff] [blame] | 1120 | } |
| 1121 | |
| 1122 | static void rt2800pci_config_retry_limit(struct rt2x00_dev *rt2x00dev, |
| 1123 | struct rt2x00lib_conf *libconf) |
| 1124 | { |
| 1125 | u32 reg; |
| 1126 | |
Bartlomiej Zolnierkiewicz | 9ca21eb | 2009-11-04 18:33:13 +0100 | [diff] [blame] | 1127 | rt2800_register_read(rt2x00dev, TX_RTY_CFG, ®); |
Ivo van Doorn | a9b3a9f | 2009-10-15 22:04:14 +0200 | [diff] [blame] | 1128 | rt2x00_set_field32(®, TX_RTY_CFG_SHORT_RTY_LIMIT, |
| 1129 | libconf->conf->short_frame_max_tx_count); |
| 1130 | rt2x00_set_field32(®, TX_RTY_CFG_LONG_RTY_LIMIT, |
| 1131 | libconf->conf->long_frame_max_tx_count); |
| 1132 | rt2x00_set_field32(®, TX_RTY_CFG_LONG_RTY_THRE, 2000); |
| 1133 | rt2x00_set_field32(®, TX_RTY_CFG_NON_AGG_RTY_MODE, 0); |
| 1134 | rt2x00_set_field32(®, TX_RTY_CFG_AGG_RTY_MODE, 0); |
| 1135 | rt2x00_set_field32(®, TX_RTY_CFG_TX_AUTO_FB_ENABLE, 1); |
Bartlomiej Zolnierkiewicz | 9ca21eb | 2009-11-04 18:33:13 +0100 | [diff] [blame] | 1136 | rt2800_register_write(rt2x00dev, TX_RTY_CFG, reg); |
Ivo van Doorn | a9b3a9f | 2009-10-15 22:04:14 +0200 | [diff] [blame] | 1137 | } |
| 1138 | |
| 1139 | static void rt2800pci_config_ps(struct rt2x00_dev *rt2x00dev, |
| 1140 | struct rt2x00lib_conf *libconf) |
| 1141 | { |
| 1142 | enum dev_state state = |
| 1143 | (libconf->conf->flags & IEEE80211_CONF_PS) ? |
| 1144 | STATE_SLEEP : STATE_AWAKE; |
| 1145 | u32 reg; |
| 1146 | |
| 1147 | if (state == STATE_SLEEP) { |
Bartlomiej Zolnierkiewicz | 9ca21eb | 2009-11-04 18:33:13 +0100 | [diff] [blame] | 1148 | rt2800_register_write(rt2x00dev, AUTOWAKEUP_CFG, 0); |
Ivo van Doorn | a9b3a9f | 2009-10-15 22:04:14 +0200 | [diff] [blame] | 1149 | |
Bartlomiej Zolnierkiewicz | 9ca21eb | 2009-11-04 18:33:13 +0100 | [diff] [blame] | 1150 | rt2800_register_read(rt2x00dev, AUTOWAKEUP_CFG, ®); |
Ivo van Doorn | a9b3a9f | 2009-10-15 22:04:14 +0200 | [diff] [blame] | 1151 | rt2x00_set_field32(®, AUTOWAKEUP_CFG_AUTO_LEAD_TIME, 5); |
| 1152 | rt2x00_set_field32(®, AUTOWAKEUP_CFG_TBCN_BEFORE_WAKE, |
| 1153 | libconf->conf->listen_interval - 1); |
| 1154 | rt2x00_set_field32(®, AUTOWAKEUP_CFG_AUTOWAKE, 1); |
Bartlomiej Zolnierkiewicz | 9ca21eb | 2009-11-04 18:33:13 +0100 | [diff] [blame] | 1155 | rt2800_register_write(rt2x00dev, AUTOWAKEUP_CFG, reg); |
Ivo van Doorn | a9b3a9f | 2009-10-15 22:04:14 +0200 | [diff] [blame] | 1156 | |
| 1157 | rt2x00dev->ops->lib->set_device_state(rt2x00dev, state); |
| 1158 | } else { |
| 1159 | rt2x00dev->ops->lib->set_device_state(rt2x00dev, state); |
| 1160 | |
Bartlomiej Zolnierkiewicz | 9ca21eb | 2009-11-04 18:33:13 +0100 | [diff] [blame] | 1161 | rt2800_register_read(rt2x00dev, AUTOWAKEUP_CFG, ®); |
Ivo van Doorn | a9b3a9f | 2009-10-15 22:04:14 +0200 | [diff] [blame] | 1162 | rt2x00_set_field32(®, AUTOWAKEUP_CFG_AUTO_LEAD_TIME, 0); |
| 1163 | rt2x00_set_field32(®, AUTOWAKEUP_CFG_TBCN_BEFORE_WAKE, 0); |
| 1164 | rt2x00_set_field32(®, AUTOWAKEUP_CFG_AUTOWAKE, 0); |
Bartlomiej Zolnierkiewicz | 9ca21eb | 2009-11-04 18:33:13 +0100 | [diff] [blame] | 1165 | rt2800_register_write(rt2x00dev, AUTOWAKEUP_CFG, reg); |
Ivo van Doorn | a9b3a9f | 2009-10-15 22:04:14 +0200 | [diff] [blame] | 1166 | } |
| 1167 | } |
| 1168 | |
| 1169 | static void rt2800pci_config(struct rt2x00_dev *rt2x00dev, |
| 1170 | struct rt2x00lib_conf *libconf, |
| 1171 | const unsigned int flags) |
| 1172 | { |
| 1173 | /* Always recalculate LNA gain before changing configuration */ |
| 1174 | rt2800pci_config_lna_gain(rt2x00dev, libconf); |
| 1175 | |
| 1176 | if (flags & IEEE80211_CONF_CHANGE_CHANNEL) |
| 1177 | rt2800pci_config_channel(rt2x00dev, libconf->conf, |
| 1178 | &libconf->rf, &libconf->channel); |
| 1179 | if (flags & IEEE80211_CONF_CHANGE_POWER) |
| 1180 | rt2800pci_config_txpower(rt2x00dev, libconf->conf->power_level); |
| 1181 | if (flags & IEEE80211_CONF_CHANGE_RETRY_LIMITS) |
| 1182 | rt2800pci_config_retry_limit(rt2x00dev, libconf); |
| 1183 | if (flags & IEEE80211_CONF_CHANGE_PS) |
| 1184 | rt2800pci_config_ps(rt2x00dev, libconf); |
| 1185 | } |
| 1186 | |
| 1187 | /* |
| 1188 | * Link tuning |
| 1189 | */ |
| 1190 | static void rt2800pci_link_stats(struct rt2x00_dev *rt2x00dev, |
| 1191 | struct link_qual *qual) |
| 1192 | { |
| 1193 | u32 reg; |
| 1194 | |
| 1195 | /* |
| 1196 | * Update FCS error count from register. |
| 1197 | */ |
Bartlomiej Zolnierkiewicz | 9ca21eb | 2009-11-04 18:33:13 +0100 | [diff] [blame] | 1198 | rt2800_register_read(rt2x00dev, RX_STA_CNT0, ®); |
Ivo van Doorn | a9b3a9f | 2009-10-15 22:04:14 +0200 | [diff] [blame] | 1199 | qual->rx_failed = rt2x00_get_field32(reg, RX_STA_CNT0_CRC_ERR); |
| 1200 | } |
| 1201 | |
| 1202 | static u8 rt2800pci_get_default_vgc(struct rt2x00_dev *rt2x00dev) |
| 1203 | { |
| 1204 | if (rt2x00dev->curr_band == IEEE80211_BAND_2GHZ) |
| 1205 | return 0x2e + rt2x00dev->lna_gain; |
| 1206 | |
| 1207 | if (!test_bit(CONFIG_CHANNEL_HT40, &rt2x00dev->flags)) |
| 1208 | return 0x32 + (rt2x00dev->lna_gain * 5) / 3; |
| 1209 | else |
| 1210 | return 0x3a + (rt2x00dev->lna_gain * 5) / 3; |
| 1211 | } |
| 1212 | |
| 1213 | static inline void rt2800pci_set_vgc(struct rt2x00_dev *rt2x00dev, |
| 1214 | struct link_qual *qual, u8 vgc_level) |
| 1215 | { |
| 1216 | if (qual->vgc_level != vgc_level) { |
Bartlomiej Zolnierkiewicz | 3e2c9df | 2009-11-04 18:33:57 +0100 | [diff] [blame] | 1217 | rt2800_bbp_write(rt2x00dev, 66, vgc_level); |
Ivo van Doorn | a9b3a9f | 2009-10-15 22:04:14 +0200 | [diff] [blame] | 1218 | qual->vgc_level = vgc_level; |
| 1219 | qual->vgc_level_reg = vgc_level; |
| 1220 | } |
| 1221 | } |
| 1222 | |
| 1223 | static void rt2800pci_reset_tuner(struct rt2x00_dev *rt2x00dev, |
| 1224 | struct link_qual *qual) |
| 1225 | { |
| 1226 | rt2800pci_set_vgc(rt2x00dev, qual, |
| 1227 | rt2800pci_get_default_vgc(rt2x00dev)); |
| 1228 | } |
| 1229 | |
| 1230 | static void rt2800pci_link_tuner(struct rt2x00_dev *rt2x00dev, |
| 1231 | struct link_qual *qual, const u32 count) |
| 1232 | { |
| 1233 | if (rt2x00_rev(&rt2x00dev->chip) == RT2860C_VERSION) |
| 1234 | return; |
| 1235 | |
| 1236 | /* |
| 1237 | * When RSSI is better then -80 increase VGC level with 0x10 |
| 1238 | */ |
| 1239 | rt2800pci_set_vgc(rt2x00dev, qual, |
| 1240 | rt2800pci_get_default_vgc(rt2x00dev) + |
| 1241 | ((qual->rssi > -80) * 0x10)); |
| 1242 | } |
| 1243 | |
| 1244 | /* |
| 1245 | * Firmware functions |
| 1246 | */ |
| 1247 | static char *rt2800pci_get_firmware_name(struct rt2x00_dev *rt2x00dev) |
| 1248 | { |
| 1249 | return FIRMWARE_RT2860; |
| 1250 | } |
| 1251 | |
| 1252 | static int rt2800pci_check_firmware(struct rt2x00_dev *rt2x00dev, |
| 1253 | const u8 *data, const size_t len) |
| 1254 | { |
| 1255 | u16 fw_crc; |
| 1256 | u16 crc; |
| 1257 | |
| 1258 | /* |
| 1259 | * Only support 8kb firmware files. |
| 1260 | */ |
| 1261 | if (len != 8192) |
| 1262 | return FW_BAD_LENGTH; |
| 1263 | |
| 1264 | /* |
| 1265 | * The last 2 bytes in the firmware array are the crc checksum itself, |
| 1266 | * this means that we should never pass those 2 bytes to the crc |
| 1267 | * algorithm. |
| 1268 | */ |
| 1269 | fw_crc = (data[len - 2] << 8 | data[len - 1]); |
| 1270 | |
| 1271 | /* |
| 1272 | * Use the crc ccitt algorithm. |
| 1273 | * This will return the same value as the legacy driver which |
| 1274 | * used bit ordering reversion on the both the firmware bytes |
| 1275 | * before input input as well as on the final output. |
| 1276 | * Obviously using crc ccitt directly is much more efficient. |
| 1277 | */ |
| 1278 | crc = crc_ccitt(~0, data, len - 2); |
| 1279 | |
| 1280 | /* |
| 1281 | * There is a small difference between the crc-itu-t + bitrev and |
| 1282 | * the crc-ccitt crc calculation. In the latter method the 2 bytes |
| 1283 | * will be swapped, use swab16 to convert the crc to the correct |
| 1284 | * value. |
| 1285 | */ |
| 1286 | crc = swab16(crc); |
| 1287 | |
| 1288 | return (fw_crc == crc) ? FW_OK : FW_BAD_CRC; |
| 1289 | } |
| 1290 | |
| 1291 | static int rt2800pci_load_firmware(struct rt2x00_dev *rt2x00dev, |
| 1292 | const u8 *data, const size_t len) |
| 1293 | { |
| 1294 | unsigned int i; |
| 1295 | u32 reg; |
| 1296 | |
| 1297 | /* |
| 1298 | * Wait for stable hardware. |
| 1299 | */ |
| 1300 | for (i = 0; i < REGISTER_BUSY_COUNT; i++) { |
Bartlomiej Zolnierkiewicz | 9ca21eb | 2009-11-04 18:33:13 +0100 | [diff] [blame] | 1301 | rt2800_register_read(rt2x00dev, MAC_CSR0, ®); |
Ivo van Doorn | a9b3a9f | 2009-10-15 22:04:14 +0200 | [diff] [blame] | 1302 | if (reg && reg != ~0) |
| 1303 | break; |
| 1304 | msleep(1); |
| 1305 | } |
| 1306 | |
| 1307 | if (i == REGISTER_BUSY_COUNT) { |
| 1308 | ERROR(rt2x00dev, "Unstable hardware.\n"); |
| 1309 | return -EBUSY; |
| 1310 | } |
| 1311 | |
Bartlomiej Zolnierkiewicz | 9ca21eb | 2009-11-04 18:33:13 +0100 | [diff] [blame] | 1312 | rt2800_register_write(rt2x00dev, PWR_PIN_CFG, 0x00000002); |
| 1313 | rt2800_register_write(rt2x00dev, AUTOWAKEUP_CFG, 0x00000000); |
Ivo van Doorn | a9b3a9f | 2009-10-15 22:04:14 +0200 | [diff] [blame] | 1314 | |
| 1315 | /* |
| 1316 | * Disable DMA, will be reenabled later when enabling |
| 1317 | * the radio. |
| 1318 | */ |
Bartlomiej Zolnierkiewicz | 9ca21eb | 2009-11-04 18:33:13 +0100 | [diff] [blame] | 1319 | rt2800_register_read(rt2x00dev, WPDMA_GLO_CFG, ®); |
Ivo van Doorn | a9b3a9f | 2009-10-15 22:04:14 +0200 | [diff] [blame] | 1320 | rt2x00_set_field32(®, WPDMA_GLO_CFG_ENABLE_TX_DMA, 0); |
| 1321 | rt2x00_set_field32(®, WPDMA_GLO_CFG_TX_DMA_BUSY, 0); |
| 1322 | rt2x00_set_field32(®, WPDMA_GLO_CFG_ENABLE_RX_DMA, 0); |
| 1323 | rt2x00_set_field32(®, WPDMA_GLO_CFG_RX_DMA_BUSY, 0); |
| 1324 | rt2x00_set_field32(®, WPDMA_GLO_CFG_TX_WRITEBACK_DONE, 1); |
Bartlomiej Zolnierkiewicz | 9ca21eb | 2009-11-04 18:33:13 +0100 | [diff] [blame] | 1325 | rt2800_register_write(rt2x00dev, WPDMA_GLO_CFG, reg); |
Ivo van Doorn | a9b3a9f | 2009-10-15 22:04:14 +0200 | [diff] [blame] | 1326 | |
| 1327 | /* |
| 1328 | * enable Host program ram write selection |
| 1329 | */ |
| 1330 | reg = 0; |
| 1331 | rt2x00_set_field32(®, PBF_SYS_CTRL_HOST_RAM_WRITE, 1); |
Bartlomiej Zolnierkiewicz | 9ca21eb | 2009-11-04 18:33:13 +0100 | [diff] [blame] | 1332 | rt2800_register_write(rt2x00dev, PBF_SYS_CTRL, reg); |
Ivo van Doorn | a9b3a9f | 2009-10-15 22:04:14 +0200 | [diff] [blame] | 1333 | |
| 1334 | /* |
| 1335 | * Write firmware to device. |
| 1336 | */ |
Bartlomiej Zolnierkiewicz | 4f2732c | 2009-11-04 18:33:27 +0100 | [diff] [blame] | 1337 | rt2800_register_multiwrite(rt2x00dev, FIRMWARE_IMAGE_BASE, |
Ivo van Doorn | a9b3a9f | 2009-10-15 22:04:14 +0200 | [diff] [blame] | 1338 | data, len); |
| 1339 | |
Bartlomiej Zolnierkiewicz | 9ca21eb | 2009-11-04 18:33:13 +0100 | [diff] [blame] | 1340 | rt2800_register_write(rt2x00dev, PBF_SYS_CTRL, 0x00000); |
| 1341 | rt2800_register_write(rt2x00dev, PBF_SYS_CTRL, 0x00001); |
Ivo van Doorn | a9b3a9f | 2009-10-15 22:04:14 +0200 | [diff] [blame] | 1342 | |
| 1343 | /* |
| 1344 | * Wait for device to stabilize. |
| 1345 | */ |
| 1346 | for (i = 0; i < REGISTER_BUSY_COUNT; i++) { |
Bartlomiej Zolnierkiewicz | 9ca21eb | 2009-11-04 18:33:13 +0100 | [diff] [blame] | 1347 | rt2800_register_read(rt2x00dev, PBF_SYS_CTRL, ®); |
Ivo van Doorn | a9b3a9f | 2009-10-15 22:04:14 +0200 | [diff] [blame] | 1348 | if (rt2x00_get_field32(reg, PBF_SYS_CTRL_READY)) |
| 1349 | break; |
| 1350 | msleep(1); |
| 1351 | } |
| 1352 | |
| 1353 | if (i == REGISTER_BUSY_COUNT) { |
| 1354 | ERROR(rt2x00dev, "PBF system register not ready.\n"); |
| 1355 | return -EBUSY; |
| 1356 | } |
| 1357 | |
| 1358 | /* |
| 1359 | * Disable interrupts |
| 1360 | */ |
| 1361 | rt2x00dev->ops->lib->set_device_state(rt2x00dev, STATE_RADIO_IRQ_OFF); |
| 1362 | |
| 1363 | /* |
| 1364 | * Initialize BBP R/W access agent |
| 1365 | */ |
Bartlomiej Zolnierkiewicz | 9ca21eb | 2009-11-04 18:33:13 +0100 | [diff] [blame] | 1366 | rt2800_register_write(rt2x00dev, H2M_BBP_AGENT, 0); |
| 1367 | rt2800_register_write(rt2x00dev, H2M_MAILBOX_CSR, 0); |
Ivo van Doorn | a9b3a9f | 2009-10-15 22:04:14 +0200 | [diff] [blame] | 1368 | |
| 1369 | return 0; |
| 1370 | } |
| 1371 | |
| 1372 | /* |
| 1373 | * Initialization functions. |
| 1374 | */ |
| 1375 | static bool rt2800pci_get_entry_state(struct queue_entry *entry) |
| 1376 | { |
| 1377 | struct queue_entry_priv_pci *entry_priv = entry->priv_data; |
| 1378 | u32 word; |
| 1379 | |
| 1380 | if (entry->queue->qid == QID_RX) { |
| 1381 | rt2x00_desc_read(entry_priv->desc, 1, &word); |
| 1382 | |
| 1383 | return (!rt2x00_get_field32(word, RXD_W1_DMA_DONE)); |
| 1384 | } else { |
| 1385 | rt2x00_desc_read(entry_priv->desc, 1, &word); |
| 1386 | |
| 1387 | return (!rt2x00_get_field32(word, TXD_W1_DMA_DONE)); |
| 1388 | } |
| 1389 | } |
| 1390 | |
| 1391 | static void rt2800pci_clear_entry(struct queue_entry *entry) |
| 1392 | { |
| 1393 | struct queue_entry_priv_pci *entry_priv = entry->priv_data; |
| 1394 | struct skb_frame_desc *skbdesc = get_skb_frame_desc(entry->skb); |
| 1395 | u32 word; |
| 1396 | |
| 1397 | if (entry->queue->qid == QID_RX) { |
| 1398 | rt2x00_desc_read(entry_priv->desc, 0, &word); |
| 1399 | rt2x00_set_field32(&word, RXD_W0_SDP0, skbdesc->skb_dma); |
| 1400 | rt2x00_desc_write(entry_priv->desc, 0, word); |
| 1401 | |
| 1402 | rt2x00_desc_read(entry_priv->desc, 1, &word); |
| 1403 | rt2x00_set_field32(&word, RXD_W1_DMA_DONE, 0); |
| 1404 | rt2x00_desc_write(entry_priv->desc, 1, word); |
| 1405 | } else { |
| 1406 | rt2x00_desc_read(entry_priv->desc, 1, &word); |
| 1407 | rt2x00_set_field32(&word, TXD_W1_DMA_DONE, 1); |
| 1408 | rt2x00_desc_write(entry_priv->desc, 1, word); |
| 1409 | } |
| 1410 | } |
| 1411 | |
| 1412 | static int rt2800pci_init_queues(struct rt2x00_dev *rt2x00dev) |
| 1413 | { |
| 1414 | struct queue_entry_priv_pci *entry_priv; |
| 1415 | u32 reg; |
| 1416 | |
Bartlomiej Zolnierkiewicz | 9ca21eb | 2009-11-04 18:33:13 +0100 | [diff] [blame] | 1417 | rt2800_register_read(rt2x00dev, WPDMA_RST_IDX, ®); |
Ivo van Doorn | a9b3a9f | 2009-10-15 22:04:14 +0200 | [diff] [blame] | 1418 | rt2x00_set_field32(®, WPDMA_RST_IDX_DTX_IDX0, 1); |
| 1419 | rt2x00_set_field32(®, WPDMA_RST_IDX_DTX_IDX1, 1); |
| 1420 | rt2x00_set_field32(®, WPDMA_RST_IDX_DTX_IDX2, 1); |
| 1421 | rt2x00_set_field32(®, WPDMA_RST_IDX_DTX_IDX3, 1); |
| 1422 | rt2x00_set_field32(®, WPDMA_RST_IDX_DTX_IDX4, 1); |
| 1423 | rt2x00_set_field32(®, WPDMA_RST_IDX_DTX_IDX5, 1); |
| 1424 | rt2x00_set_field32(®, WPDMA_RST_IDX_DRX_IDX0, 1); |
Bartlomiej Zolnierkiewicz | 9ca21eb | 2009-11-04 18:33:13 +0100 | [diff] [blame] | 1425 | rt2800_register_write(rt2x00dev, WPDMA_RST_IDX, reg); |
Ivo van Doorn | a9b3a9f | 2009-10-15 22:04:14 +0200 | [diff] [blame] | 1426 | |
Bartlomiej Zolnierkiewicz | 9ca21eb | 2009-11-04 18:33:13 +0100 | [diff] [blame] | 1427 | rt2800_register_write(rt2x00dev, PBF_SYS_CTRL, 0x00000e1f); |
| 1428 | rt2800_register_write(rt2x00dev, PBF_SYS_CTRL, 0x00000e00); |
Ivo van Doorn | a9b3a9f | 2009-10-15 22:04:14 +0200 | [diff] [blame] | 1429 | |
| 1430 | /* |
| 1431 | * Initialize registers. |
| 1432 | */ |
| 1433 | entry_priv = rt2x00dev->tx[0].entries[0].priv_data; |
Bartlomiej Zolnierkiewicz | 9ca21eb | 2009-11-04 18:33:13 +0100 | [diff] [blame] | 1434 | rt2800_register_write(rt2x00dev, TX_BASE_PTR0, entry_priv->desc_dma); |
| 1435 | rt2800_register_write(rt2x00dev, TX_MAX_CNT0, rt2x00dev->tx[0].limit); |
| 1436 | rt2800_register_write(rt2x00dev, TX_CTX_IDX0, 0); |
| 1437 | rt2800_register_write(rt2x00dev, TX_DTX_IDX0, 0); |
Ivo van Doorn | a9b3a9f | 2009-10-15 22:04:14 +0200 | [diff] [blame] | 1438 | |
| 1439 | entry_priv = rt2x00dev->tx[1].entries[0].priv_data; |
Bartlomiej Zolnierkiewicz | 9ca21eb | 2009-11-04 18:33:13 +0100 | [diff] [blame] | 1440 | rt2800_register_write(rt2x00dev, TX_BASE_PTR1, entry_priv->desc_dma); |
| 1441 | rt2800_register_write(rt2x00dev, TX_MAX_CNT1, rt2x00dev->tx[1].limit); |
| 1442 | rt2800_register_write(rt2x00dev, TX_CTX_IDX1, 0); |
| 1443 | rt2800_register_write(rt2x00dev, TX_DTX_IDX1, 0); |
Ivo van Doorn | a9b3a9f | 2009-10-15 22:04:14 +0200 | [diff] [blame] | 1444 | |
| 1445 | entry_priv = rt2x00dev->tx[2].entries[0].priv_data; |
Bartlomiej Zolnierkiewicz | 9ca21eb | 2009-11-04 18:33:13 +0100 | [diff] [blame] | 1446 | rt2800_register_write(rt2x00dev, TX_BASE_PTR2, entry_priv->desc_dma); |
| 1447 | rt2800_register_write(rt2x00dev, TX_MAX_CNT2, rt2x00dev->tx[2].limit); |
| 1448 | rt2800_register_write(rt2x00dev, TX_CTX_IDX2, 0); |
| 1449 | rt2800_register_write(rt2x00dev, TX_DTX_IDX2, 0); |
Ivo van Doorn | a9b3a9f | 2009-10-15 22:04:14 +0200 | [diff] [blame] | 1450 | |
| 1451 | entry_priv = rt2x00dev->tx[3].entries[0].priv_data; |
Bartlomiej Zolnierkiewicz | 9ca21eb | 2009-11-04 18:33:13 +0100 | [diff] [blame] | 1452 | rt2800_register_write(rt2x00dev, TX_BASE_PTR3, entry_priv->desc_dma); |
| 1453 | rt2800_register_write(rt2x00dev, TX_MAX_CNT3, rt2x00dev->tx[3].limit); |
| 1454 | rt2800_register_write(rt2x00dev, TX_CTX_IDX3, 0); |
| 1455 | rt2800_register_write(rt2x00dev, TX_DTX_IDX3, 0); |
Ivo van Doorn | a9b3a9f | 2009-10-15 22:04:14 +0200 | [diff] [blame] | 1456 | |
| 1457 | entry_priv = rt2x00dev->rx->entries[0].priv_data; |
Bartlomiej Zolnierkiewicz | 9ca21eb | 2009-11-04 18:33:13 +0100 | [diff] [blame] | 1458 | rt2800_register_write(rt2x00dev, RX_BASE_PTR, entry_priv->desc_dma); |
| 1459 | rt2800_register_write(rt2x00dev, RX_MAX_CNT, rt2x00dev->rx[0].limit); |
| 1460 | rt2800_register_write(rt2x00dev, RX_CRX_IDX, rt2x00dev->rx[0].limit - 1); |
| 1461 | rt2800_register_write(rt2x00dev, RX_DRX_IDX, 0); |
Ivo van Doorn | a9b3a9f | 2009-10-15 22:04:14 +0200 | [diff] [blame] | 1462 | |
| 1463 | /* |
| 1464 | * Enable global DMA configuration |
| 1465 | */ |
Bartlomiej Zolnierkiewicz | 9ca21eb | 2009-11-04 18:33:13 +0100 | [diff] [blame] | 1466 | rt2800_register_read(rt2x00dev, WPDMA_GLO_CFG, ®); |
Ivo van Doorn | a9b3a9f | 2009-10-15 22:04:14 +0200 | [diff] [blame] | 1467 | rt2x00_set_field32(®, WPDMA_GLO_CFG_ENABLE_TX_DMA, 0); |
| 1468 | rt2x00_set_field32(®, WPDMA_GLO_CFG_ENABLE_RX_DMA, 0); |
| 1469 | rt2x00_set_field32(®, WPDMA_GLO_CFG_TX_WRITEBACK_DONE, 1); |
Bartlomiej Zolnierkiewicz | 9ca21eb | 2009-11-04 18:33:13 +0100 | [diff] [blame] | 1470 | rt2800_register_write(rt2x00dev, WPDMA_GLO_CFG, reg); |
Ivo van Doorn | a9b3a9f | 2009-10-15 22:04:14 +0200 | [diff] [blame] | 1471 | |
Bartlomiej Zolnierkiewicz | 9ca21eb | 2009-11-04 18:33:13 +0100 | [diff] [blame] | 1472 | rt2800_register_write(rt2x00dev, DELAY_INT_CFG, 0); |
Ivo van Doorn | a9b3a9f | 2009-10-15 22:04:14 +0200 | [diff] [blame] | 1473 | |
| 1474 | return 0; |
| 1475 | } |
| 1476 | |
| 1477 | static int rt2800pci_init_registers(struct rt2x00_dev *rt2x00dev) |
| 1478 | { |
| 1479 | u32 reg; |
| 1480 | unsigned int i; |
| 1481 | |
Bartlomiej Zolnierkiewicz | 9ca21eb | 2009-11-04 18:33:13 +0100 | [diff] [blame] | 1482 | rt2800_register_write(rt2x00dev, PWR_PIN_CFG, 0x00000003); |
Ivo van Doorn | a9b3a9f | 2009-10-15 22:04:14 +0200 | [diff] [blame] | 1483 | |
Bartlomiej Zolnierkiewicz | 9ca21eb | 2009-11-04 18:33:13 +0100 | [diff] [blame] | 1484 | rt2800_register_read(rt2x00dev, MAC_SYS_CTRL, ®); |
Ivo van Doorn | a9b3a9f | 2009-10-15 22:04:14 +0200 | [diff] [blame] | 1485 | rt2x00_set_field32(®, MAC_SYS_CTRL_RESET_CSR, 1); |
| 1486 | rt2x00_set_field32(®, MAC_SYS_CTRL_RESET_BBP, 1); |
Bartlomiej Zolnierkiewicz | 9ca21eb | 2009-11-04 18:33:13 +0100 | [diff] [blame] | 1487 | rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, reg); |
Ivo van Doorn | a9b3a9f | 2009-10-15 22:04:14 +0200 | [diff] [blame] | 1488 | |
Bartlomiej Zolnierkiewicz | 9ca21eb | 2009-11-04 18:33:13 +0100 | [diff] [blame] | 1489 | rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, 0x00000000); |
Ivo van Doorn | a9b3a9f | 2009-10-15 22:04:14 +0200 | [diff] [blame] | 1490 | |
Bartlomiej Zolnierkiewicz | 9ca21eb | 2009-11-04 18:33:13 +0100 | [diff] [blame] | 1491 | rt2800_register_read(rt2x00dev, BCN_OFFSET0, ®); |
Ivo van Doorn | a9b3a9f | 2009-10-15 22:04:14 +0200 | [diff] [blame] | 1492 | rt2x00_set_field32(®, BCN_OFFSET0_BCN0, 0xe0); /* 0x3800 */ |
| 1493 | rt2x00_set_field32(®, BCN_OFFSET0_BCN1, 0xe8); /* 0x3a00 */ |
| 1494 | rt2x00_set_field32(®, BCN_OFFSET0_BCN2, 0xf0); /* 0x3c00 */ |
| 1495 | rt2x00_set_field32(®, BCN_OFFSET0_BCN3, 0xf8); /* 0x3e00 */ |
Bartlomiej Zolnierkiewicz | 9ca21eb | 2009-11-04 18:33:13 +0100 | [diff] [blame] | 1496 | rt2800_register_write(rt2x00dev, BCN_OFFSET0, reg); |
Ivo van Doorn | a9b3a9f | 2009-10-15 22:04:14 +0200 | [diff] [blame] | 1497 | |
Bartlomiej Zolnierkiewicz | 9ca21eb | 2009-11-04 18:33:13 +0100 | [diff] [blame] | 1498 | rt2800_register_read(rt2x00dev, BCN_OFFSET1, ®); |
Ivo van Doorn | a9b3a9f | 2009-10-15 22:04:14 +0200 | [diff] [blame] | 1499 | rt2x00_set_field32(®, BCN_OFFSET1_BCN4, 0xc8); /* 0x3200 */ |
| 1500 | rt2x00_set_field32(®, BCN_OFFSET1_BCN5, 0xd0); /* 0x3400 */ |
| 1501 | rt2x00_set_field32(®, BCN_OFFSET1_BCN6, 0x77); /* 0x1dc0 */ |
| 1502 | rt2x00_set_field32(®, BCN_OFFSET1_BCN7, 0x6f); /* 0x1bc0 */ |
Bartlomiej Zolnierkiewicz | 9ca21eb | 2009-11-04 18:33:13 +0100 | [diff] [blame] | 1503 | rt2800_register_write(rt2x00dev, BCN_OFFSET1, reg); |
Ivo van Doorn | a9b3a9f | 2009-10-15 22:04:14 +0200 | [diff] [blame] | 1504 | |
Bartlomiej Zolnierkiewicz | 9ca21eb | 2009-11-04 18:33:13 +0100 | [diff] [blame] | 1505 | rt2800_register_write(rt2x00dev, LEGACY_BASIC_RATE, 0x0000013f); |
| 1506 | rt2800_register_write(rt2x00dev, HT_BASIC_RATE, 0x00008003); |
Ivo van Doorn | a9b3a9f | 2009-10-15 22:04:14 +0200 | [diff] [blame] | 1507 | |
Bartlomiej Zolnierkiewicz | 9ca21eb | 2009-11-04 18:33:13 +0100 | [diff] [blame] | 1508 | rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, 0x00000000); |
Ivo van Doorn | a9b3a9f | 2009-10-15 22:04:14 +0200 | [diff] [blame] | 1509 | |
Bartlomiej Zolnierkiewicz | 9ca21eb | 2009-11-04 18:33:13 +0100 | [diff] [blame] | 1510 | rt2800_register_read(rt2x00dev, BCN_TIME_CFG, ®); |
Ivo van Doorn | a9b3a9f | 2009-10-15 22:04:14 +0200 | [diff] [blame] | 1511 | rt2x00_set_field32(®, BCN_TIME_CFG_BEACON_INTERVAL, 0); |
| 1512 | rt2x00_set_field32(®, BCN_TIME_CFG_TSF_TICKING, 0); |
| 1513 | rt2x00_set_field32(®, BCN_TIME_CFG_TSF_SYNC, 0); |
| 1514 | rt2x00_set_field32(®, BCN_TIME_CFG_TBTT_ENABLE, 0); |
| 1515 | rt2x00_set_field32(®, BCN_TIME_CFG_BEACON_GEN, 0); |
| 1516 | rt2x00_set_field32(®, BCN_TIME_CFG_TX_TIME_COMPENSATE, 0); |
Bartlomiej Zolnierkiewicz | 9ca21eb | 2009-11-04 18:33:13 +0100 | [diff] [blame] | 1517 | rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg); |
Ivo van Doorn | a9b3a9f | 2009-10-15 22:04:14 +0200 | [diff] [blame] | 1518 | |
Bartlomiej Zolnierkiewicz | 9ca21eb | 2009-11-04 18:33:13 +0100 | [diff] [blame] | 1519 | rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000000); |
| 1520 | rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00080606); |
Ivo van Doorn | a9b3a9f | 2009-10-15 22:04:14 +0200 | [diff] [blame] | 1521 | |
Bartlomiej Zolnierkiewicz | 9ca21eb | 2009-11-04 18:33:13 +0100 | [diff] [blame] | 1522 | rt2800_register_read(rt2x00dev, TX_LINK_CFG, ®); |
Ivo van Doorn | a9b3a9f | 2009-10-15 22:04:14 +0200 | [diff] [blame] | 1523 | rt2x00_set_field32(®, TX_LINK_CFG_REMOTE_MFB_LIFETIME, 32); |
| 1524 | rt2x00_set_field32(®, TX_LINK_CFG_MFB_ENABLE, 0); |
| 1525 | rt2x00_set_field32(®, TX_LINK_CFG_REMOTE_UMFS_ENABLE, 0); |
| 1526 | rt2x00_set_field32(®, TX_LINK_CFG_TX_MRQ_EN, 0); |
| 1527 | rt2x00_set_field32(®, TX_LINK_CFG_TX_RDG_EN, 0); |
| 1528 | rt2x00_set_field32(®, TX_LINK_CFG_TX_CF_ACK_EN, 1); |
| 1529 | rt2x00_set_field32(®, TX_LINK_CFG_REMOTE_MFB, 0); |
| 1530 | rt2x00_set_field32(®, TX_LINK_CFG_REMOTE_MFS, 0); |
Bartlomiej Zolnierkiewicz | 9ca21eb | 2009-11-04 18:33:13 +0100 | [diff] [blame] | 1531 | rt2800_register_write(rt2x00dev, TX_LINK_CFG, reg); |
Ivo van Doorn | a9b3a9f | 2009-10-15 22:04:14 +0200 | [diff] [blame] | 1532 | |
Bartlomiej Zolnierkiewicz | 9ca21eb | 2009-11-04 18:33:13 +0100 | [diff] [blame] | 1533 | rt2800_register_read(rt2x00dev, TX_TIMEOUT_CFG, ®); |
Ivo van Doorn | a9b3a9f | 2009-10-15 22:04:14 +0200 | [diff] [blame] | 1534 | rt2x00_set_field32(®, TX_TIMEOUT_CFG_MPDU_LIFETIME, 9); |
| 1535 | rt2x00_set_field32(®, TX_TIMEOUT_CFG_TX_OP_TIMEOUT, 10); |
Bartlomiej Zolnierkiewicz | 9ca21eb | 2009-11-04 18:33:13 +0100 | [diff] [blame] | 1536 | rt2800_register_write(rt2x00dev, TX_TIMEOUT_CFG, reg); |
Ivo van Doorn | a9b3a9f | 2009-10-15 22:04:14 +0200 | [diff] [blame] | 1537 | |
Bartlomiej Zolnierkiewicz | 9ca21eb | 2009-11-04 18:33:13 +0100 | [diff] [blame] | 1538 | rt2800_register_read(rt2x00dev, MAX_LEN_CFG, ®); |
Ivo van Doorn | a9b3a9f | 2009-10-15 22:04:14 +0200 | [diff] [blame] | 1539 | rt2x00_set_field32(®, MAX_LEN_CFG_MAX_MPDU, AGGREGATION_SIZE); |
| 1540 | if (rt2x00_rev(&rt2x00dev->chip) >= RT2880E_VERSION && |
| 1541 | rt2x00_rev(&rt2x00dev->chip) < RT3070_VERSION) |
| 1542 | rt2x00_set_field32(®, MAX_LEN_CFG_MAX_PSDU, 2); |
| 1543 | else |
| 1544 | rt2x00_set_field32(®, MAX_LEN_CFG_MAX_PSDU, 1); |
| 1545 | rt2x00_set_field32(®, MAX_LEN_CFG_MIN_PSDU, 0); |
| 1546 | rt2x00_set_field32(®, MAX_LEN_CFG_MIN_MPDU, 0); |
Bartlomiej Zolnierkiewicz | 9ca21eb | 2009-11-04 18:33:13 +0100 | [diff] [blame] | 1547 | rt2800_register_write(rt2x00dev, MAX_LEN_CFG, reg); |
Ivo van Doorn | a9b3a9f | 2009-10-15 22:04:14 +0200 | [diff] [blame] | 1548 | |
Bartlomiej Zolnierkiewicz | 9ca21eb | 2009-11-04 18:33:13 +0100 | [diff] [blame] | 1549 | rt2800_register_write(rt2x00dev, PBF_MAX_PCNT, 0x1f3fbf9f); |
Ivo van Doorn | a9b3a9f | 2009-10-15 22:04:14 +0200 | [diff] [blame] | 1550 | |
Bartlomiej Zolnierkiewicz | 9ca21eb | 2009-11-04 18:33:13 +0100 | [diff] [blame] | 1551 | rt2800_register_read(rt2x00dev, AUTO_RSP_CFG, ®); |
Ivo van Doorn | a9b3a9f | 2009-10-15 22:04:14 +0200 | [diff] [blame] | 1552 | rt2x00_set_field32(®, AUTO_RSP_CFG_AUTORESPONDER, 1); |
| 1553 | rt2x00_set_field32(®, AUTO_RSP_CFG_CTS_40_MMODE, 0); |
| 1554 | rt2x00_set_field32(®, AUTO_RSP_CFG_CTS_40_MREF, 0); |
| 1555 | rt2x00_set_field32(®, AUTO_RSP_CFG_DUAL_CTS_EN, 0); |
| 1556 | rt2x00_set_field32(®, AUTO_RSP_CFG_ACK_CTS_PSM_BIT, 0); |
Bartlomiej Zolnierkiewicz | 9ca21eb | 2009-11-04 18:33:13 +0100 | [diff] [blame] | 1557 | rt2800_register_write(rt2x00dev, AUTO_RSP_CFG, reg); |
Ivo van Doorn | a9b3a9f | 2009-10-15 22:04:14 +0200 | [diff] [blame] | 1558 | |
Bartlomiej Zolnierkiewicz | 9ca21eb | 2009-11-04 18:33:13 +0100 | [diff] [blame] | 1559 | rt2800_register_read(rt2x00dev, CCK_PROT_CFG, ®); |
Ivo van Doorn | a9b3a9f | 2009-10-15 22:04:14 +0200 | [diff] [blame] | 1560 | rt2x00_set_field32(®, CCK_PROT_CFG_PROTECT_RATE, 8); |
| 1561 | rt2x00_set_field32(®, CCK_PROT_CFG_PROTECT_CTRL, 0); |
| 1562 | rt2x00_set_field32(®, CCK_PROT_CFG_PROTECT_NAV, 1); |
| 1563 | rt2x00_set_field32(®, CCK_PROT_CFG_TX_OP_ALLOW_CCK, 1); |
| 1564 | rt2x00_set_field32(®, CCK_PROT_CFG_TX_OP_ALLOW_OFDM, 1); |
| 1565 | rt2x00_set_field32(®, CCK_PROT_CFG_TX_OP_ALLOW_MM20, 1); |
| 1566 | rt2x00_set_field32(®, CCK_PROT_CFG_TX_OP_ALLOW_MM40, 1); |
| 1567 | rt2x00_set_field32(®, CCK_PROT_CFG_TX_OP_ALLOW_GF20, 1); |
| 1568 | rt2x00_set_field32(®, CCK_PROT_CFG_TX_OP_ALLOW_GF40, 1); |
Bartlomiej Zolnierkiewicz | 9ca21eb | 2009-11-04 18:33:13 +0100 | [diff] [blame] | 1569 | rt2800_register_write(rt2x00dev, CCK_PROT_CFG, reg); |
Ivo van Doorn | a9b3a9f | 2009-10-15 22:04:14 +0200 | [diff] [blame] | 1570 | |
Bartlomiej Zolnierkiewicz | 9ca21eb | 2009-11-04 18:33:13 +0100 | [diff] [blame] | 1571 | rt2800_register_read(rt2x00dev, OFDM_PROT_CFG, ®); |
Ivo van Doorn | a9b3a9f | 2009-10-15 22:04:14 +0200 | [diff] [blame] | 1572 | rt2x00_set_field32(®, OFDM_PROT_CFG_PROTECT_RATE, 8); |
| 1573 | rt2x00_set_field32(®, OFDM_PROT_CFG_PROTECT_CTRL, 0); |
| 1574 | rt2x00_set_field32(®, OFDM_PROT_CFG_PROTECT_NAV, 1); |
| 1575 | rt2x00_set_field32(®, OFDM_PROT_CFG_TX_OP_ALLOW_CCK, 1); |
| 1576 | rt2x00_set_field32(®, OFDM_PROT_CFG_TX_OP_ALLOW_OFDM, 1); |
| 1577 | rt2x00_set_field32(®, OFDM_PROT_CFG_TX_OP_ALLOW_MM20, 1); |
| 1578 | rt2x00_set_field32(®, OFDM_PROT_CFG_TX_OP_ALLOW_MM40, 1); |
| 1579 | rt2x00_set_field32(®, OFDM_PROT_CFG_TX_OP_ALLOW_GF20, 1); |
| 1580 | rt2x00_set_field32(®, OFDM_PROT_CFG_TX_OP_ALLOW_GF40, 1); |
Bartlomiej Zolnierkiewicz | 9ca21eb | 2009-11-04 18:33:13 +0100 | [diff] [blame] | 1581 | rt2800_register_write(rt2x00dev, OFDM_PROT_CFG, reg); |
Ivo van Doorn | a9b3a9f | 2009-10-15 22:04:14 +0200 | [diff] [blame] | 1582 | |
Bartlomiej Zolnierkiewicz | 9ca21eb | 2009-11-04 18:33:13 +0100 | [diff] [blame] | 1583 | rt2800_register_read(rt2x00dev, MM20_PROT_CFG, ®); |
Ivo van Doorn | a9b3a9f | 2009-10-15 22:04:14 +0200 | [diff] [blame] | 1584 | rt2x00_set_field32(®, MM20_PROT_CFG_PROTECT_RATE, 0x4004); |
| 1585 | rt2x00_set_field32(®, MM20_PROT_CFG_PROTECT_CTRL, 0); |
| 1586 | rt2x00_set_field32(®, MM20_PROT_CFG_PROTECT_NAV, 1); |
| 1587 | rt2x00_set_field32(®, MM20_PROT_CFG_TX_OP_ALLOW_CCK, 1); |
| 1588 | rt2x00_set_field32(®, MM20_PROT_CFG_TX_OP_ALLOW_OFDM, 1); |
| 1589 | rt2x00_set_field32(®, MM20_PROT_CFG_TX_OP_ALLOW_MM20, 1); |
| 1590 | rt2x00_set_field32(®, MM20_PROT_CFG_TX_OP_ALLOW_MM40, 0); |
| 1591 | rt2x00_set_field32(®, MM20_PROT_CFG_TX_OP_ALLOW_GF20, 1); |
| 1592 | rt2x00_set_field32(®, MM20_PROT_CFG_TX_OP_ALLOW_GF40, 0); |
Bartlomiej Zolnierkiewicz | 9ca21eb | 2009-11-04 18:33:13 +0100 | [diff] [blame] | 1593 | rt2800_register_write(rt2x00dev, MM20_PROT_CFG, reg); |
Ivo van Doorn | a9b3a9f | 2009-10-15 22:04:14 +0200 | [diff] [blame] | 1594 | |
Bartlomiej Zolnierkiewicz | 9ca21eb | 2009-11-04 18:33:13 +0100 | [diff] [blame] | 1595 | rt2800_register_read(rt2x00dev, MM40_PROT_CFG, ®); |
Ivo van Doorn | a9b3a9f | 2009-10-15 22:04:14 +0200 | [diff] [blame] | 1596 | rt2x00_set_field32(®, MM40_PROT_CFG_PROTECT_RATE, 0x4084); |
| 1597 | rt2x00_set_field32(®, MM40_PROT_CFG_PROTECT_CTRL, 0); |
| 1598 | rt2x00_set_field32(®, MM40_PROT_CFG_PROTECT_NAV, 1); |
| 1599 | rt2x00_set_field32(®, MM40_PROT_CFG_TX_OP_ALLOW_CCK, 1); |
| 1600 | rt2x00_set_field32(®, MM40_PROT_CFG_TX_OP_ALLOW_OFDM, 1); |
| 1601 | rt2x00_set_field32(®, MM40_PROT_CFG_TX_OP_ALLOW_MM20, 1); |
| 1602 | rt2x00_set_field32(®, MM40_PROT_CFG_TX_OP_ALLOW_MM40, 1); |
| 1603 | rt2x00_set_field32(®, MM40_PROT_CFG_TX_OP_ALLOW_GF20, 1); |
| 1604 | rt2x00_set_field32(®, MM40_PROT_CFG_TX_OP_ALLOW_GF40, 1); |
Bartlomiej Zolnierkiewicz | 9ca21eb | 2009-11-04 18:33:13 +0100 | [diff] [blame] | 1605 | rt2800_register_write(rt2x00dev, MM40_PROT_CFG, reg); |
Ivo van Doorn | a9b3a9f | 2009-10-15 22:04:14 +0200 | [diff] [blame] | 1606 | |
Bartlomiej Zolnierkiewicz | 9ca21eb | 2009-11-04 18:33:13 +0100 | [diff] [blame] | 1607 | rt2800_register_read(rt2x00dev, GF20_PROT_CFG, ®); |
Ivo van Doorn | a9b3a9f | 2009-10-15 22:04:14 +0200 | [diff] [blame] | 1608 | rt2x00_set_field32(®, GF20_PROT_CFG_PROTECT_RATE, 0x4004); |
| 1609 | rt2x00_set_field32(®, GF20_PROT_CFG_PROTECT_CTRL, 0); |
| 1610 | rt2x00_set_field32(®, GF20_PROT_CFG_PROTECT_NAV, 1); |
| 1611 | rt2x00_set_field32(®, GF20_PROT_CFG_TX_OP_ALLOW_CCK, 1); |
| 1612 | rt2x00_set_field32(®, GF20_PROT_CFG_TX_OP_ALLOW_OFDM, 1); |
| 1613 | rt2x00_set_field32(®, GF20_PROT_CFG_TX_OP_ALLOW_MM20, 1); |
| 1614 | rt2x00_set_field32(®, GF20_PROT_CFG_TX_OP_ALLOW_MM40, 0); |
| 1615 | rt2x00_set_field32(®, GF20_PROT_CFG_TX_OP_ALLOW_GF20, 1); |
| 1616 | rt2x00_set_field32(®, GF20_PROT_CFG_TX_OP_ALLOW_GF40, 0); |
Bartlomiej Zolnierkiewicz | 9ca21eb | 2009-11-04 18:33:13 +0100 | [diff] [blame] | 1617 | rt2800_register_write(rt2x00dev, GF20_PROT_CFG, reg); |
Ivo van Doorn | a9b3a9f | 2009-10-15 22:04:14 +0200 | [diff] [blame] | 1618 | |
Bartlomiej Zolnierkiewicz | 9ca21eb | 2009-11-04 18:33:13 +0100 | [diff] [blame] | 1619 | rt2800_register_read(rt2x00dev, GF40_PROT_CFG, ®); |
Ivo van Doorn | a9b3a9f | 2009-10-15 22:04:14 +0200 | [diff] [blame] | 1620 | rt2x00_set_field32(®, GF40_PROT_CFG_PROTECT_RATE, 0x4084); |
| 1621 | rt2x00_set_field32(®, GF40_PROT_CFG_PROTECT_CTRL, 0); |
| 1622 | rt2x00_set_field32(®, GF40_PROT_CFG_PROTECT_NAV, 1); |
| 1623 | rt2x00_set_field32(®, GF40_PROT_CFG_TX_OP_ALLOW_CCK, 1); |
| 1624 | rt2x00_set_field32(®, GF40_PROT_CFG_TX_OP_ALLOW_OFDM, 1); |
| 1625 | rt2x00_set_field32(®, GF40_PROT_CFG_TX_OP_ALLOW_MM20, 1); |
| 1626 | rt2x00_set_field32(®, GF40_PROT_CFG_TX_OP_ALLOW_MM40, 1); |
| 1627 | rt2x00_set_field32(®, GF40_PROT_CFG_TX_OP_ALLOW_GF20, 1); |
| 1628 | rt2x00_set_field32(®, GF40_PROT_CFG_TX_OP_ALLOW_GF40, 1); |
Bartlomiej Zolnierkiewicz | 9ca21eb | 2009-11-04 18:33:13 +0100 | [diff] [blame] | 1629 | rt2800_register_write(rt2x00dev, GF40_PROT_CFG, reg); |
Ivo van Doorn | a9b3a9f | 2009-10-15 22:04:14 +0200 | [diff] [blame] | 1630 | |
Bartlomiej Zolnierkiewicz | 9ca21eb | 2009-11-04 18:33:13 +0100 | [diff] [blame] | 1631 | rt2800_register_write(rt2x00dev, TXOP_CTRL_CFG, 0x0000583f); |
| 1632 | rt2800_register_write(rt2x00dev, TXOP_HLDR_ET, 0x00000002); |
Ivo van Doorn | a9b3a9f | 2009-10-15 22:04:14 +0200 | [diff] [blame] | 1633 | |
Bartlomiej Zolnierkiewicz | 9ca21eb | 2009-11-04 18:33:13 +0100 | [diff] [blame] | 1634 | rt2800_register_read(rt2x00dev, TX_RTS_CFG, ®); |
Ivo van Doorn | a9b3a9f | 2009-10-15 22:04:14 +0200 | [diff] [blame] | 1635 | rt2x00_set_field32(®, TX_RTS_CFG_AUTO_RTS_RETRY_LIMIT, 32); |
| 1636 | rt2x00_set_field32(®, TX_RTS_CFG_RTS_THRES, |
| 1637 | IEEE80211_MAX_RTS_THRESHOLD); |
| 1638 | rt2x00_set_field32(®, TX_RTS_CFG_RTS_FBK_EN, 0); |
Bartlomiej Zolnierkiewicz | 9ca21eb | 2009-11-04 18:33:13 +0100 | [diff] [blame] | 1639 | rt2800_register_write(rt2x00dev, TX_RTS_CFG, reg); |
Ivo van Doorn | a9b3a9f | 2009-10-15 22:04:14 +0200 | [diff] [blame] | 1640 | |
Bartlomiej Zolnierkiewicz | 9ca21eb | 2009-11-04 18:33:13 +0100 | [diff] [blame] | 1641 | rt2800_register_write(rt2x00dev, EXP_ACK_TIME, 0x002400ca); |
| 1642 | rt2800_register_write(rt2x00dev, PWR_PIN_CFG, 0x00000003); |
Ivo van Doorn | a9b3a9f | 2009-10-15 22:04:14 +0200 | [diff] [blame] | 1643 | |
| 1644 | /* |
| 1645 | * ASIC will keep garbage value after boot, clear encryption keys. |
| 1646 | */ |
| 1647 | for (i = 0; i < 4; i++) |
Bartlomiej Zolnierkiewicz | 9ca21eb | 2009-11-04 18:33:13 +0100 | [diff] [blame] | 1648 | rt2800_register_write(rt2x00dev, |
Ivo van Doorn | a9b3a9f | 2009-10-15 22:04:14 +0200 | [diff] [blame] | 1649 | SHARED_KEY_MODE_ENTRY(i), 0); |
| 1650 | |
| 1651 | for (i = 0; i < 256; i++) { |
| 1652 | u32 wcid[2] = { 0xffffffff, 0x00ffffff }; |
Bartlomiej Zolnierkiewicz | 4f2732c | 2009-11-04 18:33:27 +0100 | [diff] [blame] | 1653 | rt2800_register_multiwrite(rt2x00dev, MAC_WCID_ENTRY(i), |
Ivo van Doorn | a9b3a9f | 2009-10-15 22:04:14 +0200 | [diff] [blame] | 1654 | wcid, sizeof(wcid)); |
| 1655 | |
Bartlomiej Zolnierkiewicz | 9ca21eb | 2009-11-04 18:33:13 +0100 | [diff] [blame] | 1656 | rt2800_register_write(rt2x00dev, MAC_WCID_ATTR_ENTRY(i), 1); |
| 1657 | rt2800_register_write(rt2x00dev, MAC_IVEIV_ENTRY(i), 0); |
Ivo van Doorn | a9b3a9f | 2009-10-15 22:04:14 +0200 | [diff] [blame] | 1658 | } |
| 1659 | |
| 1660 | /* |
| 1661 | * Clear all beacons |
| 1662 | * For the Beacon base registers we only need to clear |
| 1663 | * the first byte since that byte contains the VALID and OWNER |
| 1664 | * bits which (when set to 0) will invalidate the entire beacon. |
| 1665 | */ |
Bartlomiej Zolnierkiewicz | 9ca21eb | 2009-11-04 18:33:13 +0100 | [diff] [blame] | 1666 | rt2800_register_write(rt2x00dev, HW_BEACON_BASE0, 0); |
| 1667 | rt2800_register_write(rt2x00dev, HW_BEACON_BASE1, 0); |
| 1668 | rt2800_register_write(rt2x00dev, HW_BEACON_BASE2, 0); |
| 1669 | rt2800_register_write(rt2x00dev, HW_BEACON_BASE3, 0); |
| 1670 | rt2800_register_write(rt2x00dev, HW_BEACON_BASE4, 0); |
| 1671 | rt2800_register_write(rt2x00dev, HW_BEACON_BASE5, 0); |
| 1672 | rt2800_register_write(rt2x00dev, HW_BEACON_BASE6, 0); |
| 1673 | rt2800_register_write(rt2x00dev, HW_BEACON_BASE7, 0); |
Ivo van Doorn | a9b3a9f | 2009-10-15 22:04:14 +0200 | [diff] [blame] | 1674 | |
Bartlomiej Zolnierkiewicz | 9ca21eb | 2009-11-04 18:33:13 +0100 | [diff] [blame] | 1675 | rt2800_register_read(rt2x00dev, HT_FBK_CFG0, ®); |
Ivo van Doorn | a9b3a9f | 2009-10-15 22:04:14 +0200 | [diff] [blame] | 1676 | rt2x00_set_field32(®, HT_FBK_CFG0_HTMCS0FBK, 0); |
| 1677 | rt2x00_set_field32(®, HT_FBK_CFG0_HTMCS1FBK, 0); |
| 1678 | rt2x00_set_field32(®, HT_FBK_CFG0_HTMCS2FBK, 1); |
| 1679 | rt2x00_set_field32(®, HT_FBK_CFG0_HTMCS3FBK, 2); |
| 1680 | rt2x00_set_field32(®, HT_FBK_CFG0_HTMCS4FBK, 3); |
| 1681 | rt2x00_set_field32(®, HT_FBK_CFG0_HTMCS5FBK, 4); |
| 1682 | rt2x00_set_field32(®, HT_FBK_CFG0_HTMCS6FBK, 5); |
| 1683 | rt2x00_set_field32(®, HT_FBK_CFG0_HTMCS7FBK, 6); |
Bartlomiej Zolnierkiewicz | 9ca21eb | 2009-11-04 18:33:13 +0100 | [diff] [blame] | 1684 | rt2800_register_write(rt2x00dev, HT_FBK_CFG0, reg); |
Ivo van Doorn | a9b3a9f | 2009-10-15 22:04:14 +0200 | [diff] [blame] | 1685 | |
Bartlomiej Zolnierkiewicz | 9ca21eb | 2009-11-04 18:33:13 +0100 | [diff] [blame] | 1686 | rt2800_register_read(rt2x00dev, HT_FBK_CFG1, ®); |
Ivo van Doorn | a9b3a9f | 2009-10-15 22:04:14 +0200 | [diff] [blame] | 1687 | rt2x00_set_field32(®, HT_FBK_CFG1_HTMCS8FBK, 8); |
| 1688 | rt2x00_set_field32(®, HT_FBK_CFG1_HTMCS9FBK, 8); |
| 1689 | rt2x00_set_field32(®, HT_FBK_CFG1_HTMCS10FBK, 9); |
| 1690 | rt2x00_set_field32(®, HT_FBK_CFG1_HTMCS11FBK, 10); |
| 1691 | rt2x00_set_field32(®, HT_FBK_CFG1_HTMCS12FBK, 11); |
| 1692 | rt2x00_set_field32(®, HT_FBK_CFG1_HTMCS13FBK, 12); |
| 1693 | rt2x00_set_field32(®, HT_FBK_CFG1_HTMCS14FBK, 13); |
| 1694 | rt2x00_set_field32(®, HT_FBK_CFG1_HTMCS15FBK, 14); |
Bartlomiej Zolnierkiewicz | 9ca21eb | 2009-11-04 18:33:13 +0100 | [diff] [blame] | 1695 | rt2800_register_write(rt2x00dev, HT_FBK_CFG1, reg); |
Ivo van Doorn | a9b3a9f | 2009-10-15 22:04:14 +0200 | [diff] [blame] | 1696 | |
Bartlomiej Zolnierkiewicz | 9ca21eb | 2009-11-04 18:33:13 +0100 | [diff] [blame] | 1697 | rt2800_register_read(rt2x00dev, LG_FBK_CFG0, ®); |
Ivo van Doorn | a9b3a9f | 2009-10-15 22:04:14 +0200 | [diff] [blame] | 1698 | rt2x00_set_field32(®, LG_FBK_CFG0_OFDMMCS0FBK, 8); |
| 1699 | rt2x00_set_field32(®, LG_FBK_CFG0_OFDMMCS1FBK, 8); |
| 1700 | rt2x00_set_field32(®, LG_FBK_CFG0_OFDMMCS2FBK, 9); |
| 1701 | rt2x00_set_field32(®, LG_FBK_CFG0_OFDMMCS3FBK, 10); |
| 1702 | rt2x00_set_field32(®, LG_FBK_CFG0_OFDMMCS4FBK, 11); |
| 1703 | rt2x00_set_field32(®, LG_FBK_CFG0_OFDMMCS5FBK, 12); |
| 1704 | rt2x00_set_field32(®, LG_FBK_CFG0_OFDMMCS6FBK, 13); |
| 1705 | rt2x00_set_field32(®, LG_FBK_CFG0_OFDMMCS7FBK, 14); |
Bartlomiej Zolnierkiewicz | 9ca21eb | 2009-11-04 18:33:13 +0100 | [diff] [blame] | 1706 | rt2800_register_write(rt2x00dev, LG_FBK_CFG0, reg); |
Ivo van Doorn | a9b3a9f | 2009-10-15 22:04:14 +0200 | [diff] [blame] | 1707 | |
Bartlomiej Zolnierkiewicz | 9ca21eb | 2009-11-04 18:33:13 +0100 | [diff] [blame] | 1708 | rt2800_register_read(rt2x00dev, LG_FBK_CFG1, ®); |
Ivo van Doorn | a9b3a9f | 2009-10-15 22:04:14 +0200 | [diff] [blame] | 1709 | rt2x00_set_field32(®, LG_FBK_CFG0_CCKMCS0FBK, 0); |
| 1710 | rt2x00_set_field32(®, LG_FBK_CFG0_CCKMCS1FBK, 0); |
| 1711 | rt2x00_set_field32(®, LG_FBK_CFG0_CCKMCS2FBK, 1); |
| 1712 | rt2x00_set_field32(®, LG_FBK_CFG0_CCKMCS3FBK, 2); |
Bartlomiej Zolnierkiewicz | 9ca21eb | 2009-11-04 18:33:13 +0100 | [diff] [blame] | 1713 | rt2800_register_write(rt2x00dev, LG_FBK_CFG1, reg); |
Ivo van Doorn | a9b3a9f | 2009-10-15 22:04:14 +0200 | [diff] [blame] | 1714 | |
| 1715 | /* |
| 1716 | * We must clear the error counters. |
| 1717 | * These registers are cleared on read, |
| 1718 | * so we may pass a useless variable to store the value. |
| 1719 | */ |
Bartlomiej Zolnierkiewicz | 9ca21eb | 2009-11-04 18:33:13 +0100 | [diff] [blame] | 1720 | rt2800_register_read(rt2x00dev, RX_STA_CNT0, ®); |
| 1721 | rt2800_register_read(rt2x00dev, RX_STA_CNT1, ®); |
| 1722 | rt2800_register_read(rt2x00dev, RX_STA_CNT2, ®); |
| 1723 | rt2800_register_read(rt2x00dev, TX_STA_CNT0, ®); |
| 1724 | rt2800_register_read(rt2x00dev, TX_STA_CNT1, ®); |
| 1725 | rt2800_register_read(rt2x00dev, TX_STA_CNT2, ®); |
Ivo van Doorn | a9b3a9f | 2009-10-15 22:04:14 +0200 | [diff] [blame] | 1726 | |
| 1727 | return 0; |
| 1728 | } |
| 1729 | |
| 1730 | static int rt2800pci_wait_bbp_rf_ready(struct rt2x00_dev *rt2x00dev) |
| 1731 | { |
| 1732 | unsigned int i; |
| 1733 | u32 reg; |
| 1734 | |
| 1735 | for (i = 0; i < REGISTER_BUSY_COUNT; i++) { |
Bartlomiej Zolnierkiewicz | 9ca21eb | 2009-11-04 18:33:13 +0100 | [diff] [blame] | 1736 | rt2800_register_read(rt2x00dev, MAC_STATUS_CFG, ®); |
Ivo van Doorn | a9b3a9f | 2009-10-15 22:04:14 +0200 | [diff] [blame] | 1737 | if (!rt2x00_get_field32(reg, MAC_STATUS_CFG_BBP_RF_BUSY)) |
| 1738 | return 0; |
| 1739 | |
| 1740 | udelay(REGISTER_BUSY_DELAY); |
| 1741 | } |
| 1742 | |
| 1743 | ERROR(rt2x00dev, "BBP/RF register access failed, aborting.\n"); |
| 1744 | return -EACCES; |
| 1745 | } |
| 1746 | |
| 1747 | static int rt2800pci_wait_bbp_ready(struct rt2x00_dev *rt2x00dev) |
| 1748 | { |
| 1749 | unsigned int i; |
| 1750 | u8 value; |
| 1751 | |
| 1752 | /* |
| 1753 | * BBP was enabled after firmware was loaded, |
| 1754 | * but we need to reactivate it now. |
| 1755 | */ |
Bartlomiej Zolnierkiewicz | 9ca21eb | 2009-11-04 18:33:13 +0100 | [diff] [blame] | 1756 | rt2800_register_write(rt2x00dev, H2M_BBP_AGENT, 0); |
| 1757 | rt2800_register_write(rt2x00dev, H2M_MAILBOX_CSR, 0); |
Ivo van Doorn | a9b3a9f | 2009-10-15 22:04:14 +0200 | [diff] [blame] | 1758 | msleep(1); |
| 1759 | |
| 1760 | for (i = 0; i < REGISTER_BUSY_COUNT; i++) { |
Bartlomiej Zolnierkiewicz | 3e2c9df | 2009-11-04 18:33:57 +0100 | [diff] [blame] | 1761 | rt2800_bbp_read(rt2x00dev, 0, &value); |
Ivo van Doorn | a9b3a9f | 2009-10-15 22:04:14 +0200 | [diff] [blame] | 1762 | if ((value != 0xff) && (value != 0x00)) |
| 1763 | return 0; |
| 1764 | udelay(REGISTER_BUSY_DELAY); |
| 1765 | } |
| 1766 | |
| 1767 | ERROR(rt2x00dev, "BBP register access failed, aborting.\n"); |
| 1768 | return -EACCES; |
| 1769 | } |
| 1770 | |
| 1771 | static int rt2800pci_init_bbp(struct rt2x00_dev *rt2x00dev) |
| 1772 | { |
| 1773 | unsigned int i; |
| 1774 | u16 eeprom; |
| 1775 | u8 reg_id; |
| 1776 | u8 value; |
| 1777 | |
| 1778 | if (unlikely(rt2800pci_wait_bbp_rf_ready(rt2x00dev) || |
| 1779 | rt2800pci_wait_bbp_ready(rt2x00dev))) |
| 1780 | return -EACCES; |
| 1781 | |
Bartlomiej Zolnierkiewicz | 3e2c9df | 2009-11-04 18:33:57 +0100 | [diff] [blame] | 1782 | rt2800_bbp_write(rt2x00dev, 65, 0x2c); |
| 1783 | rt2800_bbp_write(rt2x00dev, 66, 0x38); |
| 1784 | rt2800_bbp_write(rt2x00dev, 69, 0x12); |
| 1785 | rt2800_bbp_write(rt2x00dev, 70, 0x0a); |
| 1786 | rt2800_bbp_write(rt2x00dev, 73, 0x10); |
| 1787 | rt2800_bbp_write(rt2x00dev, 81, 0x37); |
| 1788 | rt2800_bbp_write(rt2x00dev, 82, 0x62); |
| 1789 | rt2800_bbp_write(rt2x00dev, 83, 0x6a); |
| 1790 | rt2800_bbp_write(rt2x00dev, 84, 0x99); |
| 1791 | rt2800_bbp_write(rt2x00dev, 86, 0x00); |
| 1792 | rt2800_bbp_write(rt2x00dev, 91, 0x04); |
| 1793 | rt2800_bbp_write(rt2x00dev, 92, 0x00); |
| 1794 | rt2800_bbp_write(rt2x00dev, 103, 0x00); |
| 1795 | rt2800_bbp_write(rt2x00dev, 105, 0x05); |
Ivo van Doorn | a9b3a9f | 2009-10-15 22:04:14 +0200 | [diff] [blame] | 1796 | |
| 1797 | if (rt2x00_rev(&rt2x00dev->chip) == RT2860C_VERSION) { |
Bartlomiej Zolnierkiewicz | 3e2c9df | 2009-11-04 18:33:57 +0100 | [diff] [blame] | 1798 | rt2800_bbp_write(rt2x00dev, 69, 0x16); |
| 1799 | rt2800_bbp_write(rt2x00dev, 73, 0x12); |
Ivo van Doorn | a9b3a9f | 2009-10-15 22:04:14 +0200 | [diff] [blame] | 1800 | } |
| 1801 | |
| 1802 | if (rt2x00_rev(&rt2x00dev->chip) > RT2860D_VERSION) |
Bartlomiej Zolnierkiewicz | 3e2c9df | 2009-11-04 18:33:57 +0100 | [diff] [blame] | 1803 | rt2800_bbp_write(rt2x00dev, 84, 0x19); |
Ivo van Doorn | a9b3a9f | 2009-10-15 22:04:14 +0200 | [diff] [blame] | 1804 | |
| 1805 | if (rt2x00_rt(&rt2x00dev->chip, RT3052)) { |
Bartlomiej Zolnierkiewicz | 3e2c9df | 2009-11-04 18:33:57 +0100 | [diff] [blame] | 1806 | rt2800_bbp_write(rt2x00dev, 31, 0x08); |
| 1807 | rt2800_bbp_write(rt2x00dev, 78, 0x0e); |
| 1808 | rt2800_bbp_write(rt2x00dev, 80, 0x08); |
Ivo van Doorn | a9b3a9f | 2009-10-15 22:04:14 +0200 | [diff] [blame] | 1809 | } |
| 1810 | |
| 1811 | for (i = 0; i < EEPROM_BBP_SIZE; i++) { |
| 1812 | rt2x00_eeprom_read(rt2x00dev, EEPROM_BBP_START + i, &eeprom); |
| 1813 | |
| 1814 | if (eeprom != 0xffff && eeprom != 0x0000) { |
| 1815 | reg_id = rt2x00_get_field16(eeprom, EEPROM_BBP_REG_ID); |
| 1816 | value = rt2x00_get_field16(eeprom, EEPROM_BBP_VALUE); |
Bartlomiej Zolnierkiewicz | 3e2c9df | 2009-11-04 18:33:57 +0100 | [diff] [blame] | 1817 | rt2800_bbp_write(rt2x00dev, reg_id, value); |
Ivo van Doorn | a9b3a9f | 2009-10-15 22:04:14 +0200 | [diff] [blame] | 1818 | } |
| 1819 | } |
| 1820 | |
| 1821 | return 0; |
| 1822 | } |
| 1823 | |
| 1824 | static u8 rt2800pci_init_rx_filter(struct rt2x00_dev *rt2x00dev, |
| 1825 | bool bw40, u8 rfcsr24, u8 filter_target) |
| 1826 | { |
| 1827 | unsigned int i; |
| 1828 | u8 bbp; |
| 1829 | u8 rfcsr; |
| 1830 | u8 passband; |
| 1831 | u8 stopband; |
| 1832 | u8 overtuned = 0; |
| 1833 | |
Bartlomiej Zolnierkiewicz | 1af68f7 | 2009-11-04 18:34:11 +0100 | [diff] [blame] | 1834 | rt2800_rfcsr_write(rt2x00dev, 24, rfcsr24); |
Ivo van Doorn | a9b3a9f | 2009-10-15 22:04:14 +0200 | [diff] [blame] | 1835 | |
Bartlomiej Zolnierkiewicz | 3e2c9df | 2009-11-04 18:33:57 +0100 | [diff] [blame] | 1836 | rt2800_bbp_read(rt2x00dev, 4, &bbp); |
Ivo van Doorn | a9b3a9f | 2009-10-15 22:04:14 +0200 | [diff] [blame] | 1837 | rt2x00_set_field8(&bbp, BBP4_BANDWIDTH, 2 * bw40); |
Bartlomiej Zolnierkiewicz | 3e2c9df | 2009-11-04 18:33:57 +0100 | [diff] [blame] | 1838 | rt2800_bbp_write(rt2x00dev, 4, bbp); |
Ivo van Doorn | a9b3a9f | 2009-10-15 22:04:14 +0200 | [diff] [blame] | 1839 | |
Bartlomiej Zolnierkiewicz | 1af68f7 | 2009-11-04 18:34:11 +0100 | [diff] [blame] | 1840 | rt2800_rfcsr_read(rt2x00dev, 22, &rfcsr); |
Ivo van Doorn | a9b3a9f | 2009-10-15 22:04:14 +0200 | [diff] [blame] | 1841 | rt2x00_set_field8(&rfcsr, RFCSR22_BASEBAND_LOOPBACK, 1); |
Bartlomiej Zolnierkiewicz | 1af68f7 | 2009-11-04 18:34:11 +0100 | [diff] [blame] | 1842 | rt2800_rfcsr_write(rt2x00dev, 22, rfcsr); |
Ivo van Doorn | a9b3a9f | 2009-10-15 22:04:14 +0200 | [diff] [blame] | 1843 | |
| 1844 | /* |
| 1845 | * Set power & frequency of passband test tone |
| 1846 | */ |
Bartlomiej Zolnierkiewicz | 3e2c9df | 2009-11-04 18:33:57 +0100 | [diff] [blame] | 1847 | rt2800_bbp_write(rt2x00dev, 24, 0); |
Ivo van Doorn | a9b3a9f | 2009-10-15 22:04:14 +0200 | [diff] [blame] | 1848 | |
| 1849 | for (i = 0; i < 100; i++) { |
Bartlomiej Zolnierkiewicz | 3e2c9df | 2009-11-04 18:33:57 +0100 | [diff] [blame] | 1850 | rt2800_bbp_write(rt2x00dev, 25, 0x90); |
Ivo van Doorn | a9b3a9f | 2009-10-15 22:04:14 +0200 | [diff] [blame] | 1851 | msleep(1); |
| 1852 | |
Bartlomiej Zolnierkiewicz | 3e2c9df | 2009-11-04 18:33:57 +0100 | [diff] [blame] | 1853 | rt2800_bbp_read(rt2x00dev, 55, &passband); |
Ivo van Doorn | a9b3a9f | 2009-10-15 22:04:14 +0200 | [diff] [blame] | 1854 | if (passband) |
| 1855 | break; |
| 1856 | } |
| 1857 | |
| 1858 | /* |
| 1859 | * Set power & frequency of stopband test tone |
| 1860 | */ |
Bartlomiej Zolnierkiewicz | 3e2c9df | 2009-11-04 18:33:57 +0100 | [diff] [blame] | 1861 | rt2800_bbp_write(rt2x00dev, 24, 0x06); |
Ivo van Doorn | a9b3a9f | 2009-10-15 22:04:14 +0200 | [diff] [blame] | 1862 | |
| 1863 | for (i = 0; i < 100; i++) { |
Bartlomiej Zolnierkiewicz | 3e2c9df | 2009-11-04 18:33:57 +0100 | [diff] [blame] | 1864 | rt2800_bbp_write(rt2x00dev, 25, 0x90); |
Ivo van Doorn | a9b3a9f | 2009-10-15 22:04:14 +0200 | [diff] [blame] | 1865 | msleep(1); |
| 1866 | |
Bartlomiej Zolnierkiewicz | 3e2c9df | 2009-11-04 18:33:57 +0100 | [diff] [blame] | 1867 | rt2800_bbp_read(rt2x00dev, 55, &stopband); |
Ivo van Doorn | a9b3a9f | 2009-10-15 22:04:14 +0200 | [diff] [blame] | 1868 | |
| 1869 | if ((passband - stopband) <= filter_target) { |
| 1870 | rfcsr24++; |
| 1871 | overtuned += ((passband - stopband) == filter_target); |
| 1872 | } else |
| 1873 | break; |
| 1874 | |
Bartlomiej Zolnierkiewicz | 1af68f7 | 2009-11-04 18:34:11 +0100 | [diff] [blame] | 1875 | rt2800_rfcsr_write(rt2x00dev, 24, rfcsr24); |
Ivo van Doorn | a9b3a9f | 2009-10-15 22:04:14 +0200 | [diff] [blame] | 1876 | } |
| 1877 | |
| 1878 | rfcsr24 -= !!overtuned; |
| 1879 | |
Bartlomiej Zolnierkiewicz | 1af68f7 | 2009-11-04 18:34:11 +0100 | [diff] [blame] | 1880 | rt2800_rfcsr_write(rt2x00dev, 24, rfcsr24); |
Ivo van Doorn | a9b3a9f | 2009-10-15 22:04:14 +0200 | [diff] [blame] | 1881 | return rfcsr24; |
| 1882 | } |
| 1883 | |
| 1884 | static int rt2800pci_init_rfcsr(struct rt2x00_dev *rt2x00dev) |
| 1885 | { |
| 1886 | u8 rfcsr; |
| 1887 | u8 bbp; |
| 1888 | |
| 1889 | if (!rt2x00_rf(&rt2x00dev->chip, RF3020) && |
| 1890 | !rt2x00_rf(&rt2x00dev->chip, RF3021) && |
| 1891 | !rt2x00_rf(&rt2x00dev->chip, RF3022)) |
| 1892 | return 0; |
| 1893 | |
| 1894 | /* |
| 1895 | * Init RF calibration. |
| 1896 | */ |
Bartlomiej Zolnierkiewicz | 1af68f7 | 2009-11-04 18:34:11 +0100 | [diff] [blame] | 1897 | rt2800_rfcsr_read(rt2x00dev, 30, &rfcsr); |
Ivo van Doorn | a9b3a9f | 2009-10-15 22:04:14 +0200 | [diff] [blame] | 1898 | rt2x00_set_field8(&rfcsr, RFCSR30_RF_CALIBRATION, 1); |
Bartlomiej Zolnierkiewicz | 1af68f7 | 2009-11-04 18:34:11 +0100 | [diff] [blame] | 1899 | rt2800_rfcsr_write(rt2x00dev, 30, rfcsr); |
Ivo van Doorn | a9b3a9f | 2009-10-15 22:04:14 +0200 | [diff] [blame] | 1900 | msleep(1); |
| 1901 | rt2x00_set_field8(&rfcsr, RFCSR30_RF_CALIBRATION, 0); |
Bartlomiej Zolnierkiewicz | 1af68f7 | 2009-11-04 18:34:11 +0100 | [diff] [blame] | 1902 | rt2800_rfcsr_write(rt2x00dev, 30, rfcsr); |
Ivo van Doorn | a9b3a9f | 2009-10-15 22:04:14 +0200 | [diff] [blame] | 1903 | |
Bartlomiej Zolnierkiewicz | 1af68f7 | 2009-11-04 18:34:11 +0100 | [diff] [blame] | 1904 | rt2800_rfcsr_write(rt2x00dev, 0, 0x50); |
| 1905 | rt2800_rfcsr_write(rt2x00dev, 1, 0x01); |
| 1906 | rt2800_rfcsr_write(rt2x00dev, 2, 0xf7); |
| 1907 | rt2800_rfcsr_write(rt2x00dev, 3, 0x75); |
| 1908 | rt2800_rfcsr_write(rt2x00dev, 4, 0x40); |
| 1909 | rt2800_rfcsr_write(rt2x00dev, 5, 0x03); |
| 1910 | rt2800_rfcsr_write(rt2x00dev, 6, 0x02); |
| 1911 | rt2800_rfcsr_write(rt2x00dev, 7, 0x50); |
| 1912 | rt2800_rfcsr_write(rt2x00dev, 8, 0x39); |
| 1913 | rt2800_rfcsr_write(rt2x00dev, 9, 0x0f); |
| 1914 | rt2800_rfcsr_write(rt2x00dev, 10, 0x60); |
| 1915 | rt2800_rfcsr_write(rt2x00dev, 11, 0x21); |
| 1916 | rt2800_rfcsr_write(rt2x00dev, 12, 0x75); |
| 1917 | rt2800_rfcsr_write(rt2x00dev, 13, 0x75); |
| 1918 | rt2800_rfcsr_write(rt2x00dev, 14, 0x90); |
| 1919 | rt2800_rfcsr_write(rt2x00dev, 15, 0x58); |
| 1920 | rt2800_rfcsr_write(rt2x00dev, 16, 0xb3); |
| 1921 | rt2800_rfcsr_write(rt2x00dev, 17, 0x92); |
| 1922 | rt2800_rfcsr_write(rt2x00dev, 18, 0x2c); |
| 1923 | rt2800_rfcsr_write(rt2x00dev, 19, 0x02); |
| 1924 | rt2800_rfcsr_write(rt2x00dev, 20, 0xba); |
| 1925 | rt2800_rfcsr_write(rt2x00dev, 21, 0xdb); |
| 1926 | rt2800_rfcsr_write(rt2x00dev, 22, 0x00); |
| 1927 | rt2800_rfcsr_write(rt2x00dev, 23, 0x31); |
| 1928 | rt2800_rfcsr_write(rt2x00dev, 24, 0x08); |
| 1929 | rt2800_rfcsr_write(rt2x00dev, 25, 0x01); |
| 1930 | rt2800_rfcsr_write(rt2x00dev, 26, 0x25); |
| 1931 | rt2800_rfcsr_write(rt2x00dev, 27, 0x23); |
| 1932 | rt2800_rfcsr_write(rt2x00dev, 28, 0x13); |
| 1933 | rt2800_rfcsr_write(rt2x00dev, 29, 0x83); |
Ivo van Doorn | a9b3a9f | 2009-10-15 22:04:14 +0200 | [diff] [blame] | 1934 | |
| 1935 | /* |
| 1936 | * Set RX Filter calibration for 20MHz and 40MHz |
| 1937 | */ |
| 1938 | rt2x00dev->calibration[0] = |
| 1939 | rt2800pci_init_rx_filter(rt2x00dev, false, 0x07, 0x16); |
| 1940 | rt2x00dev->calibration[1] = |
| 1941 | rt2800pci_init_rx_filter(rt2x00dev, true, 0x27, 0x19); |
| 1942 | |
| 1943 | /* |
| 1944 | * Set back to initial state |
| 1945 | */ |
Bartlomiej Zolnierkiewicz | 3e2c9df | 2009-11-04 18:33:57 +0100 | [diff] [blame] | 1946 | rt2800_bbp_write(rt2x00dev, 24, 0); |
Ivo van Doorn | a9b3a9f | 2009-10-15 22:04:14 +0200 | [diff] [blame] | 1947 | |
Bartlomiej Zolnierkiewicz | 1af68f7 | 2009-11-04 18:34:11 +0100 | [diff] [blame] | 1948 | rt2800_rfcsr_read(rt2x00dev, 22, &rfcsr); |
Ivo van Doorn | a9b3a9f | 2009-10-15 22:04:14 +0200 | [diff] [blame] | 1949 | rt2x00_set_field8(&rfcsr, RFCSR22_BASEBAND_LOOPBACK, 0); |
Bartlomiej Zolnierkiewicz | 1af68f7 | 2009-11-04 18:34:11 +0100 | [diff] [blame] | 1950 | rt2800_rfcsr_write(rt2x00dev, 22, rfcsr); |
Ivo van Doorn | a9b3a9f | 2009-10-15 22:04:14 +0200 | [diff] [blame] | 1951 | |
| 1952 | /* |
| 1953 | * set BBP back to BW20 |
| 1954 | */ |
Bartlomiej Zolnierkiewicz | 3e2c9df | 2009-11-04 18:33:57 +0100 | [diff] [blame] | 1955 | rt2800_bbp_read(rt2x00dev, 4, &bbp); |
Ivo van Doorn | a9b3a9f | 2009-10-15 22:04:14 +0200 | [diff] [blame] | 1956 | rt2x00_set_field8(&bbp, BBP4_BANDWIDTH, 0); |
Bartlomiej Zolnierkiewicz | 3e2c9df | 2009-11-04 18:33:57 +0100 | [diff] [blame] | 1957 | rt2800_bbp_write(rt2x00dev, 4, bbp); |
Ivo van Doorn | a9b3a9f | 2009-10-15 22:04:14 +0200 | [diff] [blame] | 1958 | |
| 1959 | return 0; |
| 1960 | } |
| 1961 | |
| 1962 | /* |
| 1963 | * Device state switch handlers. |
| 1964 | */ |
| 1965 | static void rt2800pci_toggle_rx(struct rt2x00_dev *rt2x00dev, |
| 1966 | enum dev_state state) |
| 1967 | { |
| 1968 | u32 reg; |
| 1969 | |
Bartlomiej Zolnierkiewicz | 9ca21eb | 2009-11-04 18:33:13 +0100 | [diff] [blame] | 1970 | rt2800_register_read(rt2x00dev, MAC_SYS_CTRL, ®); |
Ivo van Doorn | a9b3a9f | 2009-10-15 22:04:14 +0200 | [diff] [blame] | 1971 | rt2x00_set_field32(®, MAC_SYS_CTRL_ENABLE_RX, |
| 1972 | (state == STATE_RADIO_RX_ON) || |
| 1973 | (state == STATE_RADIO_RX_ON_LINK)); |
Bartlomiej Zolnierkiewicz | 9ca21eb | 2009-11-04 18:33:13 +0100 | [diff] [blame] | 1974 | rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, reg); |
Ivo van Doorn | a9b3a9f | 2009-10-15 22:04:14 +0200 | [diff] [blame] | 1975 | } |
| 1976 | |
| 1977 | static void rt2800pci_toggle_irq(struct rt2x00_dev *rt2x00dev, |
| 1978 | enum dev_state state) |
| 1979 | { |
| 1980 | int mask = (state == STATE_RADIO_IRQ_ON); |
| 1981 | u32 reg; |
| 1982 | |
| 1983 | /* |
| 1984 | * When interrupts are being enabled, the interrupt registers |
| 1985 | * should clear the register to assure a clean state. |
| 1986 | */ |
| 1987 | if (state == STATE_RADIO_IRQ_ON) { |
Bartlomiej Zolnierkiewicz | 9ca21eb | 2009-11-04 18:33:13 +0100 | [diff] [blame] | 1988 | rt2800_register_read(rt2x00dev, INT_SOURCE_CSR, ®); |
| 1989 | rt2800_register_write(rt2x00dev, INT_SOURCE_CSR, reg); |
Ivo van Doorn | a9b3a9f | 2009-10-15 22:04:14 +0200 | [diff] [blame] | 1990 | } |
| 1991 | |
Bartlomiej Zolnierkiewicz | 9ca21eb | 2009-11-04 18:33:13 +0100 | [diff] [blame] | 1992 | rt2800_register_read(rt2x00dev, INT_MASK_CSR, ®); |
Ivo van Doorn | a9b3a9f | 2009-10-15 22:04:14 +0200 | [diff] [blame] | 1993 | rt2x00_set_field32(®, INT_MASK_CSR_RXDELAYINT, mask); |
| 1994 | rt2x00_set_field32(®, INT_MASK_CSR_TXDELAYINT, mask); |
| 1995 | rt2x00_set_field32(®, INT_MASK_CSR_RX_DONE, mask); |
| 1996 | rt2x00_set_field32(®, INT_MASK_CSR_AC0_DMA_DONE, mask); |
| 1997 | rt2x00_set_field32(®, INT_MASK_CSR_AC1_DMA_DONE, mask); |
| 1998 | rt2x00_set_field32(®, INT_MASK_CSR_AC2_DMA_DONE, mask); |
| 1999 | rt2x00_set_field32(®, INT_MASK_CSR_AC3_DMA_DONE, mask); |
| 2000 | rt2x00_set_field32(®, INT_MASK_CSR_HCCA_DMA_DONE, mask); |
| 2001 | rt2x00_set_field32(®, INT_MASK_CSR_MGMT_DMA_DONE, mask); |
| 2002 | rt2x00_set_field32(®, INT_MASK_CSR_MCU_COMMAND, mask); |
| 2003 | rt2x00_set_field32(®, INT_MASK_CSR_RXTX_COHERENT, mask); |
| 2004 | rt2x00_set_field32(®, INT_MASK_CSR_TBTT, mask); |
| 2005 | rt2x00_set_field32(®, INT_MASK_CSR_PRE_TBTT, mask); |
| 2006 | rt2x00_set_field32(®, INT_MASK_CSR_TX_FIFO_STATUS, mask); |
| 2007 | rt2x00_set_field32(®, INT_MASK_CSR_AUTO_WAKEUP, mask); |
| 2008 | rt2x00_set_field32(®, INT_MASK_CSR_GPTIMER, mask); |
| 2009 | rt2x00_set_field32(®, INT_MASK_CSR_RX_COHERENT, mask); |
| 2010 | rt2x00_set_field32(®, INT_MASK_CSR_TX_COHERENT, mask); |
Bartlomiej Zolnierkiewicz | 9ca21eb | 2009-11-04 18:33:13 +0100 | [diff] [blame] | 2011 | rt2800_register_write(rt2x00dev, INT_MASK_CSR, reg); |
Ivo van Doorn | a9b3a9f | 2009-10-15 22:04:14 +0200 | [diff] [blame] | 2012 | } |
| 2013 | |
| 2014 | static int rt2800pci_wait_wpdma_ready(struct rt2x00_dev *rt2x00dev) |
| 2015 | { |
| 2016 | unsigned int i; |
| 2017 | u32 reg; |
| 2018 | |
| 2019 | for (i = 0; i < REGISTER_BUSY_COUNT; i++) { |
Bartlomiej Zolnierkiewicz | 9ca21eb | 2009-11-04 18:33:13 +0100 | [diff] [blame] | 2020 | rt2800_register_read(rt2x00dev, WPDMA_GLO_CFG, ®); |
Ivo van Doorn | a9b3a9f | 2009-10-15 22:04:14 +0200 | [diff] [blame] | 2021 | if (!rt2x00_get_field32(reg, WPDMA_GLO_CFG_TX_DMA_BUSY) && |
| 2022 | !rt2x00_get_field32(reg, WPDMA_GLO_CFG_RX_DMA_BUSY)) |
| 2023 | return 0; |
| 2024 | |
| 2025 | msleep(1); |
| 2026 | } |
| 2027 | |
| 2028 | ERROR(rt2x00dev, "WPDMA TX/RX busy, aborting.\n"); |
| 2029 | return -EACCES; |
| 2030 | } |
| 2031 | |
| 2032 | static int rt2800pci_enable_radio(struct rt2x00_dev *rt2x00dev) |
| 2033 | { |
| 2034 | u32 reg; |
| 2035 | u16 word; |
| 2036 | |
| 2037 | /* |
| 2038 | * Initialize all registers. |
| 2039 | */ |
| 2040 | if (unlikely(rt2800pci_wait_wpdma_ready(rt2x00dev) || |
| 2041 | rt2800pci_init_queues(rt2x00dev) || |
| 2042 | rt2800pci_init_registers(rt2x00dev) || |
| 2043 | rt2800pci_wait_wpdma_ready(rt2x00dev) || |
| 2044 | rt2800pci_init_bbp(rt2x00dev) || |
| 2045 | rt2800pci_init_rfcsr(rt2x00dev))) |
| 2046 | return -EIO; |
| 2047 | |
| 2048 | /* |
| 2049 | * Send signal to firmware during boot time. |
| 2050 | */ |
Bartlomiej Zolnierkiewicz | 3a9e5b0 | 2009-11-04 18:34:39 +0100 | [diff] [blame] | 2051 | rt2800_mcu_request(rt2x00dev, MCU_BOOT_SIGNAL, 0xff, 0, 0); |
Ivo van Doorn | a9b3a9f | 2009-10-15 22:04:14 +0200 | [diff] [blame] | 2052 | |
| 2053 | /* |
| 2054 | * Enable RX. |
| 2055 | */ |
Bartlomiej Zolnierkiewicz | 9ca21eb | 2009-11-04 18:33:13 +0100 | [diff] [blame] | 2056 | rt2800_register_read(rt2x00dev, MAC_SYS_CTRL, ®); |
Ivo van Doorn | a9b3a9f | 2009-10-15 22:04:14 +0200 | [diff] [blame] | 2057 | rt2x00_set_field32(®, MAC_SYS_CTRL_ENABLE_TX, 1); |
| 2058 | rt2x00_set_field32(®, MAC_SYS_CTRL_ENABLE_RX, 0); |
Bartlomiej Zolnierkiewicz | 9ca21eb | 2009-11-04 18:33:13 +0100 | [diff] [blame] | 2059 | rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, reg); |
Ivo van Doorn | a9b3a9f | 2009-10-15 22:04:14 +0200 | [diff] [blame] | 2060 | |
Bartlomiej Zolnierkiewicz | 9ca21eb | 2009-11-04 18:33:13 +0100 | [diff] [blame] | 2061 | rt2800_register_read(rt2x00dev, WPDMA_GLO_CFG, ®); |
Ivo van Doorn | a9b3a9f | 2009-10-15 22:04:14 +0200 | [diff] [blame] | 2062 | rt2x00_set_field32(®, WPDMA_GLO_CFG_ENABLE_TX_DMA, 1); |
| 2063 | rt2x00_set_field32(®, WPDMA_GLO_CFG_ENABLE_RX_DMA, 1); |
| 2064 | rt2x00_set_field32(®, WPDMA_GLO_CFG_WP_DMA_BURST_SIZE, 2); |
| 2065 | rt2x00_set_field32(®, WPDMA_GLO_CFG_TX_WRITEBACK_DONE, 1); |
Bartlomiej Zolnierkiewicz | 9ca21eb | 2009-11-04 18:33:13 +0100 | [diff] [blame] | 2066 | rt2800_register_write(rt2x00dev, WPDMA_GLO_CFG, reg); |
Ivo van Doorn | a9b3a9f | 2009-10-15 22:04:14 +0200 | [diff] [blame] | 2067 | |
Bartlomiej Zolnierkiewicz | 9ca21eb | 2009-11-04 18:33:13 +0100 | [diff] [blame] | 2068 | rt2800_register_read(rt2x00dev, MAC_SYS_CTRL, ®); |
Ivo van Doorn | a9b3a9f | 2009-10-15 22:04:14 +0200 | [diff] [blame] | 2069 | rt2x00_set_field32(®, MAC_SYS_CTRL_ENABLE_TX, 1); |
| 2070 | rt2x00_set_field32(®, MAC_SYS_CTRL_ENABLE_RX, 1); |
Bartlomiej Zolnierkiewicz | 9ca21eb | 2009-11-04 18:33:13 +0100 | [diff] [blame] | 2071 | rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, reg); |
Ivo van Doorn | a9b3a9f | 2009-10-15 22:04:14 +0200 | [diff] [blame] | 2072 | |
| 2073 | /* |
| 2074 | * Initialize LED control |
| 2075 | */ |
| 2076 | rt2x00_eeprom_read(rt2x00dev, EEPROM_LED1, &word); |
Bartlomiej Zolnierkiewicz | 3a9e5b0 | 2009-11-04 18:34:39 +0100 | [diff] [blame] | 2077 | rt2800_mcu_request(rt2x00dev, MCU_LED_1, 0xff, |
Ivo van Doorn | a9b3a9f | 2009-10-15 22:04:14 +0200 | [diff] [blame] | 2078 | word & 0xff, (word >> 8) & 0xff); |
| 2079 | |
| 2080 | rt2x00_eeprom_read(rt2x00dev, EEPROM_LED2, &word); |
Bartlomiej Zolnierkiewicz | 3a9e5b0 | 2009-11-04 18:34:39 +0100 | [diff] [blame] | 2081 | rt2800_mcu_request(rt2x00dev, MCU_LED_2, 0xff, |
Ivo van Doorn | a9b3a9f | 2009-10-15 22:04:14 +0200 | [diff] [blame] | 2082 | word & 0xff, (word >> 8) & 0xff); |
| 2083 | |
| 2084 | rt2x00_eeprom_read(rt2x00dev, EEPROM_LED3, &word); |
Bartlomiej Zolnierkiewicz | 3a9e5b0 | 2009-11-04 18:34:39 +0100 | [diff] [blame] | 2085 | rt2800_mcu_request(rt2x00dev, MCU_LED_3, 0xff, |
Ivo van Doorn | a9b3a9f | 2009-10-15 22:04:14 +0200 | [diff] [blame] | 2086 | word & 0xff, (word >> 8) & 0xff); |
| 2087 | |
| 2088 | return 0; |
| 2089 | } |
| 2090 | |
| 2091 | static void rt2800pci_disable_radio(struct rt2x00_dev *rt2x00dev) |
| 2092 | { |
| 2093 | u32 reg; |
| 2094 | |
Bartlomiej Zolnierkiewicz | 9ca21eb | 2009-11-04 18:33:13 +0100 | [diff] [blame] | 2095 | rt2800_register_read(rt2x00dev, WPDMA_GLO_CFG, ®); |
Ivo van Doorn | a9b3a9f | 2009-10-15 22:04:14 +0200 | [diff] [blame] | 2096 | rt2x00_set_field32(®, WPDMA_GLO_CFG_ENABLE_TX_DMA, 0); |
| 2097 | rt2x00_set_field32(®, WPDMA_GLO_CFG_TX_DMA_BUSY, 0); |
| 2098 | rt2x00_set_field32(®, WPDMA_GLO_CFG_ENABLE_RX_DMA, 0); |
| 2099 | rt2x00_set_field32(®, WPDMA_GLO_CFG_RX_DMA_BUSY, 0); |
| 2100 | rt2x00_set_field32(®, WPDMA_GLO_CFG_TX_WRITEBACK_DONE, 1); |
Bartlomiej Zolnierkiewicz | 9ca21eb | 2009-11-04 18:33:13 +0100 | [diff] [blame] | 2101 | rt2800_register_write(rt2x00dev, WPDMA_GLO_CFG, reg); |
Ivo van Doorn | a9b3a9f | 2009-10-15 22:04:14 +0200 | [diff] [blame] | 2102 | |
Bartlomiej Zolnierkiewicz | 9ca21eb | 2009-11-04 18:33:13 +0100 | [diff] [blame] | 2103 | rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, 0); |
| 2104 | rt2800_register_write(rt2x00dev, PWR_PIN_CFG, 0); |
| 2105 | rt2800_register_write(rt2x00dev, TX_PIN_CFG, 0); |
Ivo van Doorn | a9b3a9f | 2009-10-15 22:04:14 +0200 | [diff] [blame] | 2106 | |
Bartlomiej Zolnierkiewicz | 9ca21eb | 2009-11-04 18:33:13 +0100 | [diff] [blame] | 2107 | rt2800_register_write(rt2x00dev, PBF_SYS_CTRL, 0x00001280); |
Ivo van Doorn | a9b3a9f | 2009-10-15 22:04:14 +0200 | [diff] [blame] | 2108 | |
Bartlomiej Zolnierkiewicz | 9ca21eb | 2009-11-04 18:33:13 +0100 | [diff] [blame] | 2109 | rt2800_register_read(rt2x00dev, WPDMA_RST_IDX, ®); |
Ivo van Doorn | a9b3a9f | 2009-10-15 22:04:14 +0200 | [diff] [blame] | 2110 | rt2x00_set_field32(®, WPDMA_RST_IDX_DTX_IDX0, 1); |
| 2111 | rt2x00_set_field32(®, WPDMA_RST_IDX_DTX_IDX1, 1); |
| 2112 | rt2x00_set_field32(®, WPDMA_RST_IDX_DTX_IDX2, 1); |
| 2113 | rt2x00_set_field32(®, WPDMA_RST_IDX_DTX_IDX3, 1); |
| 2114 | rt2x00_set_field32(®, WPDMA_RST_IDX_DTX_IDX4, 1); |
| 2115 | rt2x00_set_field32(®, WPDMA_RST_IDX_DTX_IDX5, 1); |
| 2116 | rt2x00_set_field32(®, WPDMA_RST_IDX_DRX_IDX0, 1); |
Bartlomiej Zolnierkiewicz | 9ca21eb | 2009-11-04 18:33:13 +0100 | [diff] [blame] | 2117 | rt2800_register_write(rt2x00dev, WPDMA_RST_IDX, reg); |
Ivo van Doorn | a9b3a9f | 2009-10-15 22:04:14 +0200 | [diff] [blame] | 2118 | |
Bartlomiej Zolnierkiewicz | 9ca21eb | 2009-11-04 18:33:13 +0100 | [diff] [blame] | 2119 | rt2800_register_write(rt2x00dev, PBF_SYS_CTRL, 0x00000e1f); |
| 2120 | rt2800_register_write(rt2x00dev, PBF_SYS_CTRL, 0x00000e00); |
Ivo van Doorn | a9b3a9f | 2009-10-15 22:04:14 +0200 | [diff] [blame] | 2121 | |
| 2122 | /* Wait for DMA, ignore error */ |
| 2123 | rt2800pci_wait_wpdma_ready(rt2x00dev); |
| 2124 | } |
| 2125 | |
| 2126 | static int rt2800pci_set_state(struct rt2x00_dev *rt2x00dev, |
| 2127 | enum dev_state state) |
| 2128 | { |
| 2129 | /* |
| 2130 | * Always put the device to sleep (even when we intend to wakeup!) |
| 2131 | * if the device is booting and wasn't asleep it will return |
| 2132 | * failure when attempting to wakeup. |
| 2133 | */ |
Bartlomiej Zolnierkiewicz | 3a9e5b0 | 2009-11-04 18:34:39 +0100 | [diff] [blame] | 2134 | rt2800_mcu_request(rt2x00dev, MCU_SLEEP, 0xff, 0, 2); |
Ivo van Doorn | a9b3a9f | 2009-10-15 22:04:14 +0200 | [diff] [blame] | 2135 | |
| 2136 | if (state == STATE_AWAKE) { |
Bartlomiej Zolnierkiewicz | 3a9e5b0 | 2009-11-04 18:34:39 +0100 | [diff] [blame] | 2137 | rt2800_mcu_request(rt2x00dev, MCU_WAKEUP, TOKEN_WAKUP, 0, 0); |
Ivo van Doorn | a9b3a9f | 2009-10-15 22:04:14 +0200 | [diff] [blame] | 2138 | rt2800pci_mcu_status(rt2x00dev, TOKEN_WAKUP); |
| 2139 | } |
| 2140 | |
| 2141 | return 0; |
| 2142 | } |
| 2143 | |
| 2144 | static int rt2800pci_set_device_state(struct rt2x00_dev *rt2x00dev, |
| 2145 | enum dev_state state) |
| 2146 | { |
| 2147 | int retval = 0; |
| 2148 | |
| 2149 | switch (state) { |
| 2150 | case STATE_RADIO_ON: |
| 2151 | /* |
| 2152 | * Before the radio can be enabled, the device first has |
| 2153 | * to be woken up. After that it needs a bit of time |
| 2154 | * to be fully awake and then the radio can be enabled. |
| 2155 | */ |
| 2156 | rt2800pci_set_state(rt2x00dev, STATE_AWAKE); |
| 2157 | msleep(1); |
| 2158 | retval = rt2800pci_enable_radio(rt2x00dev); |
| 2159 | break; |
| 2160 | case STATE_RADIO_OFF: |
| 2161 | /* |
| 2162 | * After the radio has been disabled, the device should |
| 2163 | * be put to sleep for powersaving. |
| 2164 | */ |
| 2165 | rt2800pci_disable_radio(rt2x00dev); |
| 2166 | rt2800pci_set_state(rt2x00dev, STATE_SLEEP); |
| 2167 | break; |
| 2168 | case STATE_RADIO_RX_ON: |
| 2169 | case STATE_RADIO_RX_ON_LINK: |
| 2170 | case STATE_RADIO_RX_OFF: |
| 2171 | case STATE_RADIO_RX_OFF_LINK: |
| 2172 | rt2800pci_toggle_rx(rt2x00dev, state); |
| 2173 | break; |
| 2174 | case STATE_RADIO_IRQ_ON: |
| 2175 | case STATE_RADIO_IRQ_OFF: |
| 2176 | rt2800pci_toggle_irq(rt2x00dev, state); |
| 2177 | break; |
| 2178 | case STATE_DEEP_SLEEP: |
| 2179 | case STATE_SLEEP: |
| 2180 | case STATE_STANDBY: |
| 2181 | case STATE_AWAKE: |
| 2182 | retval = rt2800pci_set_state(rt2x00dev, state); |
| 2183 | break; |
| 2184 | default: |
| 2185 | retval = -ENOTSUPP; |
| 2186 | break; |
| 2187 | } |
| 2188 | |
| 2189 | if (unlikely(retval)) |
| 2190 | ERROR(rt2x00dev, "Device failed to enter state %d (%d).\n", |
| 2191 | state, retval); |
| 2192 | |
| 2193 | return retval; |
| 2194 | } |
| 2195 | |
| 2196 | /* |
| 2197 | * TX descriptor initialization |
| 2198 | */ |
| 2199 | static void rt2800pci_write_tx_desc(struct rt2x00_dev *rt2x00dev, |
| 2200 | struct sk_buff *skb, |
| 2201 | struct txentry_desc *txdesc) |
| 2202 | { |
| 2203 | struct skb_frame_desc *skbdesc = get_skb_frame_desc(skb); |
| 2204 | __le32 *txd = skbdesc->desc; |
| 2205 | __le32 *txwi = (__le32 *)(skb->data - rt2x00dev->hw->extra_tx_headroom); |
| 2206 | u32 word; |
| 2207 | |
| 2208 | /* |
| 2209 | * Initialize TX Info descriptor |
| 2210 | */ |
| 2211 | rt2x00_desc_read(txwi, 0, &word); |
| 2212 | rt2x00_set_field32(&word, TXWI_W0_FRAG, |
| 2213 | test_bit(ENTRY_TXD_MORE_FRAG, &txdesc->flags)); |
| 2214 | rt2x00_set_field32(&word, TXWI_W0_MIMO_PS, 0); |
| 2215 | rt2x00_set_field32(&word, TXWI_W0_CF_ACK, 0); |
| 2216 | rt2x00_set_field32(&word, TXWI_W0_TS, |
| 2217 | test_bit(ENTRY_TXD_REQ_TIMESTAMP, &txdesc->flags)); |
| 2218 | rt2x00_set_field32(&word, TXWI_W0_AMPDU, |
| 2219 | test_bit(ENTRY_TXD_HT_AMPDU, &txdesc->flags)); |
| 2220 | rt2x00_set_field32(&word, TXWI_W0_MPDU_DENSITY, txdesc->mpdu_density); |
| 2221 | rt2x00_set_field32(&word, TXWI_W0_TX_OP, txdesc->ifs); |
| 2222 | rt2x00_set_field32(&word, TXWI_W0_MCS, txdesc->mcs); |
| 2223 | rt2x00_set_field32(&word, TXWI_W0_BW, |
| 2224 | test_bit(ENTRY_TXD_HT_BW_40, &txdesc->flags)); |
| 2225 | rt2x00_set_field32(&word, TXWI_W0_SHORT_GI, |
| 2226 | test_bit(ENTRY_TXD_HT_SHORT_GI, &txdesc->flags)); |
| 2227 | rt2x00_set_field32(&word, TXWI_W0_STBC, txdesc->stbc); |
| 2228 | rt2x00_set_field32(&word, TXWI_W0_PHYMODE, txdesc->rate_mode); |
| 2229 | rt2x00_desc_write(txwi, 0, word); |
| 2230 | |
| 2231 | rt2x00_desc_read(txwi, 1, &word); |
| 2232 | rt2x00_set_field32(&word, TXWI_W1_ACK, |
| 2233 | test_bit(ENTRY_TXD_ACK, &txdesc->flags)); |
| 2234 | rt2x00_set_field32(&word, TXWI_W1_NSEQ, |
| 2235 | test_bit(ENTRY_TXD_GENERATE_SEQ, &txdesc->flags)); |
| 2236 | rt2x00_set_field32(&word, TXWI_W1_BW_WIN_SIZE, txdesc->ba_size); |
| 2237 | rt2x00_set_field32(&word, TXWI_W1_WIRELESS_CLI_ID, |
| 2238 | test_bit(ENTRY_TXD_ENCRYPT, &txdesc->flags) ? |
Bartlomiej Zolnierkiewicz | f644fea | 2009-11-04 18:32:24 +0100 | [diff] [blame] | 2239 | txdesc->key_idx : 0xff); |
Ivo van Doorn | a9b3a9f | 2009-10-15 22:04:14 +0200 | [diff] [blame] | 2240 | rt2x00_set_field32(&word, TXWI_W1_MPDU_TOTAL_BYTE_COUNT, |
| 2241 | skb->len - txdesc->l2pad); |
| 2242 | rt2x00_set_field32(&word, TXWI_W1_PACKETID, |
| 2243 | skbdesc->entry->queue->qid + 1); |
| 2244 | rt2x00_desc_write(txwi, 1, word); |
| 2245 | |
| 2246 | /* |
| 2247 | * Always write 0 to IV/EIV fields, hardware will insert the IV |
Bartlomiej Zolnierkiewicz | 77dba49 | 2009-11-04 18:32:40 +0100 | [diff] [blame] | 2248 | * from the IVEIV register when TXD_W3_WIV is set to 0. |
| 2249 | * When TXD_W3_WIV is set to 1 it will use the IV data |
Ivo van Doorn | a9b3a9f | 2009-10-15 22:04:14 +0200 | [diff] [blame] | 2250 | * from the descriptor. The TXWI_W1_WIRELESS_CLI_ID indicates which |
| 2251 | * crypto entry in the registers should be used to encrypt the frame. |
| 2252 | */ |
| 2253 | _rt2x00_desc_write(txwi, 2, 0 /* skbdesc->iv[0] */); |
| 2254 | _rt2x00_desc_write(txwi, 3, 0 /* skbdesc->iv[1] */); |
| 2255 | |
| 2256 | /* |
| 2257 | * The buffers pointed by SD_PTR0/SD_LEN0 and SD_PTR1/SD_LEN1 |
| 2258 | * must contains a TXWI structure + 802.11 header + padding + 802.11 |
| 2259 | * data. We choose to have SD_PTR0/SD_LEN0 only contains TXWI and |
| 2260 | * SD_PTR1/SD_LEN1 contains 802.11 header + padding + 802.11 |
| 2261 | * data. It means that LAST_SEC0 is always 0. |
| 2262 | */ |
| 2263 | |
| 2264 | /* |
| 2265 | * Initialize TX descriptor |
| 2266 | */ |
| 2267 | rt2x00_desc_read(txd, 0, &word); |
| 2268 | rt2x00_set_field32(&word, TXD_W0_SD_PTR0, skbdesc->skb_dma); |
| 2269 | rt2x00_desc_write(txd, 0, word); |
| 2270 | |
| 2271 | rt2x00_desc_read(txd, 1, &word); |
| 2272 | rt2x00_set_field32(&word, TXD_W1_SD_LEN1, skb->len); |
| 2273 | rt2x00_set_field32(&word, TXD_W1_LAST_SEC1, |
| 2274 | !test_bit(ENTRY_TXD_MORE_FRAG, &txdesc->flags)); |
| 2275 | rt2x00_set_field32(&word, TXD_W1_BURST, |
| 2276 | test_bit(ENTRY_TXD_BURST, &txdesc->flags)); |
| 2277 | rt2x00_set_field32(&word, TXD_W1_SD_LEN0, |
| 2278 | rt2x00dev->hw->extra_tx_headroom); |
| 2279 | rt2x00_set_field32(&word, TXD_W1_LAST_SEC0, 0); |
| 2280 | rt2x00_set_field32(&word, TXD_W1_DMA_DONE, 0); |
| 2281 | rt2x00_desc_write(txd, 1, word); |
| 2282 | |
| 2283 | rt2x00_desc_read(txd, 2, &word); |
| 2284 | rt2x00_set_field32(&word, TXD_W2_SD_PTR1, |
| 2285 | skbdesc->skb_dma + rt2x00dev->hw->extra_tx_headroom); |
| 2286 | rt2x00_desc_write(txd, 2, word); |
| 2287 | |
| 2288 | rt2x00_desc_read(txd, 3, &word); |
| 2289 | rt2x00_set_field32(&word, TXD_W3_WIV, |
| 2290 | !test_bit(ENTRY_TXD_ENCRYPT_IV, &txdesc->flags)); |
| 2291 | rt2x00_set_field32(&word, TXD_W3_QSEL, 2); |
| 2292 | rt2x00_desc_write(txd, 3, word); |
| 2293 | } |
| 2294 | |
| 2295 | /* |
| 2296 | * TX data initialization |
| 2297 | */ |
| 2298 | static void rt2800pci_write_beacon(struct queue_entry *entry) |
| 2299 | { |
| 2300 | struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev; |
| 2301 | struct skb_frame_desc *skbdesc = get_skb_frame_desc(entry->skb); |
| 2302 | unsigned int beacon_base; |
| 2303 | u32 reg; |
| 2304 | |
| 2305 | /* |
| 2306 | * Disable beaconing while we are reloading the beacon data, |
| 2307 | * otherwise we might be sending out invalid data. |
| 2308 | */ |
Bartlomiej Zolnierkiewicz | 9ca21eb | 2009-11-04 18:33:13 +0100 | [diff] [blame] | 2309 | rt2800_register_read(rt2x00dev, BCN_TIME_CFG, ®); |
Ivo van Doorn | a9b3a9f | 2009-10-15 22:04:14 +0200 | [diff] [blame] | 2310 | rt2x00_set_field32(®, BCN_TIME_CFG_BEACON_GEN, 0); |
Bartlomiej Zolnierkiewicz | 9ca21eb | 2009-11-04 18:33:13 +0100 | [diff] [blame] | 2311 | rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg); |
Ivo van Doorn | a9b3a9f | 2009-10-15 22:04:14 +0200 | [diff] [blame] | 2312 | |
| 2313 | /* |
| 2314 | * Write entire beacon with descriptor to register. |
| 2315 | */ |
| 2316 | beacon_base = HW_BEACON_OFFSET(entry->entry_idx); |
Bartlomiej Zolnierkiewicz | 4f2732c | 2009-11-04 18:33:27 +0100 | [diff] [blame] | 2317 | rt2800_register_multiwrite(rt2x00dev, |
Ivo van Doorn | a9b3a9f | 2009-10-15 22:04:14 +0200 | [diff] [blame] | 2318 | beacon_base, |
| 2319 | skbdesc->desc, skbdesc->desc_len); |
Bartlomiej Zolnierkiewicz | 4f2732c | 2009-11-04 18:33:27 +0100 | [diff] [blame] | 2320 | rt2800_register_multiwrite(rt2x00dev, |
Ivo van Doorn | a9b3a9f | 2009-10-15 22:04:14 +0200 | [diff] [blame] | 2321 | beacon_base + skbdesc->desc_len, |
| 2322 | entry->skb->data, entry->skb->len); |
| 2323 | |
| 2324 | /* |
| 2325 | * Clean up beacon skb. |
| 2326 | */ |
| 2327 | dev_kfree_skb_any(entry->skb); |
| 2328 | entry->skb = NULL; |
| 2329 | } |
| 2330 | |
| 2331 | static void rt2800pci_kick_tx_queue(struct rt2x00_dev *rt2x00dev, |
| 2332 | const enum data_queue_qid queue_idx) |
| 2333 | { |
| 2334 | struct data_queue *queue; |
| 2335 | unsigned int idx, qidx = 0; |
| 2336 | u32 reg; |
| 2337 | |
| 2338 | if (queue_idx == QID_BEACON) { |
Bartlomiej Zolnierkiewicz | 9ca21eb | 2009-11-04 18:33:13 +0100 | [diff] [blame] | 2339 | rt2800_register_read(rt2x00dev, BCN_TIME_CFG, ®); |
Ivo van Doorn | a9b3a9f | 2009-10-15 22:04:14 +0200 | [diff] [blame] | 2340 | if (!rt2x00_get_field32(reg, BCN_TIME_CFG_BEACON_GEN)) { |
| 2341 | rt2x00_set_field32(®, BCN_TIME_CFG_TSF_TICKING, 1); |
| 2342 | rt2x00_set_field32(®, BCN_TIME_CFG_TBTT_ENABLE, 1); |
| 2343 | rt2x00_set_field32(®, BCN_TIME_CFG_BEACON_GEN, 1); |
Bartlomiej Zolnierkiewicz | 9ca21eb | 2009-11-04 18:33:13 +0100 | [diff] [blame] | 2344 | rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg); |
Ivo van Doorn | a9b3a9f | 2009-10-15 22:04:14 +0200 | [diff] [blame] | 2345 | } |
| 2346 | return; |
| 2347 | } |
| 2348 | |
| 2349 | if (queue_idx > QID_HCCA && queue_idx != QID_MGMT) |
| 2350 | return; |
| 2351 | |
| 2352 | queue = rt2x00queue_get_queue(rt2x00dev, queue_idx); |
| 2353 | idx = queue->index[Q_INDEX]; |
| 2354 | |
| 2355 | if (queue_idx == QID_MGMT) |
| 2356 | qidx = 5; |
| 2357 | else |
| 2358 | qidx = queue_idx; |
| 2359 | |
Bartlomiej Zolnierkiewicz | 9ca21eb | 2009-11-04 18:33:13 +0100 | [diff] [blame] | 2360 | rt2800_register_write(rt2x00dev, TX_CTX_IDX(qidx), idx); |
Ivo van Doorn | a9b3a9f | 2009-10-15 22:04:14 +0200 | [diff] [blame] | 2361 | } |
| 2362 | |
| 2363 | static void rt2800pci_kill_tx_queue(struct rt2x00_dev *rt2x00dev, |
| 2364 | const enum data_queue_qid qid) |
| 2365 | { |
| 2366 | u32 reg; |
| 2367 | |
| 2368 | if (qid == QID_BEACON) { |
Bartlomiej Zolnierkiewicz | 9ca21eb | 2009-11-04 18:33:13 +0100 | [diff] [blame] | 2369 | rt2800_register_write(rt2x00dev, BCN_TIME_CFG, 0); |
Ivo van Doorn | a9b3a9f | 2009-10-15 22:04:14 +0200 | [diff] [blame] | 2370 | return; |
| 2371 | } |
| 2372 | |
Bartlomiej Zolnierkiewicz | 9ca21eb | 2009-11-04 18:33:13 +0100 | [diff] [blame] | 2373 | rt2800_register_read(rt2x00dev, WPDMA_RST_IDX, ®); |
Ivo van Doorn | a9b3a9f | 2009-10-15 22:04:14 +0200 | [diff] [blame] | 2374 | rt2x00_set_field32(®, WPDMA_RST_IDX_DTX_IDX0, (qid == QID_AC_BE)); |
| 2375 | rt2x00_set_field32(®, WPDMA_RST_IDX_DTX_IDX1, (qid == QID_AC_BK)); |
| 2376 | rt2x00_set_field32(®, WPDMA_RST_IDX_DTX_IDX2, (qid == QID_AC_VI)); |
| 2377 | rt2x00_set_field32(®, WPDMA_RST_IDX_DTX_IDX3, (qid == QID_AC_VO)); |
Bartlomiej Zolnierkiewicz | 9ca21eb | 2009-11-04 18:33:13 +0100 | [diff] [blame] | 2378 | rt2800_register_write(rt2x00dev, WPDMA_RST_IDX, reg); |
Ivo van Doorn | a9b3a9f | 2009-10-15 22:04:14 +0200 | [diff] [blame] | 2379 | } |
| 2380 | |
| 2381 | /* |
| 2382 | * RX control handlers |
| 2383 | */ |
| 2384 | static void rt2800pci_fill_rxdone(struct queue_entry *entry, |
| 2385 | struct rxdone_entry_desc *rxdesc) |
| 2386 | { |
| 2387 | struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev; |
| 2388 | struct skb_frame_desc *skbdesc = get_skb_frame_desc(entry->skb); |
| 2389 | struct queue_entry_priv_pci *entry_priv = entry->priv_data; |
| 2390 | __le32 *rxd = entry_priv->desc; |
| 2391 | __le32 *rxwi = (__le32 *)entry->skb->data; |
| 2392 | u32 rxd3; |
| 2393 | u32 rxwi0; |
| 2394 | u32 rxwi1; |
| 2395 | u32 rxwi2; |
| 2396 | u32 rxwi3; |
| 2397 | |
| 2398 | rt2x00_desc_read(rxd, 3, &rxd3); |
| 2399 | rt2x00_desc_read(rxwi, 0, &rxwi0); |
| 2400 | rt2x00_desc_read(rxwi, 1, &rxwi1); |
| 2401 | rt2x00_desc_read(rxwi, 2, &rxwi2); |
| 2402 | rt2x00_desc_read(rxwi, 3, &rxwi3); |
| 2403 | |
| 2404 | if (rt2x00_get_field32(rxd3, RXD_W3_CRC_ERROR)) |
| 2405 | rxdesc->flags |= RX_FLAG_FAILED_FCS_CRC; |
| 2406 | |
| 2407 | if (test_bit(CONFIG_SUPPORT_HW_CRYPTO, &rt2x00dev->flags)) { |
| 2408 | /* |
| 2409 | * Unfortunately we don't know the cipher type used during |
| 2410 | * decryption. This prevents us from correct providing |
| 2411 | * correct statistics through debugfs. |
| 2412 | */ |
| 2413 | rxdesc->cipher = rt2x00_get_field32(rxwi0, RXWI_W0_UDF); |
| 2414 | rxdesc->cipher_status = |
| 2415 | rt2x00_get_field32(rxd3, RXD_W3_CIPHER_ERROR); |
| 2416 | } |
| 2417 | |
| 2418 | if (rt2x00_get_field32(rxd3, RXD_W3_DECRYPTED)) { |
| 2419 | /* |
| 2420 | * Hardware has stripped IV/EIV data from 802.11 frame during |
| 2421 | * decryption. Unfortunately the descriptor doesn't contain |
| 2422 | * any fields with the EIV/IV data either, so they can't |
| 2423 | * be restored by rt2x00lib. |
| 2424 | */ |
| 2425 | rxdesc->flags |= RX_FLAG_IV_STRIPPED; |
| 2426 | |
| 2427 | if (rxdesc->cipher_status == RX_CRYPTO_SUCCESS) |
| 2428 | rxdesc->flags |= RX_FLAG_DECRYPTED; |
| 2429 | else if (rxdesc->cipher_status == RX_CRYPTO_FAIL_MIC) |
| 2430 | rxdesc->flags |= RX_FLAG_MMIC_ERROR; |
| 2431 | } |
| 2432 | |
| 2433 | if (rt2x00_get_field32(rxd3, RXD_W3_MY_BSS)) |
| 2434 | rxdesc->dev_flags |= RXDONE_MY_BSS; |
| 2435 | |
| 2436 | if (rt2x00_get_field32(rxd3, RXD_W3_L2PAD)) { |
| 2437 | rxdesc->dev_flags |= RXDONE_L2PAD; |
| 2438 | skbdesc->flags |= SKBDESC_L2_PADDED; |
| 2439 | } |
| 2440 | |
| 2441 | if (rt2x00_get_field32(rxwi1, RXWI_W1_SHORT_GI)) |
| 2442 | rxdesc->flags |= RX_FLAG_SHORT_GI; |
| 2443 | |
| 2444 | if (rt2x00_get_field32(rxwi1, RXWI_W1_BW)) |
| 2445 | rxdesc->flags |= RX_FLAG_40MHZ; |
| 2446 | |
| 2447 | /* |
| 2448 | * Detect RX rate, always use MCS as signal type. |
| 2449 | */ |
| 2450 | rxdesc->dev_flags |= RXDONE_SIGNAL_MCS; |
| 2451 | rxdesc->rate_mode = rt2x00_get_field32(rxwi1, RXWI_W1_PHYMODE); |
| 2452 | rxdesc->signal = rt2x00_get_field32(rxwi1, RXWI_W1_MCS); |
| 2453 | |
| 2454 | /* |
| 2455 | * Mask of 0x8 bit to remove the short preamble flag. |
| 2456 | */ |
| 2457 | if (rxdesc->rate_mode == RATE_MODE_CCK) |
| 2458 | rxdesc->signal &= ~0x8; |
| 2459 | |
| 2460 | rxdesc->rssi = |
| 2461 | (rt2x00_get_field32(rxwi2, RXWI_W2_RSSI0) + |
| 2462 | rt2x00_get_field32(rxwi2, RXWI_W2_RSSI1)) / 2; |
| 2463 | |
| 2464 | rxdesc->noise = |
| 2465 | (rt2x00_get_field32(rxwi3, RXWI_W3_SNR0) + |
| 2466 | rt2x00_get_field32(rxwi3, RXWI_W3_SNR1)) / 2; |
| 2467 | |
| 2468 | rxdesc->size = rt2x00_get_field32(rxwi0, RXWI_W0_MPDU_TOTAL_BYTE_COUNT); |
| 2469 | |
| 2470 | /* |
| 2471 | * Set RX IDX in register to inform hardware that we have handled |
| 2472 | * this entry and it is available for reuse again. |
| 2473 | */ |
Bartlomiej Zolnierkiewicz | 9ca21eb | 2009-11-04 18:33:13 +0100 | [diff] [blame] | 2474 | rt2800_register_write(rt2x00dev, RX_CRX_IDX, entry->entry_idx); |
Ivo van Doorn | a9b3a9f | 2009-10-15 22:04:14 +0200 | [diff] [blame] | 2475 | |
| 2476 | /* |
| 2477 | * Remove TXWI descriptor from start of buffer. |
| 2478 | */ |
| 2479 | skb_pull(entry->skb, RXWI_DESC_SIZE); |
| 2480 | skb_trim(entry->skb, rxdesc->size); |
| 2481 | } |
| 2482 | |
| 2483 | /* |
| 2484 | * Interrupt functions. |
| 2485 | */ |
| 2486 | static void rt2800pci_txdone(struct rt2x00_dev *rt2x00dev) |
| 2487 | { |
| 2488 | struct data_queue *queue; |
| 2489 | struct queue_entry *entry; |
| 2490 | struct queue_entry *entry_done; |
| 2491 | struct queue_entry_priv_pci *entry_priv; |
| 2492 | struct txdone_entry_desc txdesc; |
| 2493 | u32 word; |
| 2494 | u32 reg; |
| 2495 | u32 old_reg; |
| 2496 | unsigned int type; |
| 2497 | unsigned int index; |
| 2498 | u16 mcs, real_mcs; |
| 2499 | |
| 2500 | /* |
| 2501 | * During each loop we will compare the freshly read |
| 2502 | * TX_STA_FIFO register value with the value read from |
| 2503 | * the previous loop. If the 2 values are equal then |
| 2504 | * we should stop processing because the chance it |
| 2505 | * quite big that the device has been unplugged and |
| 2506 | * we risk going into an endless loop. |
| 2507 | */ |
| 2508 | old_reg = 0; |
| 2509 | |
| 2510 | while (1) { |
Bartlomiej Zolnierkiewicz | 9ca21eb | 2009-11-04 18:33:13 +0100 | [diff] [blame] | 2511 | rt2800_register_read(rt2x00dev, TX_STA_FIFO, ®); |
Ivo van Doorn | a9b3a9f | 2009-10-15 22:04:14 +0200 | [diff] [blame] | 2512 | if (!rt2x00_get_field32(reg, TX_STA_FIFO_VALID)) |
| 2513 | break; |
| 2514 | |
| 2515 | if (old_reg == reg) |
| 2516 | break; |
| 2517 | old_reg = reg; |
| 2518 | |
| 2519 | /* |
| 2520 | * Skip this entry when it contains an invalid |
| 2521 | * queue identication number. |
| 2522 | */ |
| 2523 | type = rt2x00_get_field32(reg, TX_STA_FIFO_PID_TYPE) - 1; |
| 2524 | if (type >= QID_RX) |
| 2525 | continue; |
| 2526 | |
| 2527 | queue = rt2x00queue_get_queue(rt2x00dev, type); |
| 2528 | if (unlikely(!queue)) |
| 2529 | continue; |
| 2530 | |
| 2531 | /* |
| 2532 | * Skip this entry when it contains an invalid |
| 2533 | * index number. |
| 2534 | */ |
| 2535 | index = rt2x00_get_field32(reg, TX_STA_FIFO_WCID) - 1; |
| 2536 | if (unlikely(index >= queue->limit)) |
| 2537 | continue; |
| 2538 | |
| 2539 | entry = &queue->entries[index]; |
| 2540 | entry_priv = entry->priv_data; |
| 2541 | rt2x00_desc_read((__le32 *)entry->skb->data, 0, &word); |
| 2542 | |
| 2543 | entry_done = rt2x00queue_get_entry(queue, Q_INDEX_DONE); |
| 2544 | while (entry != entry_done) { |
| 2545 | /* |
| 2546 | * Catch up. |
| 2547 | * Just report any entries we missed as failed. |
| 2548 | */ |
| 2549 | WARNING(rt2x00dev, |
| 2550 | "TX status report missed for entry %d\n", |
| 2551 | entry_done->entry_idx); |
| 2552 | |
| 2553 | txdesc.flags = 0; |
| 2554 | __set_bit(TXDONE_UNKNOWN, &txdesc.flags); |
| 2555 | txdesc.retry = 0; |
| 2556 | |
| 2557 | rt2x00lib_txdone(entry_done, &txdesc); |
| 2558 | entry_done = rt2x00queue_get_entry(queue, Q_INDEX_DONE); |
| 2559 | } |
| 2560 | |
| 2561 | /* |
| 2562 | * Obtain the status about this packet. |
| 2563 | */ |
| 2564 | txdesc.flags = 0; |
| 2565 | if (rt2x00_get_field32(reg, TX_STA_FIFO_TX_SUCCESS)) |
| 2566 | __set_bit(TXDONE_SUCCESS, &txdesc.flags); |
| 2567 | else |
| 2568 | __set_bit(TXDONE_FAILURE, &txdesc.flags); |
| 2569 | |
| 2570 | /* |
| 2571 | * Ralink has a retry mechanism using a global fallback |
| 2572 | * table. We setup this fallback table to try immediate |
| 2573 | * lower rate for all rates. In the TX_STA_FIFO, |
| 2574 | * the MCS field contains the MCS used for the successfull |
| 2575 | * transmission. If the first transmission succeed, |
| 2576 | * we have mcs == tx_mcs. On the second transmission, |
| 2577 | * we have mcs = tx_mcs - 1. So the number of |
| 2578 | * retry is (tx_mcs - mcs). |
| 2579 | */ |
| 2580 | mcs = rt2x00_get_field32(word, TXWI_W0_MCS); |
| 2581 | real_mcs = rt2x00_get_field32(reg, TX_STA_FIFO_MCS); |
| 2582 | __set_bit(TXDONE_FALLBACK, &txdesc.flags); |
| 2583 | txdesc.retry = mcs - min(mcs, real_mcs); |
| 2584 | |
| 2585 | rt2x00lib_txdone(entry, &txdesc); |
| 2586 | } |
| 2587 | } |
| 2588 | |
| 2589 | static irqreturn_t rt2800pci_interrupt(int irq, void *dev_instance) |
| 2590 | { |
| 2591 | struct rt2x00_dev *rt2x00dev = dev_instance; |
| 2592 | u32 reg; |
| 2593 | |
| 2594 | /* Read status and ACK all interrupts */ |
Bartlomiej Zolnierkiewicz | 9ca21eb | 2009-11-04 18:33:13 +0100 | [diff] [blame] | 2595 | rt2800_register_read(rt2x00dev, INT_SOURCE_CSR, ®); |
| 2596 | rt2800_register_write(rt2x00dev, INT_SOURCE_CSR, reg); |
Ivo van Doorn | a9b3a9f | 2009-10-15 22:04:14 +0200 | [diff] [blame] | 2597 | |
| 2598 | if (!reg) |
| 2599 | return IRQ_NONE; |
| 2600 | |
| 2601 | if (!test_bit(DEVICE_STATE_ENABLED_RADIO, &rt2x00dev->flags)) |
| 2602 | return IRQ_HANDLED; |
| 2603 | |
| 2604 | /* |
| 2605 | * 1 - Rx ring done interrupt. |
| 2606 | */ |
| 2607 | if (rt2x00_get_field32(reg, INT_SOURCE_CSR_RX_DONE)) |
| 2608 | rt2x00pci_rxdone(rt2x00dev); |
| 2609 | |
| 2610 | if (rt2x00_get_field32(reg, INT_SOURCE_CSR_TX_FIFO_STATUS)) |
| 2611 | rt2800pci_txdone(rt2x00dev); |
| 2612 | |
| 2613 | return IRQ_HANDLED; |
| 2614 | } |
| 2615 | |
| 2616 | /* |
| 2617 | * Device probe functions. |
| 2618 | */ |
| 2619 | static int rt2800pci_validate_eeprom(struct rt2x00_dev *rt2x00dev) |
| 2620 | { |
| 2621 | u16 word; |
| 2622 | u8 *mac; |
| 2623 | u8 default_lna_gain; |
| 2624 | |
| 2625 | /* |
| 2626 | * Read EEPROM into buffer |
| 2627 | */ |
| 2628 | switch(rt2x00dev->chip.rt) { |
| 2629 | case RT2880: |
| 2630 | case RT3052: |
| 2631 | rt2800pci_read_eeprom_soc(rt2x00dev); |
| 2632 | break; |
| 2633 | case RT3090: |
| 2634 | rt2800pci_read_eeprom_efuse(rt2x00dev); |
| 2635 | break; |
| 2636 | default: |
| 2637 | rt2800pci_read_eeprom_pci(rt2x00dev); |
| 2638 | break; |
| 2639 | } |
| 2640 | |
| 2641 | /* |
| 2642 | * Start validation of the data that has been read. |
| 2643 | */ |
| 2644 | mac = rt2x00_eeprom_addr(rt2x00dev, EEPROM_MAC_ADDR_0); |
| 2645 | if (!is_valid_ether_addr(mac)) { |
| 2646 | random_ether_addr(mac); |
| 2647 | EEPROM(rt2x00dev, "MAC: %pM\n", mac); |
| 2648 | } |
| 2649 | |
| 2650 | rt2x00_eeprom_read(rt2x00dev, EEPROM_ANTENNA, &word); |
| 2651 | if (word == 0xffff) { |
| 2652 | rt2x00_set_field16(&word, EEPROM_ANTENNA_RXPATH, 2); |
| 2653 | rt2x00_set_field16(&word, EEPROM_ANTENNA_TXPATH, 1); |
| 2654 | rt2x00_set_field16(&word, EEPROM_ANTENNA_RF_TYPE, RF2820); |
| 2655 | rt2x00_eeprom_write(rt2x00dev, EEPROM_ANTENNA, word); |
| 2656 | EEPROM(rt2x00dev, "Antenna: 0x%04x\n", word); |
| 2657 | } else if (rt2x00_rev(&rt2x00dev->chip) < RT2883_VERSION) { |
| 2658 | /* |
| 2659 | * There is a max of 2 RX streams for RT2860 series |
| 2660 | */ |
| 2661 | if (rt2x00_get_field16(word, EEPROM_ANTENNA_RXPATH) > 2) |
| 2662 | rt2x00_set_field16(&word, EEPROM_ANTENNA_RXPATH, 2); |
| 2663 | rt2x00_eeprom_write(rt2x00dev, EEPROM_ANTENNA, word); |
| 2664 | } |
| 2665 | |
| 2666 | rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC, &word); |
| 2667 | if (word == 0xffff) { |
| 2668 | rt2x00_set_field16(&word, EEPROM_NIC_HW_RADIO, 0); |
| 2669 | rt2x00_set_field16(&word, EEPROM_NIC_DYNAMIC_TX_AGC, 0); |
| 2670 | rt2x00_set_field16(&word, EEPROM_NIC_EXTERNAL_LNA_BG, 0); |
| 2671 | rt2x00_set_field16(&word, EEPROM_NIC_EXTERNAL_LNA_A, 0); |
| 2672 | rt2x00_set_field16(&word, EEPROM_NIC_CARDBUS_ACCEL, 0); |
| 2673 | rt2x00_set_field16(&word, EEPROM_NIC_BW40M_SB_BG, 0); |
| 2674 | rt2x00_set_field16(&word, EEPROM_NIC_BW40M_SB_A, 0); |
| 2675 | rt2x00_set_field16(&word, EEPROM_NIC_WPS_PBC, 0); |
| 2676 | rt2x00_set_field16(&word, EEPROM_NIC_BW40M_BG, 0); |
| 2677 | rt2x00_set_field16(&word, EEPROM_NIC_BW40M_A, 0); |
| 2678 | rt2x00_eeprom_write(rt2x00dev, EEPROM_NIC, word); |
| 2679 | EEPROM(rt2x00dev, "NIC: 0x%04x\n", word); |
| 2680 | } |
| 2681 | |
| 2682 | rt2x00_eeprom_read(rt2x00dev, EEPROM_FREQ, &word); |
| 2683 | if ((word & 0x00ff) == 0x00ff) { |
| 2684 | rt2x00_set_field16(&word, EEPROM_FREQ_OFFSET, 0); |
| 2685 | rt2x00_set_field16(&word, EEPROM_FREQ_LED_MODE, |
| 2686 | LED_MODE_TXRX_ACTIVITY); |
| 2687 | rt2x00_set_field16(&word, EEPROM_FREQ_LED_POLARITY, 0); |
| 2688 | rt2x00_eeprom_write(rt2x00dev, EEPROM_FREQ, word); |
| 2689 | rt2x00_eeprom_write(rt2x00dev, EEPROM_LED1, 0x5555); |
| 2690 | rt2x00_eeprom_write(rt2x00dev, EEPROM_LED2, 0x2221); |
| 2691 | rt2x00_eeprom_write(rt2x00dev, EEPROM_LED3, 0xa9f8); |
| 2692 | EEPROM(rt2x00dev, "Freq: 0x%04x\n", word); |
| 2693 | } |
| 2694 | |
| 2695 | /* |
| 2696 | * During the LNA validation we are going to use |
| 2697 | * lna0 as correct value. Note that EEPROM_LNA |
| 2698 | * is never validated. |
| 2699 | */ |
| 2700 | rt2x00_eeprom_read(rt2x00dev, EEPROM_LNA, &word); |
| 2701 | default_lna_gain = rt2x00_get_field16(word, EEPROM_LNA_A0); |
| 2702 | |
| 2703 | rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_BG, &word); |
| 2704 | if (abs(rt2x00_get_field16(word, EEPROM_RSSI_BG_OFFSET0)) > 10) |
| 2705 | rt2x00_set_field16(&word, EEPROM_RSSI_BG_OFFSET0, 0); |
| 2706 | if (abs(rt2x00_get_field16(word, EEPROM_RSSI_BG_OFFSET1)) > 10) |
| 2707 | rt2x00_set_field16(&word, EEPROM_RSSI_BG_OFFSET1, 0); |
| 2708 | rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_BG, word); |
| 2709 | |
| 2710 | rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_BG2, &word); |
| 2711 | if (abs(rt2x00_get_field16(word, EEPROM_RSSI_BG2_OFFSET2)) > 10) |
| 2712 | rt2x00_set_field16(&word, EEPROM_RSSI_BG2_OFFSET2, 0); |
| 2713 | if (rt2x00_get_field16(word, EEPROM_RSSI_BG2_LNA_A1) == 0x00 || |
| 2714 | rt2x00_get_field16(word, EEPROM_RSSI_BG2_LNA_A1) == 0xff) |
| 2715 | rt2x00_set_field16(&word, EEPROM_RSSI_BG2_LNA_A1, |
| 2716 | default_lna_gain); |
| 2717 | rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_BG2, word); |
| 2718 | |
| 2719 | rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_A, &word); |
| 2720 | if (abs(rt2x00_get_field16(word, EEPROM_RSSI_A_OFFSET0)) > 10) |
| 2721 | rt2x00_set_field16(&word, EEPROM_RSSI_A_OFFSET0, 0); |
| 2722 | if (abs(rt2x00_get_field16(word, EEPROM_RSSI_A_OFFSET1)) > 10) |
| 2723 | rt2x00_set_field16(&word, EEPROM_RSSI_A_OFFSET1, 0); |
| 2724 | rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_A, word); |
| 2725 | |
| 2726 | rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_A2, &word); |
| 2727 | if (abs(rt2x00_get_field16(word, EEPROM_RSSI_A2_OFFSET2)) > 10) |
| 2728 | rt2x00_set_field16(&word, EEPROM_RSSI_A2_OFFSET2, 0); |
| 2729 | if (rt2x00_get_field16(word, EEPROM_RSSI_A2_LNA_A2) == 0x00 || |
| 2730 | rt2x00_get_field16(word, EEPROM_RSSI_A2_LNA_A2) == 0xff) |
| 2731 | rt2x00_set_field16(&word, EEPROM_RSSI_A2_LNA_A2, |
| 2732 | default_lna_gain); |
| 2733 | rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_A2, word); |
| 2734 | |
| 2735 | return 0; |
| 2736 | } |
| 2737 | |
| 2738 | static int rt2800pci_init_eeprom(struct rt2x00_dev *rt2x00dev) |
| 2739 | { |
| 2740 | u32 reg; |
| 2741 | u16 value; |
| 2742 | u16 eeprom; |
| 2743 | |
| 2744 | /* |
| 2745 | * Read EEPROM word for configuration. |
| 2746 | */ |
| 2747 | rt2x00_eeprom_read(rt2x00dev, EEPROM_ANTENNA, &eeprom); |
| 2748 | |
| 2749 | /* |
| 2750 | * Identify RF chipset. |
| 2751 | */ |
| 2752 | value = rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RF_TYPE); |
Bartlomiej Zolnierkiewicz | 9ca21eb | 2009-11-04 18:33:13 +0100 | [diff] [blame] | 2753 | rt2800_register_read(rt2x00dev, MAC_CSR0, ®); |
Ivo van Doorn | a9b3a9f | 2009-10-15 22:04:14 +0200 | [diff] [blame] | 2754 | rt2x00_set_chip_rf(rt2x00dev, value, reg); |
| 2755 | |
| 2756 | if (!rt2x00_rf(&rt2x00dev->chip, RF2820) && |
| 2757 | !rt2x00_rf(&rt2x00dev->chip, RF2850) && |
| 2758 | !rt2x00_rf(&rt2x00dev->chip, RF2720) && |
| 2759 | !rt2x00_rf(&rt2x00dev->chip, RF2750) && |
| 2760 | !rt2x00_rf(&rt2x00dev->chip, RF3020) && |
| 2761 | !rt2x00_rf(&rt2x00dev->chip, RF2020) && |
| 2762 | !rt2x00_rf(&rt2x00dev->chip, RF3021) && |
| 2763 | !rt2x00_rf(&rt2x00dev->chip, RF3022)) { |
| 2764 | ERROR(rt2x00dev, "Invalid RF chipset detected.\n"); |
| 2765 | return -ENODEV; |
| 2766 | } |
| 2767 | |
| 2768 | /* |
| 2769 | * Identify default antenna configuration. |
| 2770 | */ |
| 2771 | rt2x00dev->default_ant.tx = |
| 2772 | rt2x00_get_field16(eeprom, EEPROM_ANTENNA_TXPATH); |
| 2773 | rt2x00dev->default_ant.rx = |
| 2774 | rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RXPATH); |
| 2775 | |
| 2776 | /* |
| 2777 | * Read frequency offset and RF programming sequence. |
| 2778 | */ |
| 2779 | rt2x00_eeprom_read(rt2x00dev, EEPROM_FREQ, &eeprom); |
| 2780 | rt2x00dev->freq_offset = rt2x00_get_field16(eeprom, EEPROM_FREQ_OFFSET); |
| 2781 | |
| 2782 | /* |
| 2783 | * Read external LNA informations. |
| 2784 | */ |
| 2785 | rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC, &eeprom); |
| 2786 | |
| 2787 | if (rt2x00_get_field16(eeprom, EEPROM_NIC_EXTERNAL_LNA_A)) |
| 2788 | __set_bit(CONFIG_EXTERNAL_LNA_A, &rt2x00dev->flags); |
| 2789 | if (rt2x00_get_field16(eeprom, EEPROM_NIC_EXTERNAL_LNA_BG)) |
| 2790 | __set_bit(CONFIG_EXTERNAL_LNA_BG, &rt2x00dev->flags); |
| 2791 | |
| 2792 | /* |
| 2793 | * Detect if this device has an hardware controlled radio. |
| 2794 | */ |
| 2795 | if (rt2x00_get_field16(eeprom, EEPROM_NIC_HW_RADIO)) |
| 2796 | __set_bit(CONFIG_SUPPORT_HW_BUTTON, &rt2x00dev->flags); |
| 2797 | |
| 2798 | /* |
| 2799 | * Store led settings, for correct led behaviour. |
| 2800 | */ |
| 2801 | #ifdef CONFIG_RT2X00_LIB_LEDS |
| 2802 | rt2800pci_init_led(rt2x00dev, &rt2x00dev->led_radio, LED_TYPE_RADIO); |
| 2803 | rt2800pci_init_led(rt2x00dev, &rt2x00dev->led_assoc, LED_TYPE_ASSOC); |
| 2804 | rt2800pci_init_led(rt2x00dev, &rt2x00dev->led_qual, LED_TYPE_QUALITY); |
| 2805 | |
| 2806 | rt2x00_eeprom_read(rt2x00dev, EEPROM_FREQ, &rt2x00dev->led_mcu_reg); |
| 2807 | #endif /* CONFIG_RT2X00_LIB_LEDS */ |
| 2808 | |
| 2809 | return 0; |
| 2810 | } |
| 2811 | |
| 2812 | /* |
| 2813 | * RF value list for rt2860 |
| 2814 | * Supports: 2.4 GHz (all) & 5.2 GHz (RF2850 & RF2750) |
| 2815 | */ |
| 2816 | static const struct rf_channel rf_vals[] = { |
| 2817 | { 1, 0x18402ecc, 0x184c0786, 0x1816b455, 0x1800510b }, |
| 2818 | { 2, 0x18402ecc, 0x184c0786, 0x18168a55, 0x1800519f }, |
| 2819 | { 3, 0x18402ecc, 0x184c078a, 0x18168a55, 0x1800518b }, |
| 2820 | { 4, 0x18402ecc, 0x184c078a, 0x18168a55, 0x1800519f }, |
| 2821 | { 5, 0x18402ecc, 0x184c078e, 0x18168a55, 0x1800518b }, |
| 2822 | { 6, 0x18402ecc, 0x184c078e, 0x18168a55, 0x1800519f }, |
| 2823 | { 7, 0x18402ecc, 0x184c0792, 0x18168a55, 0x1800518b }, |
| 2824 | { 8, 0x18402ecc, 0x184c0792, 0x18168a55, 0x1800519f }, |
| 2825 | { 9, 0x18402ecc, 0x184c0796, 0x18168a55, 0x1800518b }, |
| 2826 | { 10, 0x18402ecc, 0x184c0796, 0x18168a55, 0x1800519f }, |
| 2827 | { 11, 0x18402ecc, 0x184c079a, 0x18168a55, 0x1800518b }, |
| 2828 | { 12, 0x18402ecc, 0x184c079a, 0x18168a55, 0x1800519f }, |
| 2829 | { 13, 0x18402ecc, 0x184c079e, 0x18168a55, 0x1800518b }, |
| 2830 | { 14, 0x18402ecc, 0x184c07a2, 0x18168a55, 0x18005193 }, |
| 2831 | |
| 2832 | /* 802.11 UNI / HyperLan 2 */ |
| 2833 | { 36, 0x18402ecc, 0x184c099a, 0x18158a55, 0x180ed1a3 }, |
| 2834 | { 38, 0x18402ecc, 0x184c099e, 0x18158a55, 0x180ed193 }, |
| 2835 | { 40, 0x18402ec8, 0x184c0682, 0x18158a55, 0x180ed183 }, |
| 2836 | { 44, 0x18402ec8, 0x184c0682, 0x18158a55, 0x180ed1a3 }, |
| 2837 | { 46, 0x18402ec8, 0x184c0686, 0x18158a55, 0x180ed18b }, |
| 2838 | { 48, 0x18402ec8, 0x184c0686, 0x18158a55, 0x180ed19b }, |
| 2839 | { 52, 0x18402ec8, 0x184c068a, 0x18158a55, 0x180ed193 }, |
| 2840 | { 54, 0x18402ec8, 0x184c068a, 0x18158a55, 0x180ed1a3 }, |
| 2841 | { 56, 0x18402ec8, 0x184c068e, 0x18158a55, 0x180ed18b }, |
| 2842 | { 60, 0x18402ec8, 0x184c0692, 0x18158a55, 0x180ed183 }, |
| 2843 | { 62, 0x18402ec8, 0x184c0692, 0x18158a55, 0x180ed193 }, |
| 2844 | { 64, 0x18402ec8, 0x184c0692, 0x18158a55, 0x180ed1a3 }, |
| 2845 | |
| 2846 | /* 802.11 HyperLan 2 */ |
| 2847 | { 100, 0x18402ec8, 0x184c06b2, 0x18178a55, 0x180ed783 }, |
| 2848 | { 102, 0x18402ec8, 0x184c06b2, 0x18578a55, 0x180ed793 }, |
| 2849 | { 104, 0x18402ec8, 0x185c06b2, 0x18578a55, 0x180ed1a3 }, |
| 2850 | { 108, 0x18402ecc, 0x185c0a32, 0x18578a55, 0x180ed193 }, |
| 2851 | { 110, 0x18402ecc, 0x184c0a36, 0x18178a55, 0x180ed183 }, |
| 2852 | { 112, 0x18402ecc, 0x184c0a36, 0x18178a55, 0x180ed19b }, |
| 2853 | { 116, 0x18402ecc, 0x184c0a3a, 0x18178a55, 0x180ed1a3 }, |
| 2854 | { 118, 0x18402ecc, 0x184c0a3e, 0x18178a55, 0x180ed193 }, |
| 2855 | { 120, 0x18402ec4, 0x184c0382, 0x18178a55, 0x180ed183 }, |
| 2856 | { 124, 0x18402ec4, 0x184c0382, 0x18178a55, 0x180ed193 }, |
| 2857 | { 126, 0x18402ec4, 0x184c0382, 0x18178a55, 0x180ed15b }, |
| 2858 | { 128, 0x18402ec4, 0x184c0382, 0x18178a55, 0x180ed1a3 }, |
| 2859 | { 132, 0x18402ec4, 0x184c0386, 0x18178a55, 0x180ed18b }, |
| 2860 | { 134, 0x18402ec4, 0x184c0386, 0x18178a55, 0x180ed193 }, |
| 2861 | { 136, 0x18402ec4, 0x184c0386, 0x18178a55, 0x180ed19b }, |
| 2862 | { 140, 0x18402ec4, 0x184c038a, 0x18178a55, 0x180ed183 }, |
| 2863 | |
| 2864 | /* 802.11 UNII */ |
| 2865 | { 149, 0x18402ec4, 0x184c038a, 0x18178a55, 0x180ed1a7 }, |
| 2866 | { 151, 0x18402ec4, 0x184c038e, 0x18178a55, 0x180ed187 }, |
| 2867 | { 153, 0x18402ec4, 0x184c038e, 0x18178a55, 0x180ed18f }, |
| 2868 | { 157, 0x18402ec4, 0x184c038e, 0x18178a55, 0x180ed19f }, |
| 2869 | { 159, 0x18402ec4, 0x184c038e, 0x18178a55, 0x180ed1a7 }, |
| 2870 | { 161, 0x18402ec4, 0x184c0392, 0x18178a55, 0x180ed187 }, |
| 2871 | { 165, 0x18402ec4, 0x184c0392, 0x18178a55, 0x180ed197 }, |
| 2872 | |
| 2873 | /* 802.11 Japan */ |
| 2874 | { 184, 0x15002ccc, 0x1500491e, 0x1509be55, 0x150c0a0b }, |
| 2875 | { 188, 0x15002ccc, 0x15004922, 0x1509be55, 0x150c0a13 }, |
| 2876 | { 192, 0x15002ccc, 0x15004926, 0x1509be55, 0x150c0a1b }, |
| 2877 | { 196, 0x15002ccc, 0x1500492a, 0x1509be55, 0x150c0a23 }, |
| 2878 | { 208, 0x15002ccc, 0x1500493a, 0x1509be55, 0x150c0a13 }, |
| 2879 | { 212, 0x15002ccc, 0x1500493e, 0x1509be55, 0x150c0a1b }, |
| 2880 | { 216, 0x15002ccc, 0x15004982, 0x1509be55, 0x150c0a23 }, |
| 2881 | }; |
| 2882 | |
| 2883 | static int rt2800pci_probe_hw_mode(struct rt2x00_dev *rt2x00dev) |
| 2884 | { |
| 2885 | struct hw_mode_spec *spec = &rt2x00dev->spec; |
| 2886 | struct channel_info *info; |
| 2887 | char *tx_power1; |
| 2888 | char *tx_power2; |
| 2889 | unsigned int i; |
| 2890 | u16 eeprom; |
| 2891 | |
| 2892 | /* |
| 2893 | * Initialize all hw fields. |
| 2894 | */ |
| 2895 | rt2x00dev->hw->flags = |
| 2896 | IEEE80211_HW_HOST_BROADCAST_PS_BUFFERING | |
| 2897 | IEEE80211_HW_SIGNAL_DBM | |
| 2898 | IEEE80211_HW_SUPPORTS_PS | |
| 2899 | IEEE80211_HW_PS_NULLFUNC_STACK; |
| 2900 | rt2x00dev->hw->extra_tx_headroom = TXWI_DESC_SIZE; |
| 2901 | |
| 2902 | SET_IEEE80211_DEV(rt2x00dev->hw, rt2x00dev->dev); |
| 2903 | SET_IEEE80211_PERM_ADDR(rt2x00dev->hw, |
| 2904 | rt2x00_eeprom_addr(rt2x00dev, |
| 2905 | EEPROM_MAC_ADDR_0)); |
| 2906 | |
| 2907 | rt2x00_eeprom_read(rt2x00dev, EEPROM_ANTENNA, &eeprom); |
| 2908 | |
| 2909 | /* |
| 2910 | * Initialize hw_mode information. |
| 2911 | */ |
| 2912 | spec->supported_bands = SUPPORT_BAND_2GHZ; |
| 2913 | spec->supported_rates = SUPPORT_RATE_CCK | SUPPORT_RATE_OFDM; |
| 2914 | |
| 2915 | if (rt2x00_rf(&rt2x00dev->chip, RF2820) || |
| 2916 | rt2x00_rf(&rt2x00dev->chip, RF2720) || |
| 2917 | rt2x00_rf(&rt2x00dev->chip, RF3020) || |
| 2918 | rt2x00_rf(&rt2x00dev->chip, RF3021) || |
| 2919 | rt2x00_rf(&rt2x00dev->chip, RF3022) || |
| 2920 | rt2x00_rf(&rt2x00dev->chip, RF2020) || |
| 2921 | rt2x00_rf(&rt2x00dev->chip, RF3052)) { |
| 2922 | spec->num_channels = 14; |
| 2923 | spec->channels = rf_vals; |
| 2924 | } else if (rt2x00_rf(&rt2x00dev->chip, RF2850) || |
| 2925 | rt2x00_rf(&rt2x00dev->chip, RF2750)) { |
| 2926 | spec->supported_bands |= SUPPORT_BAND_5GHZ; |
| 2927 | spec->num_channels = ARRAY_SIZE(rf_vals); |
| 2928 | spec->channels = rf_vals; |
| 2929 | } |
| 2930 | |
| 2931 | /* |
| 2932 | * Initialize HT information. |
| 2933 | */ |
| 2934 | spec->ht.ht_supported = true; |
| 2935 | spec->ht.cap = |
| 2936 | IEEE80211_HT_CAP_SUP_WIDTH_20_40 | |
| 2937 | IEEE80211_HT_CAP_GRN_FLD | |
| 2938 | IEEE80211_HT_CAP_SGI_20 | |
| 2939 | IEEE80211_HT_CAP_SGI_40 | |
| 2940 | IEEE80211_HT_CAP_TX_STBC | |
| 2941 | IEEE80211_HT_CAP_RX_STBC | |
| 2942 | IEEE80211_HT_CAP_PSMP_SUPPORT; |
| 2943 | spec->ht.ampdu_factor = 3; |
| 2944 | spec->ht.ampdu_density = 4; |
| 2945 | spec->ht.mcs.tx_params = |
| 2946 | IEEE80211_HT_MCS_TX_DEFINED | |
| 2947 | IEEE80211_HT_MCS_TX_RX_DIFF | |
| 2948 | ((rt2x00_get_field16(eeprom, EEPROM_ANTENNA_TXPATH) - 1) << |
| 2949 | IEEE80211_HT_MCS_TX_MAX_STREAMS_SHIFT); |
| 2950 | |
| 2951 | switch (rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RXPATH)) { |
| 2952 | case 3: |
| 2953 | spec->ht.mcs.rx_mask[2] = 0xff; |
| 2954 | case 2: |
| 2955 | spec->ht.mcs.rx_mask[1] = 0xff; |
| 2956 | case 1: |
| 2957 | spec->ht.mcs.rx_mask[0] = 0xff; |
| 2958 | spec->ht.mcs.rx_mask[4] = 0x1; /* MCS32 */ |
| 2959 | break; |
| 2960 | } |
| 2961 | |
| 2962 | /* |
| 2963 | * Create channel information array |
| 2964 | */ |
| 2965 | info = kzalloc(spec->num_channels * sizeof(*info), GFP_KERNEL); |
| 2966 | if (!info) |
| 2967 | return -ENOMEM; |
| 2968 | |
| 2969 | spec->channels_info = info; |
| 2970 | |
| 2971 | tx_power1 = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_BG1); |
| 2972 | tx_power2 = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_BG2); |
| 2973 | |
| 2974 | for (i = 0; i < 14; i++) { |
| 2975 | info[i].tx_power1 = TXPOWER_G_FROM_DEV(tx_power1[i]); |
| 2976 | info[i].tx_power2 = TXPOWER_G_FROM_DEV(tx_power2[i]); |
| 2977 | } |
| 2978 | |
| 2979 | if (spec->num_channels > 14) { |
| 2980 | tx_power1 = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_A1); |
| 2981 | tx_power2 = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_A2); |
| 2982 | |
| 2983 | for (i = 14; i < spec->num_channels; i++) { |
| 2984 | info[i].tx_power1 = TXPOWER_A_FROM_DEV(tx_power1[i]); |
| 2985 | info[i].tx_power2 = TXPOWER_A_FROM_DEV(tx_power2[i]); |
| 2986 | } |
| 2987 | } |
| 2988 | |
| 2989 | return 0; |
| 2990 | } |
| 2991 | |
Bartlomiej Zolnierkiewicz | b0a1eda | 2009-11-04 18:35:00 +0100 | [diff] [blame] | 2992 | static const struct rt2800_ops rt2800pci_rt2800_ops = { |
| 2993 | .register_read = rt2x00pci_register_read, |
| 2994 | .register_write = rt2x00pci_register_write, |
| 2995 | .register_write_lock = rt2x00pci_register_write, /* same for PCI */ |
| 2996 | |
| 2997 | .register_multiread = rt2x00pci_register_multiread, |
| 2998 | .register_multiwrite = rt2x00pci_register_multiwrite, |
| 2999 | |
| 3000 | .regbusy_read = rt2x00pci_regbusy_read, |
| 3001 | }; |
| 3002 | |
Ivo van Doorn | a9b3a9f | 2009-10-15 22:04:14 +0200 | [diff] [blame] | 3003 | static int rt2800pci_probe_hw(struct rt2x00_dev *rt2x00dev) |
| 3004 | { |
| 3005 | int retval; |
| 3006 | |
Bartlomiej Zolnierkiewicz | b0a1eda | 2009-11-04 18:35:00 +0100 | [diff] [blame] | 3007 | rt2x00dev->priv = (void *)&rt2800pci_rt2800_ops; |
| 3008 | |
Ivo van Doorn | a9b3a9f | 2009-10-15 22:04:14 +0200 | [diff] [blame] | 3009 | /* |
| 3010 | * Allocate eeprom data. |
| 3011 | */ |
| 3012 | retval = rt2800pci_validate_eeprom(rt2x00dev); |
| 3013 | if (retval) |
| 3014 | return retval; |
| 3015 | |
| 3016 | retval = rt2800pci_init_eeprom(rt2x00dev); |
| 3017 | if (retval) |
| 3018 | return retval; |
| 3019 | |
| 3020 | /* |
| 3021 | * Initialize hw specifications. |
| 3022 | */ |
| 3023 | retval = rt2800pci_probe_hw_mode(rt2x00dev); |
| 3024 | if (retval) |
| 3025 | return retval; |
| 3026 | |
| 3027 | /* |
| 3028 | * This device has multiple filters for control frames |
| 3029 | * and has a separate filter for PS Poll frames. |
| 3030 | */ |
| 3031 | __set_bit(DRIVER_SUPPORT_CONTROL_FILTERS, &rt2x00dev->flags); |
| 3032 | __set_bit(DRIVER_SUPPORT_CONTROL_FILTER_PSPOLL, &rt2x00dev->flags); |
| 3033 | |
| 3034 | /* |
| 3035 | * This device requires firmware. |
| 3036 | */ |
| 3037 | if (!rt2x00_rt(&rt2x00dev->chip, RT2880) && |
| 3038 | !rt2x00_rt(&rt2x00dev->chip, RT3052)) |
| 3039 | __set_bit(DRIVER_REQUIRE_FIRMWARE, &rt2x00dev->flags); |
| 3040 | __set_bit(DRIVER_REQUIRE_DMA, &rt2x00dev->flags); |
| 3041 | __set_bit(DRIVER_REQUIRE_L2PAD, &rt2x00dev->flags); |
| 3042 | if (!modparam_nohwcrypt) |
| 3043 | __set_bit(CONFIG_SUPPORT_HW_CRYPTO, &rt2x00dev->flags); |
| 3044 | |
| 3045 | /* |
| 3046 | * Set the rssi offset. |
| 3047 | */ |
| 3048 | rt2x00dev->rssi_offset = DEFAULT_RSSI_OFFSET; |
| 3049 | |
| 3050 | return 0; |
| 3051 | } |
| 3052 | |
| 3053 | /* |
| 3054 | * IEEE80211 stack callback functions. |
| 3055 | */ |
| 3056 | static void rt2800pci_get_tkip_seq(struct ieee80211_hw *hw, u8 hw_key_idx, |
| 3057 | u32 *iv32, u16 *iv16) |
| 3058 | { |
| 3059 | struct rt2x00_dev *rt2x00dev = hw->priv; |
| 3060 | struct mac_iveiv_entry iveiv_entry; |
| 3061 | u32 offset; |
| 3062 | |
| 3063 | offset = MAC_IVEIV_ENTRY(hw_key_idx); |
Bartlomiej Zolnierkiewicz | 4f2732c | 2009-11-04 18:33:27 +0100 | [diff] [blame] | 3064 | rt2800_register_multiread(rt2x00dev, offset, |
Ivo van Doorn | a9b3a9f | 2009-10-15 22:04:14 +0200 | [diff] [blame] | 3065 | &iveiv_entry, sizeof(iveiv_entry)); |
| 3066 | |
| 3067 | memcpy(&iveiv_entry.iv[0], iv16, sizeof(iv16)); |
| 3068 | memcpy(&iveiv_entry.iv[4], iv32, sizeof(iv32)); |
| 3069 | } |
| 3070 | |
| 3071 | static int rt2800pci_set_rts_threshold(struct ieee80211_hw *hw, u32 value) |
| 3072 | { |
| 3073 | struct rt2x00_dev *rt2x00dev = hw->priv; |
| 3074 | u32 reg; |
| 3075 | bool enabled = (value < IEEE80211_MAX_RTS_THRESHOLD); |
| 3076 | |
Bartlomiej Zolnierkiewicz | 9ca21eb | 2009-11-04 18:33:13 +0100 | [diff] [blame] | 3077 | rt2800_register_read(rt2x00dev, TX_RTS_CFG, ®); |
Ivo van Doorn | a9b3a9f | 2009-10-15 22:04:14 +0200 | [diff] [blame] | 3078 | rt2x00_set_field32(®, TX_RTS_CFG_RTS_THRES, value); |
Bartlomiej Zolnierkiewicz | 9ca21eb | 2009-11-04 18:33:13 +0100 | [diff] [blame] | 3079 | rt2800_register_write(rt2x00dev, TX_RTS_CFG, reg); |
Ivo van Doorn | a9b3a9f | 2009-10-15 22:04:14 +0200 | [diff] [blame] | 3080 | |
Bartlomiej Zolnierkiewicz | 9ca21eb | 2009-11-04 18:33:13 +0100 | [diff] [blame] | 3081 | rt2800_register_read(rt2x00dev, CCK_PROT_CFG, ®); |
Ivo van Doorn | a9b3a9f | 2009-10-15 22:04:14 +0200 | [diff] [blame] | 3082 | rt2x00_set_field32(®, CCK_PROT_CFG_RTS_TH_EN, enabled); |
Bartlomiej Zolnierkiewicz | 9ca21eb | 2009-11-04 18:33:13 +0100 | [diff] [blame] | 3083 | rt2800_register_write(rt2x00dev, CCK_PROT_CFG, reg); |
Ivo van Doorn | a9b3a9f | 2009-10-15 22:04:14 +0200 | [diff] [blame] | 3084 | |
Bartlomiej Zolnierkiewicz | 9ca21eb | 2009-11-04 18:33:13 +0100 | [diff] [blame] | 3085 | rt2800_register_read(rt2x00dev, OFDM_PROT_CFG, ®); |
Ivo van Doorn | a9b3a9f | 2009-10-15 22:04:14 +0200 | [diff] [blame] | 3086 | rt2x00_set_field32(®, OFDM_PROT_CFG_RTS_TH_EN, enabled); |
Bartlomiej Zolnierkiewicz | 9ca21eb | 2009-11-04 18:33:13 +0100 | [diff] [blame] | 3087 | rt2800_register_write(rt2x00dev, OFDM_PROT_CFG, reg); |
Ivo van Doorn | a9b3a9f | 2009-10-15 22:04:14 +0200 | [diff] [blame] | 3088 | |
Bartlomiej Zolnierkiewicz | 9ca21eb | 2009-11-04 18:33:13 +0100 | [diff] [blame] | 3089 | rt2800_register_read(rt2x00dev, MM20_PROT_CFG, ®); |
Ivo van Doorn | a9b3a9f | 2009-10-15 22:04:14 +0200 | [diff] [blame] | 3090 | rt2x00_set_field32(®, MM20_PROT_CFG_RTS_TH_EN, enabled); |
Bartlomiej Zolnierkiewicz | 9ca21eb | 2009-11-04 18:33:13 +0100 | [diff] [blame] | 3091 | rt2800_register_write(rt2x00dev, MM20_PROT_CFG, reg); |
Ivo van Doorn | a9b3a9f | 2009-10-15 22:04:14 +0200 | [diff] [blame] | 3092 | |
Bartlomiej Zolnierkiewicz | 9ca21eb | 2009-11-04 18:33:13 +0100 | [diff] [blame] | 3093 | rt2800_register_read(rt2x00dev, MM40_PROT_CFG, ®); |
Ivo van Doorn | a9b3a9f | 2009-10-15 22:04:14 +0200 | [diff] [blame] | 3094 | rt2x00_set_field32(®, MM40_PROT_CFG_RTS_TH_EN, enabled); |
Bartlomiej Zolnierkiewicz | 9ca21eb | 2009-11-04 18:33:13 +0100 | [diff] [blame] | 3095 | rt2800_register_write(rt2x00dev, MM40_PROT_CFG, reg); |
Ivo van Doorn | a9b3a9f | 2009-10-15 22:04:14 +0200 | [diff] [blame] | 3096 | |
Bartlomiej Zolnierkiewicz | 9ca21eb | 2009-11-04 18:33:13 +0100 | [diff] [blame] | 3097 | rt2800_register_read(rt2x00dev, GF20_PROT_CFG, ®); |
Ivo van Doorn | a9b3a9f | 2009-10-15 22:04:14 +0200 | [diff] [blame] | 3098 | rt2x00_set_field32(®, GF20_PROT_CFG_RTS_TH_EN, enabled); |
Bartlomiej Zolnierkiewicz | 9ca21eb | 2009-11-04 18:33:13 +0100 | [diff] [blame] | 3099 | rt2800_register_write(rt2x00dev, GF20_PROT_CFG, reg); |
Ivo van Doorn | a9b3a9f | 2009-10-15 22:04:14 +0200 | [diff] [blame] | 3100 | |
Bartlomiej Zolnierkiewicz | 9ca21eb | 2009-11-04 18:33:13 +0100 | [diff] [blame] | 3101 | rt2800_register_read(rt2x00dev, GF40_PROT_CFG, ®); |
Ivo van Doorn | a9b3a9f | 2009-10-15 22:04:14 +0200 | [diff] [blame] | 3102 | rt2x00_set_field32(®, GF40_PROT_CFG_RTS_TH_EN, enabled); |
Bartlomiej Zolnierkiewicz | 9ca21eb | 2009-11-04 18:33:13 +0100 | [diff] [blame] | 3103 | rt2800_register_write(rt2x00dev, GF40_PROT_CFG, reg); |
Ivo van Doorn | a9b3a9f | 2009-10-15 22:04:14 +0200 | [diff] [blame] | 3104 | |
| 3105 | return 0; |
| 3106 | } |
| 3107 | |
| 3108 | static int rt2800pci_conf_tx(struct ieee80211_hw *hw, u16 queue_idx, |
| 3109 | const struct ieee80211_tx_queue_params *params) |
| 3110 | { |
| 3111 | struct rt2x00_dev *rt2x00dev = hw->priv; |
| 3112 | struct data_queue *queue; |
| 3113 | struct rt2x00_field32 field; |
| 3114 | int retval; |
| 3115 | u32 reg; |
| 3116 | u32 offset; |
| 3117 | |
| 3118 | /* |
| 3119 | * First pass the configuration through rt2x00lib, that will |
| 3120 | * update the queue settings and validate the input. After that |
| 3121 | * we are free to update the registers based on the value |
| 3122 | * in the queue parameter. |
| 3123 | */ |
| 3124 | retval = rt2x00mac_conf_tx(hw, queue_idx, params); |
| 3125 | if (retval) |
| 3126 | return retval; |
| 3127 | |
| 3128 | /* |
| 3129 | * We only need to perform additional register initialization |
| 3130 | * for WMM queues/ |
| 3131 | */ |
| 3132 | if (queue_idx >= 4) |
| 3133 | return 0; |
| 3134 | |
| 3135 | queue = rt2x00queue_get_queue(rt2x00dev, queue_idx); |
| 3136 | |
| 3137 | /* Update WMM TXOP register */ |
| 3138 | offset = WMM_TXOP0_CFG + (sizeof(u32) * (!!(queue_idx & 2))); |
| 3139 | field.bit_offset = (queue_idx & 1) * 16; |
| 3140 | field.bit_mask = 0xffff << field.bit_offset; |
| 3141 | |
Bartlomiej Zolnierkiewicz | 9ca21eb | 2009-11-04 18:33:13 +0100 | [diff] [blame] | 3142 | rt2800_register_read(rt2x00dev, offset, ®); |
Ivo van Doorn | a9b3a9f | 2009-10-15 22:04:14 +0200 | [diff] [blame] | 3143 | rt2x00_set_field32(®, field, queue->txop); |
Bartlomiej Zolnierkiewicz | 9ca21eb | 2009-11-04 18:33:13 +0100 | [diff] [blame] | 3144 | rt2800_register_write(rt2x00dev, offset, reg); |
Ivo van Doorn | a9b3a9f | 2009-10-15 22:04:14 +0200 | [diff] [blame] | 3145 | |
| 3146 | /* Update WMM registers */ |
| 3147 | field.bit_offset = queue_idx * 4; |
| 3148 | field.bit_mask = 0xf << field.bit_offset; |
| 3149 | |
Bartlomiej Zolnierkiewicz | 9ca21eb | 2009-11-04 18:33:13 +0100 | [diff] [blame] | 3150 | rt2800_register_read(rt2x00dev, WMM_AIFSN_CFG, ®); |
Ivo van Doorn | a9b3a9f | 2009-10-15 22:04:14 +0200 | [diff] [blame] | 3151 | rt2x00_set_field32(®, field, queue->aifs); |
Bartlomiej Zolnierkiewicz | 9ca21eb | 2009-11-04 18:33:13 +0100 | [diff] [blame] | 3152 | rt2800_register_write(rt2x00dev, WMM_AIFSN_CFG, reg); |
Ivo van Doorn | a9b3a9f | 2009-10-15 22:04:14 +0200 | [diff] [blame] | 3153 | |
Bartlomiej Zolnierkiewicz | 9ca21eb | 2009-11-04 18:33:13 +0100 | [diff] [blame] | 3154 | rt2800_register_read(rt2x00dev, WMM_CWMIN_CFG, ®); |
Ivo van Doorn | a9b3a9f | 2009-10-15 22:04:14 +0200 | [diff] [blame] | 3155 | rt2x00_set_field32(®, field, queue->cw_min); |
Bartlomiej Zolnierkiewicz | 9ca21eb | 2009-11-04 18:33:13 +0100 | [diff] [blame] | 3156 | rt2800_register_write(rt2x00dev, WMM_CWMIN_CFG, reg); |
Ivo van Doorn | a9b3a9f | 2009-10-15 22:04:14 +0200 | [diff] [blame] | 3157 | |
Bartlomiej Zolnierkiewicz | 9ca21eb | 2009-11-04 18:33:13 +0100 | [diff] [blame] | 3158 | rt2800_register_read(rt2x00dev, WMM_CWMAX_CFG, ®); |
Ivo van Doorn | a9b3a9f | 2009-10-15 22:04:14 +0200 | [diff] [blame] | 3159 | rt2x00_set_field32(®, field, queue->cw_max); |
Bartlomiej Zolnierkiewicz | 9ca21eb | 2009-11-04 18:33:13 +0100 | [diff] [blame] | 3160 | rt2800_register_write(rt2x00dev, WMM_CWMAX_CFG, reg); |
Ivo van Doorn | a9b3a9f | 2009-10-15 22:04:14 +0200 | [diff] [blame] | 3161 | |
| 3162 | /* Update EDCA registers */ |
| 3163 | offset = EDCA_AC0_CFG + (sizeof(u32) * queue_idx); |
| 3164 | |
Bartlomiej Zolnierkiewicz | 9ca21eb | 2009-11-04 18:33:13 +0100 | [diff] [blame] | 3165 | rt2800_register_read(rt2x00dev, offset, ®); |
Ivo van Doorn | a9b3a9f | 2009-10-15 22:04:14 +0200 | [diff] [blame] | 3166 | rt2x00_set_field32(®, EDCA_AC0_CFG_TX_OP, queue->txop); |
| 3167 | rt2x00_set_field32(®, EDCA_AC0_CFG_AIFSN, queue->aifs); |
| 3168 | rt2x00_set_field32(®, EDCA_AC0_CFG_CWMIN, queue->cw_min); |
| 3169 | rt2x00_set_field32(®, EDCA_AC0_CFG_CWMAX, queue->cw_max); |
Bartlomiej Zolnierkiewicz | 9ca21eb | 2009-11-04 18:33:13 +0100 | [diff] [blame] | 3170 | rt2800_register_write(rt2x00dev, offset, reg); |
Ivo van Doorn | a9b3a9f | 2009-10-15 22:04:14 +0200 | [diff] [blame] | 3171 | |
| 3172 | return 0; |
| 3173 | } |
| 3174 | |
| 3175 | static u64 rt2800pci_get_tsf(struct ieee80211_hw *hw) |
| 3176 | { |
| 3177 | struct rt2x00_dev *rt2x00dev = hw->priv; |
| 3178 | u64 tsf; |
| 3179 | u32 reg; |
| 3180 | |
Bartlomiej Zolnierkiewicz | 9ca21eb | 2009-11-04 18:33:13 +0100 | [diff] [blame] | 3181 | rt2800_register_read(rt2x00dev, TSF_TIMER_DW1, ®); |
Ivo van Doorn | a9b3a9f | 2009-10-15 22:04:14 +0200 | [diff] [blame] | 3182 | tsf = (u64) rt2x00_get_field32(reg, TSF_TIMER_DW1_HIGH_WORD) << 32; |
Bartlomiej Zolnierkiewicz | 9ca21eb | 2009-11-04 18:33:13 +0100 | [diff] [blame] | 3183 | rt2800_register_read(rt2x00dev, TSF_TIMER_DW0, ®); |
Ivo van Doorn | a9b3a9f | 2009-10-15 22:04:14 +0200 | [diff] [blame] | 3184 | tsf |= rt2x00_get_field32(reg, TSF_TIMER_DW0_LOW_WORD); |
| 3185 | |
| 3186 | return tsf; |
| 3187 | } |
| 3188 | |
| 3189 | static const struct ieee80211_ops rt2800pci_mac80211_ops = { |
| 3190 | .tx = rt2x00mac_tx, |
| 3191 | .start = rt2x00mac_start, |
| 3192 | .stop = rt2x00mac_stop, |
| 3193 | .add_interface = rt2x00mac_add_interface, |
| 3194 | .remove_interface = rt2x00mac_remove_interface, |
| 3195 | .config = rt2x00mac_config, |
| 3196 | .configure_filter = rt2x00mac_configure_filter, |
| 3197 | .set_key = rt2x00mac_set_key, |
| 3198 | .get_stats = rt2x00mac_get_stats, |
| 3199 | .get_tkip_seq = rt2800pci_get_tkip_seq, |
| 3200 | .set_rts_threshold = rt2800pci_set_rts_threshold, |
| 3201 | .bss_info_changed = rt2x00mac_bss_info_changed, |
| 3202 | .conf_tx = rt2800pci_conf_tx, |
| 3203 | .get_tx_stats = rt2x00mac_get_tx_stats, |
| 3204 | .get_tsf = rt2800pci_get_tsf, |
| 3205 | .rfkill_poll = rt2x00mac_rfkill_poll, |
| 3206 | }; |
| 3207 | |
| 3208 | static const struct rt2x00lib_ops rt2800pci_rt2x00_ops = { |
| 3209 | .irq_handler = rt2800pci_interrupt, |
| 3210 | .probe_hw = rt2800pci_probe_hw, |
| 3211 | .get_firmware_name = rt2800pci_get_firmware_name, |
| 3212 | .check_firmware = rt2800pci_check_firmware, |
| 3213 | .load_firmware = rt2800pci_load_firmware, |
| 3214 | .initialize = rt2x00pci_initialize, |
| 3215 | .uninitialize = rt2x00pci_uninitialize, |
| 3216 | .get_entry_state = rt2800pci_get_entry_state, |
| 3217 | .clear_entry = rt2800pci_clear_entry, |
| 3218 | .set_device_state = rt2800pci_set_device_state, |
| 3219 | .rfkill_poll = rt2800pci_rfkill_poll, |
| 3220 | .link_stats = rt2800pci_link_stats, |
| 3221 | .reset_tuner = rt2800pci_reset_tuner, |
| 3222 | .link_tuner = rt2800pci_link_tuner, |
| 3223 | .write_tx_desc = rt2800pci_write_tx_desc, |
| 3224 | .write_tx_data = rt2x00pci_write_tx_data, |
| 3225 | .write_beacon = rt2800pci_write_beacon, |
| 3226 | .kick_tx_queue = rt2800pci_kick_tx_queue, |
| 3227 | .kill_tx_queue = rt2800pci_kill_tx_queue, |
| 3228 | .fill_rxdone = rt2800pci_fill_rxdone, |
| 3229 | .config_shared_key = rt2800pci_config_shared_key, |
| 3230 | .config_pairwise_key = rt2800pci_config_pairwise_key, |
| 3231 | .config_filter = rt2800pci_config_filter, |
| 3232 | .config_intf = rt2800pci_config_intf, |
| 3233 | .config_erp = rt2800pci_config_erp, |
| 3234 | .config_ant = rt2800pci_config_ant, |
| 3235 | .config = rt2800pci_config, |
| 3236 | }; |
| 3237 | |
| 3238 | static const struct data_queue_desc rt2800pci_queue_rx = { |
| 3239 | .entry_num = RX_ENTRIES, |
| 3240 | .data_size = AGGREGATION_SIZE, |
| 3241 | .desc_size = RXD_DESC_SIZE, |
| 3242 | .priv_size = sizeof(struct queue_entry_priv_pci), |
| 3243 | }; |
| 3244 | |
| 3245 | static const struct data_queue_desc rt2800pci_queue_tx = { |
| 3246 | .entry_num = TX_ENTRIES, |
| 3247 | .data_size = AGGREGATION_SIZE, |
| 3248 | .desc_size = TXD_DESC_SIZE, |
| 3249 | .priv_size = sizeof(struct queue_entry_priv_pci), |
| 3250 | }; |
| 3251 | |
| 3252 | static const struct data_queue_desc rt2800pci_queue_bcn = { |
| 3253 | .entry_num = 8 * BEACON_ENTRIES, |
| 3254 | .data_size = 0, /* No DMA required for beacons */ |
| 3255 | .desc_size = TXWI_DESC_SIZE, |
| 3256 | .priv_size = sizeof(struct queue_entry_priv_pci), |
| 3257 | }; |
| 3258 | |
| 3259 | static const struct rt2x00_ops rt2800pci_ops = { |
| 3260 | .name = KBUILD_MODNAME, |
| 3261 | .max_sta_intf = 1, |
| 3262 | .max_ap_intf = 8, |
| 3263 | .eeprom_size = EEPROM_SIZE, |
| 3264 | .rf_size = RF_SIZE, |
| 3265 | .tx_queues = NUM_TX_QUEUES, |
| 3266 | .rx = &rt2800pci_queue_rx, |
| 3267 | .tx = &rt2800pci_queue_tx, |
| 3268 | .bcn = &rt2800pci_queue_bcn, |
| 3269 | .lib = &rt2800pci_rt2x00_ops, |
| 3270 | .hw = &rt2800pci_mac80211_ops, |
| 3271 | #ifdef CONFIG_RT2X00_LIB_DEBUGFS |
| 3272 | .debugfs = &rt2800pci_rt2x00debug, |
| 3273 | #endif /* CONFIG_RT2X00_LIB_DEBUGFS */ |
| 3274 | }; |
| 3275 | |
| 3276 | /* |
| 3277 | * RT2800pci module information. |
| 3278 | */ |
| 3279 | static struct pci_device_id rt2800pci_device_table[] = { |
| 3280 | { PCI_DEVICE(0x1462, 0x891a), PCI_DEVICE_DATA(&rt2800pci_ops) }, |
| 3281 | { PCI_DEVICE(0x1432, 0x7708), PCI_DEVICE_DATA(&rt2800pci_ops) }, |
| 3282 | { PCI_DEVICE(0x1432, 0x7727), PCI_DEVICE_DATA(&rt2800pci_ops) }, |
| 3283 | { PCI_DEVICE(0x1432, 0x7728), PCI_DEVICE_DATA(&rt2800pci_ops) }, |
| 3284 | { PCI_DEVICE(0x1432, 0x7738), PCI_DEVICE_DATA(&rt2800pci_ops) }, |
| 3285 | { PCI_DEVICE(0x1432, 0x7748), PCI_DEVICE_DATA(&rt2800pci_ops) }, |
| 3286 | { PCI_DEVICE(0x1432, 0x7758), PCI_DEVICE_DATA(&rt2800pci_ops) }, |
| 3287 | { PCI_DEVICE(0x1432, 0x7768), PCI_DEVICE_DATA(&rt2800pci_ops) }, |
| 3288 | { PCI_DEVICE(0x1814, 0x0601), PCI_DEVICE_DATA(&rt2800pci_ops) }, |
| 3289 | { PCI_DEVICE(0x1814, 0x0681), PCI_DEVICE_DATA(&rt2800pci_ops) }, |
| 3290 | { PCI_DEVICE(0x1814, 0x0701), PCI_DEVICE_DATA(&rt2800pci_ops) }, |
| 3291 | { PCI_DEVICE(0x1814, 0x0781), PCI_DEVICE_DATA(&rt2800pci_ops) }, |
| 3292 | { PCI_DEVICE(0x1814, 0x3060), PCI_DEVICE_DATA(&rt2800pci_ops) }, |
| 3293 | { PCI_DEVICE(0x1814, 0x3062), PCI_DEVICE_DATA(&rt2800pci_ops) }, |
| 3294 | { PCI_DEVICE(0x1814, 0x3090), PCI_DEVICE_DATA(&rt2800pci_ops) }, |
| 3295 | { PCI_DEVICE(0x1814, 0x3091), PCI_DEVICE_DATA(&rt2800pci_ops) }, |
| 3296 | { PCI_DEVICE(0x1814, 0x3092), PCI_DEVICE_DATA(&rt2800pci_ops) }, |
| 3297 | { PCI_DEVICE(0x1814, 0x3562), PCI_DEVICE_DATA(&rt2800pci_ops) }, |
| 3298 | { PCI_DEVICE(0x1814, 0x3592), PCI_DEVICE_DATA(&rt2800pci_ops) }, |
| 3299 | { PCI_DEVICE(0x1a3b, 0x1059), PCI_DEVICE_DATA(&rt2800pci_ops) }, |
| 3300 | { 0, } |
| 3301 | }; |
| 3302 | |
| 3303 | MODULE_AUTHOR(DRV_PROJECT); |
| 3304 | MODULE_VERSION(DRV_VERSION); |
| 3305 | MODULE_DESCRIPTION("Ralink RT2800 PCI & PCMCIA Wireless LAN driver."); |
| 3306 | MODULE_SUPPORTED_DEVICE("Ralink RT2860 PCI & PCMCIA chipset based cards"); |
| 3307 | #ifdef CONFIG_RT2800PCI_PCI |
| 3308 | MODULE_FIRMWARE(FIRMWARE_RT2860); |
| 3309 | MODULE_DEVICE_TABLE(pci, rt2800pci_device_table); |
| 3310 | #endif /* CONFIG_RT2800PCI_PCI */ |
| 3311 | MODULE_LICENSE("GPL"); |
| 3312 | |
| 3313 | #ifdef CONFIG_RT2800PCI_WISOC |
| 3314 | #if defined(CONFIG_RALINK_RT288X) |
| 3315 | __rt2x00soc_probe(RT2880, &rt2800pci_ops); |
| 3316 | #elif defined(CONFIG_RALINK_RT305X) |
| 3317 | __rt2x00soc_probe(RT3052, &rt2800pci_ops); |
| 3318 | #endif |
| 3319 | |
| 3320 | static struct platform_driver rt2800soc_driver = { |
| 3321 | .driver = { |
| 3322 | .name = "rt2800_wmac", |
| 3323 | .owner = THIS_MODULE, |
| 3324 | .mod_name = KBUILD_MODNAME, |
| 3325 | }, |
| 3326 | .probe = __rt2x00soc_probe, |
| 3327 | .remove = __devexit_p(rt2x00soc_remove), |
| 3328 | .suspend = rt2x00soc_suspend, |
| 3329 | .resume = rt2x00soc_resume, |
| 3330 | }; |
| 3331 | #endif /* CONFIG_RT2800PCI_WISOC */ |
| 3332 | |
| 3333 | #ifdef CONFIG_RT2800PCI_PCI |
| 3334 | static struct pci_driver rt2800pci_driver = { |
| 3335 | .name = KBUILD_MODNAME, |
| 3336 | .id_table = rt2800pci_device_table, |
| 3337 | .probe = rt2x00pci_probe, |
| 3338 | .remove = __devexit_p(rt2x00pci_remove), |
| 3339 | .suspend = rt2x00pci_suspend, |
| 3340 | .resume = rt2x00pci_resume, |
| 3341 | }; |
| 3342 | #endif /* CONFIG_RT2800PCI_PCI */ |
| 3343 | |
| 3344 | static int __init rt2800pci_init(void) |
| 3345 | { |
| 3346 | int ret = 0; |
| 3347 | |
| 3348 | #ifdef CONFIG_RT2800PCI_WISOC |
| 3349 | ret = platform_driver_register(&rt2800soc_driver); |
| 3350 | if (ret) |
| 3351 | return ret; |
| 3352 | #endif |
| 3353 | #ifdef CONFIG_RT2800PCI_PCI |
| 3354 | ret = pci_register_driver(&rt2800pci_driver); |
| 3355 | if (ret) { |
| 3356 | #ifdef CONFIG_RT2800PCI_WISOC |
| 3357 | platform_driver_unregister(&rt2800soc_driver); |
| 3358 | #endif |
| 3359 | return ret; |
| 3360 | } |
| 3361 | #endif |
| 3362 | |
| 3363 | return ret; |
| 3364 | } |
| 3365 | |
| 3366 | static void __exit rt2800pci_exit(void) |
| 3367 | { |
| 3368 | #ifdef CONFIG_RT2800PCI_PCI |
| 3369 | pci_unregister_driver(&rt2800pci_driver); |
| 3370 | #endif |
| 3371 | #ifdef CONFIG_RT2800PCI_WISOC |
| 3372 | platform_driver_unregister(&rt2800soc_driver); |
| 3373 | #endif |
| 3374 | } |
| 3375 | |
| 3376 | module_init(rt2800pci_init); |
| 3377 | module_exit(rt2800pci_exit); |