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Pete Popove3ad1c22005-03-01 06:33:16 +00001/*
2 *
3 * BRIEF MODULE DESCRIPTION
4 * Alchemy Pb1200/Db1200 board setup.
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License as published by the
8 * Free Software Foundation; either version 2 of the License, or (at your
9 * option) any later version.
10 *
11 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
12 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
13 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
14 * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
15 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
16 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
17 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
18 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
19 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
20 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
21 *
22 * You should have received a copy of the GNU General Public License along
23 * with this program; if not, write to the Free Software Foundation, Inc.,
24 * 675 Mass Ave, Cambridge, MA 02139, USA.
25 */
Sergei Shtylyovce28f942008-04-23 22:43:55 +040026
Pete Popove3ad1c22005-03-01 06:33:16 +000027#include <linux/init.h>
28#include <linux/sched.h>
Yoichi Yuasa25b31cb2007-10-15 19:11:24 +090029
Yoichi Yuasa25b31cb2007-10-15 19:11:24 +090030#include <prom.h>
Sergei Shtylyovc3d1d5c2008-04-30 23:29:04 +040031#include <au1xxx.h>
Pete Popove3ad1c22005-03-01 06:33:16 +000032
33extern void _board_init_irq(void);
Yoichi Yuasa0d02f072006-11-01 18:40:15 +090034extern void (*board_init_irq)(void);
Pete Popove3ad1c22005-03-01 06:33:16 +000035
Ralf Baechle49a89ef2007-10-11 23:46:15 +010036void board_reset(void)
Pete Popove3ad1c22005-03-01 06:33:16 +000037{
38 bcsr->resets = 0;
Pete Popov64abf642005-09-14 16:17:59 +000039 bcsr->system = 0;
Pete Popove3ad1c22005-03-01 06:33:16 +000040}
41
42void __init board_setup(void)
43{
44 char *argptr = NULL;
Pete Popove3ad1c22005-03-01 06:33:16 +000045
46#if 0
Ralf Baechlef5cd9f12007-11-01 12:22:53 +000047 {
Sergei Shtylyovc3d1d5c2008-04-30 23:29:04 +040048 u32 pin_func;
Ralf Baechlef5cd9f12007-11-01 12:22:53 +000049
Sergei Shtylyovc3d1d5c2008-04-30 23:29:04 +040050 /*
51 * Enable PSC1 SYNC for AC97. Normaly done in audio driver,
52 * but it is board specific code, so put it here.
53 */
54 pin_func = au_readl(SYS_PINFUNC);
55 au_sync();
56 pin_func |= SYS_PF_MUST_BE_SET | SYS_PF_PSC1_S1;
57 au_writel(pin_func, SYS_PINFUNC);
Pete Popove3ad1c22005-03-01 06:33:16 +000058
Sergei Shtylyovc3d1d5c2008-04-30 23:29:04 +040059 au_writel(0, (u32)bcsr | 0x10); /* turn off PCMCIA power */
60 au_sync();
Ralf Baechlef5cd9f12007-11-01 12:22:53 +000061 }
Pete Popove3ad1c22005-03-01 06:33:16 +000062#endif
63
Pete Popov64abf642005-09-14 16:17:59 +000064#if defined(CONFIG_I2C_AU1550)
Pete Popove3ad1c22005-03-01 06:33:16 +000065 {
Sergei Shtylyovc3d1d5c2008-04-30 23:29:04 +040066 u32 freq0, clksrc;
67 u32 pin_func;
Pete Popove3ad1c22005-03-01 06:33:16 +000068
Sergei Shtylyovc3d1d5c2008-04-30 23:29:04 +040069 /* Select SMBus in CPLD */
70 bcsr->resets &= ~BCSR_RESETS_PCS0MUX;
Pete Popove3ad1c22005-03-01 06:33:16 +000071
Sergei Shtylyovc3d1d5c2008-04-30 23:29:04 +040072 pin_func = au_readl(SYS_PINFUNC);
73 au_sync();
74 pin_func &= ~(SYS_PINFUNC_P0A | SYS_PINFUNC_P0B);
75 /* Set GPIOs correctly */
76 pin_func |= 2 << 17;
77 au_writel(pin_func, SYS_PINFUNC);
78 au_sync();
Pete Popove3ad1c22005-03-01 06:33:16 +000079
Sergei Shtylyovc3d1d5c2008-04-30 23:29:04 +040080 /* The I2C driver depends on 50 MHz clock */
81 freq0 = au_readl(SYS_FREQCTRL0);
82 au_sync();
83 freq0 &= ~(SYS_FC_FRDIV1_MASK | SYS_FC_FS1 | SYS_FC_FE1);
84 freq0 |= 3 << SYS_FC_FRDIV1_BIT;
85 /* 396 MHz / (3 + 1) * 2 == 49.5 MHz */
86 au_writel(freq0, SYS_FREQCTRL0);
87 au_sync();
88 freq0 |= SYS_FC_FE1;
89 au_writel(freq0, SYS_FREQCTRL0);
90 au_sync();
Pete Popove3ad1c22005-03-01 06:33:16 +000091
Sergei Shtylyovc3d1d5c2008-04-30 23:29:04 +040092 clksrc = au_readl(SYS_CLKSRC);
93 au_sync();
94 clksrc &= ~(SYS_CS_CE0 | SYS_CS_DE0 | SYS_CS_ME0_MASK);
95 /* Bit 22 is EXTCLK0 for PSC0 */
96 clksrc |= SYS_CS_MUX_FQ1 << SYS_CS_ME0_BIT;
97 au_writel(clksrc, SYS_CLKSRC);
98 au_sync();
Pete Popove3ad1c22005-03-01 06:33:16 +000099 }
100#endif
101
102#ifdef CONFIG_FB_AU1200
103 argptr = prom_getcmdline();
104#ifdef CONFIG_MIPS_PB1200
Pete Popov64abf642005-09-14 16:17:59 +0000105 strcat(argptr, " video=au1200fb:panel:bs");
Pete Popove3ad1c22005-03-01 06:33:16 +0000106#endif
107#ifdef CONFIG_MIPS_DB1200
Pete Popov64abf642005-09-14 16:17:59 +0000108 strcat(argptr, " video=au1200fb:panel:bs");
Pete Popove3ad1c22005-03-01 06:33:16 +0000109#endif
110#endif
111
Sergei Shtylyovc3d1d5c2008-04-30 23:29:04 +0400112 /*
113 * The Pb1200 development board uses external MUX for PSC0 to
114 * support SMB/SPI. bcsr->resets bit 12: 0=SMB 1=SPI
115 */
Ralf Baechle6fec2e12007-07-13 06:33:09 +0100116#ifdef CONFIG_I2C_AU1550
Sergei Shtylyovc3d1d5c2008-04-30 23:29:04 +0400117 bcsr->resets &= ~BCSR_RESETS_PCS0MUX;
Pete Popove3ad1c22005-03-01 06:33:16 +0000118#endif
119 au_sync();
120
121#ifdef CONFIG_MIPS_PB1200
Sergei Shtylyovc3d1d5c2008-04-30 23:29:04 +0400122 printk(KERN_INFO "AMD Alchemy Pb1200 Board\n");
Pete Popove3ad1c22005-03-01 06:33:16 +0000123#endif
124#ifdef CONFIG_MIPS_DB1200
Sergei Shtylyovc3d1d5c2008-04-30 23:29:04 +0400125 printk(KERN_INFO "AMD Alchemy Db1200 Board\n");
Pete Popove3ad1c22005-03-01 06:33:16 +0000126#endif
Pete Popovebc7f122005-03-04 08:31:06 +0000127
Pete Popove3ad1c22005-03-01 06:33:16 +0000128 /* Setup Pb1200 External Interrupt Controller */
Yoichi Yuasa0d02f072006-11-01 18:40:15 +0900129 board_init_irq = _board_init_irq;
Pete Popove3ad1c22005-03-01 06:33:16 +0000130}
Pete Popov64abf642005-09-14 16:17:59 +0000131
Sergei Shtylyovc3d1d5c2008-04-30 23:29:04 +0400132int board_au1200fb_panel(void)
Pete Popov64abf642005-09-14 16:17:59 +0000133{
134 BCSR *bcsr = (BCSR *)BCSR_KSEG1_ADDR;
135 int p;
136
137 p = bcsr->switches;
138 p >>= 8;
139 p &= 0x0F;
140 return p;
141}
142
Sergei Shtylyovc3d1d5c2008-04-30 23:29:04 +0400143int board_au1200fb_panel_init(void)
Pete Popov64abf642005-09-14 16:17:59 +0000144{
145 /* Apply power */
Sergei Shtylyovc3d1d5c2008-04-30 23:29:04 +0400146 BCSR *bcsr = (BCSR *)BCSR_KSEG1_ADDR;
147
148 bcsr->board |= BCSR_BOARD_LCDVEE | BCSR_BOARD_LCDVDD | BCSR_BOARD_LCDBL;
149 /* printk(KERN_DEBUG "board_au1200fb_panel_init()\n"); */
Pete Popov64abf642005-09-14 16:17:59 +0000150 return 0;
151}
152
Sergei Shtylyovc3d1d5c2008-04-30 23:29:04 +0400153int board_au1200fb_panel_shutdown(void)
Pete Popov64abf642005-09-14 16:17:59 +0000154{
155 /* Remove power */
Sergei Shtylyovc3d1d5c2008-04-30 23:29:04 +0400156 BCSR *bcsr = (BCSR *)BCSR_KSEG1_ADDR;
157
158 bcsr->board &= ~(BCSR_BOARD_LCDVEE | BCSR_BOARD_LCDVDD |
159 BCSR_BOARD_LCDBL);
160 /* printk(KERN_DEBUG "board_au1200fb_panel_shutdown()\n"); */
Pete Popov64abf642005-09-14 16:17:59 +0000161 return 0;
162}