blob: 6e8daf4e1085bae1513d28059628fbb74513319b [file] [log] [blame]
Kalle Valo2f01a1f2009-04-29 23:33:31 +03001/*
Kalle Valo80301cd2009-06-12 14:17:39 +03002 * This file is part of wl1251
Kalle Valo2f01a1f2009-04-29 23:33:31 +03003 *
4 * Copyright (c) 1998-2007 Texas Instruments Incorporated
5 * Copyright (C) 2008 Nokia Corporation
6 *
7 * Contact: Kalle Valo <kalle.valo@nokia.com>
8 *
9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License
11 * version 2 as published by the Free Software Foundation.
12 *
13 * This program is distributed in the hope that it will be useful, but
14 * WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
16 * General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
21 * 02110-1301 USA
22 *
23 */
24
Kalle Valo80301cd2009-06-12 14:17:39 +030025#ifndef __WL1251_SPI_H__
26#define __WL1251_SPI_H__
Kalle Valo2f01a1f2009-04-29 23:33:31 +030027
Kalle Valoef2f8d42009-06-12 14:17:19 +030028#include "wl1251_cmd.h"
29#include "wl1251_acx.h"
Kalle Valo2f01a1f2009-04-29 23:33:31 +030030#include "reg.h"
31
32#define HW_ACCESS_MEMORY_MAX_RANGE 0x1FFC0
33
34#define HW_ACCESS_PART0_SIZE_ADDR 0x1FFC0
35#define HW_ACCESS_PART0_START_ADDR 0x1FFC4
36#define HW_ACCESS_PART1_SIZE_ADDR 0x1FFC8
37#define HW_ACCESS_PART1_START_ADDR 0x1FFCC
38
39#define HW_ACCESS_REGISTER_SIZE 4
40
41#define HW_ACCESS_PRAM_MAX_RANGE 0x3c000
42
43#define WSPI_CMD_READ 0x40000000
44#define WSPI_CMD_WRITE 0x00000000
45#define WSPI_CMD_FIXED 0x20000000
46#define WSPI_CMD_BYTE_LENGTH 0x1FFE0000
47#define WSPI_CMD_BYTE_LENGTH_OFFSET 17
48#define WSPI_CMD_BYTE_ADDR 0x0001FFFF
49
50#define WSPI_INIT_CMD_CRC_LEN 5
51
52#define WSPI_INIT_CMD_START 0x00
53#define WSPI_INIT_CMD_TX 0x40
54/* the extra bypass bit is sampled by the TNET as '1' */
55#define WSPI_INIT_CMD_BYPASS_BIT 0x80
56#define WSPI_INIT_CMD_FIXEDBUSY_LEN 0x07
57#define WSPI_INIT_CMD_EN_FIXEDBUSY 0x80
58#define WSPI_INIT_CMD_DIS_FIXEDBUSY 0x00
59#define WSPI_INIT_CMD_IOD 0x40
60#define WSPI_INIT_CMD_IP 0x20
61#define WSPI_INIT_CMD_CS 0x10
62#define WSPI_INIT_CMD_WS 0x08
63#define WSPI_INIT_CMD_WSPI 0x01
64#define WSPI_INIT_CMD_END 0x01
65
66#define WSPI_INIT_CMD_LEN 8
67
Kalle Valo2f01a1f2009-04-29 23:33:31 +030068#define HW_ACCESS_WSPI_FIXED_BUSY_LEN \
Kalle Valo80301cd2009-06-12 14:17:39 +030069 ((WL1251_BUSY_WORD_LEN - 4) / sizeof(u32))
Kalle Valo2f01a1f2009-04-29 23:33:31 +030070#define HW_ACCESS_WSPI_INIT_CMD_MASK 0
71
72
73/* Raw target IO, address is not translated */
Kalle Valo80301cd2009-06-12 14:17:39 +030074void wl1251_spi_write(struct wl1251 *wl, int addr, void *buf,
Juuso Oikarinen8ec8beb2009-06-12 14:16:00 +030075 size_t len, bool fixed);
Kalle Valo80301cd2009-06-12 14:17:39 +030076void wl1251_spi_read(struct wl1251 *wl, int addr, void *buf,
Luciano Coelho052a6252009-06-12 14:15:41 +030077 size_t len, bool fixed);
Kalle Valo2f01a1f2009-04-29 23:33:31 +030078
79/* Memory target IO, address is tranlated to partition 0 */
Kalle Valo80301cd2009-06-12 14:17:39 +030080void wl1251_spi_mem_read(struct wl1251 *wl, int addr, void *buf, size_t len);
81void wl1251_spi_mem_write(struct wl1251 *wl, int addr, void *buf, size_t len);
82u32 wl1251_mem_read32(struct wl1251 *wl, int addr);
83void wl1251_mem_write32(struct wl1251 *wl, int addr, u32 val);
Kalle Valo2f01a1f2009-04-29 23:33:31 +030084
85/* Registers IO */
Kalle Valo80301cd2009-06-12 14:17:39 +030086void wl1251_spi_reg_read(struct wl1251 *wl, int addr, void *buf, size_t len,
Luciano Coelho052a6252009-06-12 14:15:41 +030087 bool fixed);
Kalle Valo80301cd2009-06-12 14:17:39 +030088void wl1251_spi_reg_write(struct wl1251 *wl, int addr, void *buf, size_t len,
Juuso Oikarinen8ec8beb2009-06-12 14:16:00 +030089 bool fixed);
Kalle Valo80301cd2009-06-12 14:17:39 +030090u32 wl1251_reg_read32(struct wl1251 *wl, int addr);
91void wl1251_reg_write32(struct wl1251 *wl, int addr, u32 val);
Kalle Valo2f01a1f2009-04-29 23:33:31 +030092
93/* INIT and RESET words */
Kalle Valo80301cd2009-06-12 14:17:39 +030094void wl1251_spi_reset(struct wl1251 *wl);
95void wl1251_spi_init(struct wl1251 *wl);
96int wl1251_set_partition(struct wl1251 *wl,
Kalle Valo8d47cdb2009-06-12 14:14:41 +030097 u32 part_start, u32 part_size,
98 u32 reg_start, u32 reg_size);
Kalle Valo2f01a1f2009-04-29 23:33:31 +030099
Kalle Valo80301cd2009-06-12 14:17:39 +0300100static inline u32 wl1251_read32(struct wl1251 *wl, int addr)
Kalle Valo2f01a1f2009-04-29 23:33:31 +0300101{
Kalle Valo80301cd2009-06-12 14:17:39 +0300102 wl1251_spi_read(wl, addr, &wl->buffer_32,
Luciano Coelho052a6252009-06-12 14:15:41 +0300103 sizeof(wl->buffer_32), false);
Kalle Valo2f01a1f2009-04-29 23:33:31 +0300104
Kalle Valo1d3b8132009-06-12 14:14:28 +0300105 return wl->buffer_32;
Kalle Valo2f01a1f2009-04-29 23:33:31 +0300106}
107
Kalle Valo80301cd2009-06-12 14:17:39 +0300108static inline void wl1251_write32(struct wl1251 *wl, int addr, u32 val)
Kalle Valo2f01a1f2009-04-29 23:33:31 +0300109{
Kalle Valo1d3b8132009-06-12 14:14:28 +0300110 wl->buffer_32 = val;
Kalle Valo80301cd2009-06-12 14:17:39 +0300111 wl1251_spi_write(wl, addr, &wl->buffer_32,
Juuso Oikarinen8ec8beb2009-06-12 14:16:00 +0300112 sizeof(wl->buffer_32), false);
Kalle Valo2f01a1f2009-04-29 23:33:31 +0300113}
114
Kalle Valo80301cd2009-06-12 14:17:39 +0300115#endif /* __WL1251_SPI_H__ */