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gerrit-public.fairphone.software / kernel / msm / 80928860941023bb37e9c61927395d0eb753bc3b / . / drivers / net / ll_temac.h
blob: 1af66a1e6911e8c0589c647a210e5425810628a8 [file] [log] [blame]
Grant Likely92744982009-04-25 12:53:39 +0000[diff] [blame]1
2#ifndef XILINX_LL_TEMAC_H
3#define XILINX_LL_TEMAC_H
4
5#include <linux/netdevice.h>
6#include <linux/of.h>
7#include <linux/spinlock.h>
8#include <asm/dcr.h>
9#include <asm/dcr-regs.h>
10
11/* packet size info */
12#define XTE_HDR_SIZE 14 /* size of Ethernet header */
13#define XTE_TRL_SIZE 4 /* size of Ethernet trailer (FCS) */
14#define XTE_JUMBO_MTU 9000
15#define XTE_MAX_JUMBO_FRAME_SIZE (XTE_JUMBO_MTU + XTE_HDR_SIZE + XTE_TRL_SIZE)
16
17/* Configuration options */
18
19/* Accept all incoming packets.
20 * This option defaults to disabled (cleared) */
21#define XTE_OPTION_PROMISC (1 << 0)
22/* Jumbo frame support for Tx & Rx.
23 * This option defaults to disabled (cleared) */
24#define XTE_OPTION_JUMBO (1 << 1)
25/* VLAN Rx & Tx frame support.
26 * This option defaults to disabled (cleared) */
27#define XTE_OPTION_VLAN (1 << 2)
28/* Enable recognition of flow control frames on Rx
29 * This option defaults to enabled (set) */
30#define XTE_OPTION_FLOW_CONTROL (1 << 4)
31/* Strip FCS and PAD from incoming frames.
32 * Note: PAD from VLAN frames is not stripped.
33 * This option defaults to disabled (set) */
34#define XTE_OPTION_FCS_STRIP (1 << 5)
35/* Generate FCS field and add PAD automatically for outgoing frames.
36 * This option defaults to enabled (set) */
37#define XTE_OPTION_FCS_INSERT (1 << 6)
38/* Enable Length/Type error checking for incoming frames. When this option is
39set, the MAC will filter frames that have a mismatched type/length field
40and if XTE_OPTION_REPORT_RXERR is set, the user is notified when these
41types of frames are encountered. When this option is cleared, the MAC will
42allow these types of frames to be received.
43This option defaults to enabled (set) */
44#define XTE_OPTION_LENTYPE_ERR (1 << 7)
45/* Enable the transmitter.
46 * This option defaults to enabled (set) */
47#define XTE_OPTION_TXEN (1 << 11)
48/* Enable the receiver
49* This option defaults to enabled (set) */
50#define XTE_OPTION_RXEN (1 << 12)
51
52/* Default options set when device is initialized or reset */
53#define XTE_OPTION_DEFAULTS \
54 (XTE_OPTION_TXEN | \
55 XTE_OPTION_FLOW_CONTROL | \
56 XTE_OPTION_RXEN)
57
58/* XPS_LL_TEMAC SDMA registers definition */
59
60#define TX_NXTDESC_PTR 0x00 /* r */
61#define TX_CURBUF_ADDR 0x01 /* r */
62#define TX_CURBUF_LENGTH 0x02 /* r */
63#define TX_CURDESC_PTR 0x03 /* rw */
64#define TX_TAILDESC_PTR 0x04 /* rw */
65#define TX_CHNL_CTRL 0x05 /* rw */
66/*
67 0:7 24:31 IRQTimeout
68 8:15 16:23 IRQCount
69 16:20 11:15 Reserved
70 21 10 0
71 22 9 UseIntOnEnd
72 23 8 LdIRQCnt
73 24 7 IRQEn
74 25:28 3:6 Reserved
75 29 2 IrqErrEn
76 30 1 IrqDlyEn
77 31 0 IrqCoalEn
78*/
79#define CHNL_CTRL_IRQ_IOE (1 << 9)
80#define CHNL_CTRL_IRQ_EN (1 << 7)
81#define CHNL_CTRL_IRQ_ERR_EN (1 << 2)
82#define CHNL_CTRL_IRQ_DLY_EN (1 << 1)
83#define CHNL_CTRL_IRQ_COAL_EN (1 << 0)
84#define TX_IRQ_REG 0x06 /* rw */
85/*
86 0:7 24:31 DltTmrValue
87 8:15 16:23 ClscCntrValue
88 16:17 14:15 Reserved
89 18:21 10:13 ClscCnt
90 22:23 8:9 DlyCnt
91 24:28 3::7 Reserved
92 29 2 ErrIrq
93 30 1 DlyIrq
94 31 0 CoalIrq
95 */
96#define TX_CHNL_STS 0x07 /* r */
97/*
98 0:9 22:31 Reserved
99 10 21 TailPErr
100 11 20 CmpErr
101 12 19 AddrErr
102 13 18 NxtPErr
103 14 17 CurPErr
104 15 16 BsyWr
105 16:23 8:15 Reserved
106 24 7 Error
107 25 6 IOE
108 26 5 SOE
109 27 4 Cmplt
110 28 3 SOP
111 29 2 EOP
112 30 1 EngBusy
113 31 0 Reserved
114*/
115
116#define RX_NXTDESC_PTR 0x08 /* r */
117#define RX_CURBUF_ADDR 0x09 /* r */
118#define RX_CURBUF_LENGTH 0x0a /* r */
119#define RX_CURDESC_PTR 0x0b /* rw */
120#define RX_TAILDESC_PTR 0x0c /* rw */
121#define RX_CHNL_CTRL 0x0d /* rw */
122/*
123 0:7 24:31 IRQTimeout
124 8:15 16:23 IRQCount
125 16:20 11:15 Reserved
126 21 10 0
127 22 9 UseIntOnEnd
128 23 8 LdIRQCnt
129 24 7 IRQEn
130 25:28 3:6 Reserved
131 29 2 IrqErrEn
132 30 1 IrqDlyEn
133 31 0 IrqCoalEn
134 */
135#define RX_IRQ_REG 0x0e /* rw */
136#define IRQ_COAL (1 << 0)
137#define IRQ_DLY (1 << 1)
138#define IRQ_ERR (1 << 2)
139#define IRQ_DMAERR (1 << 7) /* this is not documented ??? */
140/*
141 0:7 24:31 DltTmrValue
142 8:15 16:23 ClscCntrValue
143 16:17 14:15 Reserved
144 18:21 10:13 ClscCnt
145 22:23 8:9 DlyCnt
146 24:28 3::7 Reserved
147*/
148#define RX_CHNL_STS 0x0f /* r */
149#define CHNL_STS_ENGBUSY (1 << 1)
150#define CHNL_STS_EOP (1 << 2)
151#define CHNL_STS_SOP (1 << 3)
152#define CHNL_STS_CMPLT (1 << 4)
153#define CHNL_STS_SOE (1 << 5)
154#define CHNL_STS_IOE (1 << 6)
155#define CHNL_STS_ERR (1 << 7)
156
157#define CHNL_STS_BSYWR (1 << 16)
158#define CHNL_STS_CURPERR (1 << 17)
159#define CHNL_STS_NXTPERR (1 << 18)
160#define CHNL_STS_ADDRERR (1 << 19)
161#define CHNL_STS_CMPERR (1 << 20)
162#define CHNL_STS_TAILERR (1 << 21)
163/*
164 0:9 22:31 Reserved
165 10 21 TailPErr
166 11 20 CmpErr
167 12 19 AddrErr
168 13 18 NxtPErr
169 14 17 CurPErr
170 15 16 BsyWr
171 16:23 8:15 Reserved
172 24 7 Error
173 25 6 IOE
174 26 5 SOE
175 27 4 Cmplt
176 28 3 SOP
177 29 2 EOP
178 30 1 EngBusy
179 31 0 Reserved
180*/
181
182#define DMA_CONTROL_REG 0x10 /* rw */
183#define DMA_CONTROL_RST (1 << 0)
184#define DMA_TAIL_ENABLE (1 << 2)
185
186/* XPS_LL_TEMAC direct registers definition */
187
188#define XTE_RAF0_OFFSET 0x00
189#define RAF0_RST (1 << 0)
190#define RAF0_MCSTREJ (1 << 1)
191#define RAF0_BCSTREJ (1 << 2)
192#define XTE_TPF0_OFFSET 0x04
193#define XTE_IFGP0_OFFSET 0x08
194#define XTE_ISR0_OFFSET 0x0c
195#define ISR0_HARDACSCMPLT (1 << 0)
196#define ISR0_AUTONEG (1 << 1)
197#define ISR0_RXCMPLT (1 << 2)
198#define ISR0_RXREJ (1 << 3)
199#define ISR0_RXFIFOOVR (1 << 4)
200#define ISR0_TXCMPLT (1 << 5)
201#define ISR0_RXDCMLCK (1 << 6)
202
203#define XTE_IPR0_OFFSET 0x10
204#define XTE_IER0_OFFSET 0x14
205
206#define XTE_MSW0_OFFSET 0x20
207#define XTE_LSW0_OFFSET 0x24
208#define XTE_CTL0_OFFSET 0x28
209#define XTE_RDY0_OFFSET 0x2c
210
211#define XTE_RSE_MIIM_RR_MASK 0x0002
212#define XTE_RSE_MIIM_WR_MASK 0x0004
213#define XTE_RSE_CFG_RR_MASK 0x0020
214#define XTE_RSE_CFG_WR_MASK 0x0040
215#define XTE_RDY0_HARD_ACS_RDY_MASK (0x10000)
216
217/* XPS_LL_TEMAC indirect registers offset definition */
218
219#define XTE_RXC0_OFFSET 0x00000200 /* Rx configuration word 0 */
220#define XTE_RXC1_OFFSET 0x00000240 /* Rx configuration word 1 */
221#define XTE_RXC1_RXRST_MASK (1 << 31) /* Receiver reset */
222#define XTE_RXC1_RXJMBO_MASK (1 << 30) /* Jumbo frame enable */
223#define XTE_RXC1_RXFCS_MASK (1 << 29) /* FCS not stripped */
224#define XTE_RXC1_RXEN_MASK (1 << 28) /* Receiver enable */
225#define XTE_RXC1_RXVLAN_MASK (1 << 27) /* VLAN enable */
226#define XTE_RXC1_RXHD_MASK (1 << 26) /* Half duplex */
227#define XTE_RXC1_RXLT_MASK (1 << 25) /* Length/type check disable */
228
229#define XTE_TXC_OFFSET 0x00000280 /* Tx configuration */
230#define XTE_TXC_TXRST_MASK (1 << 31) /* Transmitter reset */
231#define XTE_TXC_TXJMBO_MASK (1 << 30) /* Jumbo frame enable */
232#define XTE_TXC_TXFCS_MASK (1 << 29) /* Generate FCS */
233#define XTE_TXC_TXEN_MASK (1 << 28) /* Transmitter enable */
234#define XTE_TXC_TXVLAN_MASK (1 << 27) /* VLAN enable */
235#define XTE_TXC_TXHD_MASK (1 << 26) /* Half duplex */
236
237#define XTE_FCC_OFFSET 0x000002C0 /* Flow control config */
238#define XTE_FCC_RXFLO_MASK (1 << 29) /* Rx flow control enable */
239#define XTE_FCC_TXFLO_MASK (1 << 30) /* Tx flow control enable */
240
241#define XTE_EMCFG_OFFSET 0x00000300 /* EMAC configuration */
242#define XTE_EMCFG_LINKSPD_MASK 0xC0000000 /* Link speed */
243#define XTE_EMCFG_HOSTEN_MASK (1 << 26) /* Host interface enable */
244#define XTE_EMCFG_LINKSPD_10 0x00000000 /* 10 Mbit LINKSPD_MASK */
245#define XTE_EMCFG_LINKSPD_100 (1 << 30) /* 100 Mbit LINKSPD_MASK */
246#define XTE_EMCFG_LINKSPD_1000 (1 << 31) /* 1000 Mbit LINKSPD_MASK */
247
248#define XTE_GMIC_OFFSET 0x00000320 /* RGMII/SGMII config */
249#define XTE_MC_OFFSET 0x00000340 /* MDIO configuration */
250#define XTE_UAW0_OFFSET 0x00000380 /* Unicast address word 0 */
251#define XTE_UAW1_OFFSET 0x00000384 /* Unicast address word 1 */
252
253#define XTE_MAW0_OFFSET 0x00000388 /* Multicast addr word 0 */
254#define XTE_MAW1_OFFSET 0x0000038C /* Multicast addr word 1 */
255#define XTE_AFM_OFFSET 0x00000390 /* Promiscuous mode */
256#define XTE_AFM_EPPRM_MASK (1 << 31) /* Promiscuous mode enable */
257
258/* Interrupt Request status */
259#define XTE_TIS_OFFSET 0x000003A0
260#define TIS_FRIS (1 << 0)
261#define TIS_MRIS (1 << 1)
262#define TIS_MWIS (1 << 2)
263#define TIS_ARIS (1 << 3)
264#define TIS_AWIS (1 << 4)
265#define TIS_CRIS (1 << 5)
266#define TIS_CWIS (1 << 6)
267
268#define XTE_TIE_OFFSET 0x000003A4 /* Interrupt enable */
269
270/** MII Mamagement Control register (MGTCR) */
271#define XTE_MGTDR_OFFSET 0x000003B0 /* MII data */
272#define XTE_MIIMAI_OFFSET 0x000003B4 /* MII control */
273
274#define CNTLREG_WRITE_ENABLE_MASK 0x8000
275#define CNTLREG_EMAC1SEL_MASK 0x0400
276#define CNTLREG_ADDRESSCODE_MASK 0x03ff
277
278/* CDMAC descriptor status bit definitions */
279
280#define STS_CTRL_APP0_ERR (1 << 31)
281#define STS_CTRL_APP0_IRQONEND (1 << 30)
282/* undoccumented */
283#define STS_CTRL_APP0_STOPONEND (1 << 29)
284#define STS_CTRL_APP0_CMPLT (1 << 28)
285#define STS_CTRL_APP0_SOP (1 << 27)
286#define STS_CTRL_APP0_EOP (1 << 26)
287#define STS_CTRL_APP0_ENGBUSY (1 << 25)
288/* undocumented */
289#define STS_CTRL_APP0_ENGRST (1 << 24)
290
291#define TX_CONTROL_CALC_CSUM_MASK 1
292
293#define XTE_ALIGN 32
294#define BUFFER_ALIGN(adr) ((XTE_ALIGN - ((u32) adr)) % XTE_ALIGN)
295
296#define MULTICAST_CAM_TABLE_NUM 4
297
298/* TX/RX CURDESC_PTR points to first descriptor */
299/* TX/RX TAILDESC_PTR points to last descriptor in linked list */
300
301/**
302 * struct cdmac_bd - LocalLink buffer descriptor format
303 *
304 * app0 bits:
305 * 0 Error
306 * 1 IrqOnEnd generate an interrupt at completion of DMA op
307 * 2 reserved
308 * 3 completed Current descriptor completed
309 * 4 SOP TX - marks first desc/ RX marks first desct
310 * 5 EOP TX marks last desc/RX marks last desc
311 * 6 EngBusy DMA is processing
312 * 7 reserved
313 * 8:31 application specific
314 */
315struct cdmac_bd {
316 u32 next; /* Physical address of next buffer descriptor */
317 u32 phys;
318 u32 len;
319 u32 app0;
320 u32 app1; /* TX start << 16 | insert */
321 u32 app2; /* TX csum */
322 u32 app3;
323 u32 app4; /* skb for TX length for RX */
324};
325
326struct temac_local {
327 struct net_device *ndev;
328 struct device *dev;
329
330 /* Connection to PHY device */
331 struct phy_device *phy_dev; /* Pointer to PHY device */
332 struct device_node *phy_node;
333
334 /* MDIO bus data */
335 struct mii_bus *mii_bus; /* MII bus reference */
336 int mdio_irqs[PHY_MAX_ADDR]; /* IRQs table for MDIO bus */
337
338 /* IO registers and IRQs */
339 void __iomem *regs;
340 dcr_host_t sdma_dcrs;
341 int tx_irq;
342 int rx_irq;
343 int emac_num;
344
345 struct sk_buff **rx_skb;
346 spinlock_t rx_lock;
347 struct mutex indirect_mutex;
348 u32 options; /* Current options word */
349 int last_link;
350
351 /* Buffer descriptors */
352 struct cdmac_bd *tx_bd_v;
353 dma_addr_t tx_bd_p;
354 struct cdmac_bd *rx_bd_v;
355 dma_addr_t rx_bd_p;
356 int tx_bd_ci;
357 int tx_bd_next;
358 int tx_bd_tail;
359 int rx_bd_ci;
360};
361
362/* xilinx_temac.c */
363u32 temac_ior(struct temac_local *lp, int offset);
364void temac_iow(struct temac_local *lp, int offset, u32 value);
365int temac_indirect_busywait(struct temac_local *lp);
366u32 temac_indirect_in32(struct temac_local *lp, int reg);
367void temac_indirect_out32(struct temac_local *lp, int reg, u32 value);
368
369
370/* xilinx_temac_mdio.c */
371int temac_mdio_setup(struct temac_local *lp, struct device_node *np);
372void temac_mdio_teardown(struct temac_local *lp);
373
374#endif /* XILINX_LL_TEMAC_H */