| Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 1 | /* Copyright (c) 2011, Code Aurora Forum. All rights reserved. |
| 2 | * |
| 3 | * This program is free software; you can redistribute it and/or modify |
| 4 | * it under the terms of the GNU General Public License version 2 and |
| 5 | * only version 2 as published by the Free Software Foundation. |
| 6 | * |
| 7 | * This program is distributed in the hope that it will be useful, |
| 8 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 9 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 10 | * GNU General Public License for more details. |
| 11 | */ |
| 12 | |
| 13 | #ifndef __ASM_ARCH_MSM_IRQS_8064_H |
| 14 | #define __ASM_ARCH_MSM_IRQS_8064_H |
| 15 | |
| 16 | /* MSM ACPU Interrupt Numbers */ |
| 17 | |
| 18 | /* |
| 19 | * 0-15: STI/SGI (software triggered/generated interrupts) |
| 20 | * 16-31: PPI (private peripheral interrupts) |
| 21 | * 32+: SPI (shared peripheral interrupts) |
| 22 | */ |
| 23 | |
| 24 | #define GIC_PPI_START 16 |
| 25 | #define GIC_SPI_START 32 |
| 26 | |
| 27 | #define INT_VGIC (GIC_PPI_START + 0) |
| 28 | #define INT_DEBUG_TIMER_EXP (GIC_PPI_START + 1) |
| 29 | #define INT_GP_TIMER_EXP (GIC_PPI_START + 2) |
| 30 | #define INT_GP_TIMER2_EXP (GIC_PPI_START + 3) |
| 31 | #define WDT0_ACCSCSSNBARK_INT (GIC_PPI_START + 4) |
| 32 | #define WDT1_ACCSCSSNBARK_INT (GIC_PPI_START + 5) |
| 33 | #define AVS_SVICINT (GIC_PPI_START + 6) |
| 34 | #define AVS_SVICINTSWDONE (GIC_PPI_START + 7) |
| 35 | #define CPU_DBGCPUXCOMMRXFULL (GIC_PPI_START + 8) |
| 36 | #define CPU_DBGCPUXCOMMTXEMPTY (GIC_PPI_START + 9) |
| 37 | #define INT_ARMQC_PERFMON (GIC_PPI_START + 10) |
| 38 | #define SC_AVSCPUXDOWN (GIC_PPI_START + 11) |
| 39 | #define SC_AVSCPUXUP (GIC_PPI_START + 12) |
| 40 | #define SC_SICCPUXACGIRPTREQ (GIC_PPI_START + 13) |
| 41 | #define SC_SICCPUXEXTFAULTIRPTREQ (GIC_PPI_START + 14) |
| 42 | /* PPI 15 is unused */ |
| 43 | |
| 44 | #define APCC_QGICACGIRPTREQ (GIC_SPI_START + 0) |
| 45 | #define APCC_QGICL2PERFMONIRPTREQ (GIC_SPI_START + 1) |
| 46 | #define SC_SICL2PERFMONIRPTREQ APCC_QGICL2PERFMONIRPTREQ |
| 47 | #define APCC_QGICL2IRPTREQ (GIC_SPI_START + 2) |
| 48 | #define APCC_QGICMPUIRPTREQ (GIC_SPI_START + 3) |
| 49 | #define TLMM_MSM_DIR_CONN_IRQ_0 (GIC_SPI_START + 4) |
| 50 | #define TLMM_MSM_DIR_CONN_IRQ_1 (GIC_SPI_START + 5) |
| 51 | #define TLMM_MSM_DIR_CONN_IRQ_2 (GIC_SPI_START + 6) |
| 52 | #define TLMM_MSM_DIR_CONN_IRQ_3 (GIC_SPI_START + 7) |
| 53 | #define TLMM_MSM_DIR_CONN_IRQ_4 (GIC_SPI_START + 8) |
| 54 | #define TLMM_MSM_DIR_CONN_IRQ_5 (GIC_SPI_START + 9) |
| 55 | #define TLMM_MSM_DIR_CONN_IRQ_6 (GIC_SPI_START + 10) |
| 56 | #define TLMM_MSM_DIR_CONN_IRQ_7 (GIC_SPI_START + 11) |
| 57 | #define TLMM_MSM_DIR_CONN_IRQ_8 (GIC_SPI_START + 12) |
| 58 | #define TLMM_MSM_DIR_CONN_IRQ_9 (GIC_SPI_START + 13) |
| 59 | #define PM8921_SEC_IRQ_N (GIC_SPI_START + 14) |
| 60 | #define PM8018_SEC_IRQ_N (GIC_SPI_START + 15) |
| 61 | #define TLMM_MSM_SUMMARY_IRQ (GIC_SPI_START + 16) |
| 62 | #define SPDM_RT_1_IRQ (GIC_SPI_START + 17) |
| 63 | #define SPDM_DIAG_IRQ (GIC_SPI_START + 18) |
| 64 | #define RPM_APCC_CPU0_GP_HIGH_IRQ (GIC_SPI_START + 19) |
| 65 | #define RPM_APCC_CPU0_GP_MEDIUM_IRQ (GIC_SPI_START + 20) |
| 66 | #define RPM_APCC_CPU0_GP_LOW_IRQ (GIC_SPI_START + 21) |
| 67 | #define RPM_APCC_CPU0_WAKE_UP_IRQ (GIC_SPI_START + 22) |
| 68 | #define RPM_APCC_CPU1_GP_HIGH_IRQ (GIC_SPI_START + 23) |
| 69 | #define RPM_APCC_CPU1_GP_MEDIUM_IRQ (GIC_SPI_START + 24) |
| 70 | #define RPM_APCC_CPU1_GP_LOW_IRQ (GIC_SPI_START + 25) |
| 71 | #define RPM_APCC_CPU1_WAKE_UP_IRQ (GIC_SPI_START + 26) |
| 72 | #define SSBI2_2_SC_CPU0_SECURE_IRQ (GIC_SPI_START + 27) |
| 73 | #define SSBI2_2_SC_CPU0_NON_SECURE_IRQ (GIC_SPI_START + 28) |
| 74 | #define SSBI2_1_SC_CPU0_SECURE_IRQ (GIC_SPI_START + 29) |
| 75 | #define SSBI2_1_SC_CPU0_NON_SECURE_IRQ (GIC_SPI_START + 30) |
| 76 | #define MSMC_SC_SEC_CE_IRQ (GIC_SPI_START + 31) |
| 77 | #define MSMC_SC_PRI_CE_IRQ (GIC_SPI_START + 32) |
| 78 | #define SLIMBUS0_CORE_EE1_IRQ (GIC_SPI_START + 33) |
| 79 | #define SLIMBUS0_BAM_EE1_IRQ (GIC_SPI_START + 34) |
| 80 | #define KPSS_SPARE_0 (GIC_SPI_START + 35) |
| 81 | #define GSS_A5_WDOG_EXPIRED (GIC_SPI_START + 36) |
| 82 | #define GSS_TO_APPS_IRQ_0 (GIC_SPI_START + 37) |
| 83 | #define GSS_TO_APPS_IRQ_1 (GIC_SPI_START + 38) |
| 84 | #define GSS_TO_APPS_IRQ_2 (GIC_SPI_START + 39) |
| 85 | #define GSS_TO_APPS_IRQ_3 (GIC_SPI_START + 40) |
| 86 | #define GSS_TO_APPS_IRQ_4 (GIC_SPI_START + 41) |
| 87 | #define GSS_TO_APPS_IRQ_5 (GIC_SPI_START + 42) |
| 88 | #define GSS_TO_APPS_IRQ_6 (GIC_SPI_START + 43) |
| 89 | #define GSS_TO_APPS_IRQ_7 (GIC_SPI_START + 44) |
| 90 | #define GSS_TO_APPS_IRQ_8 (GIC_SPI_START + 45) |
| 91 | #define GSS_TO_APPS_IRQ_9 (GIC_SPI_START + 46) |
| 92 | #define VPE_IRQ (GIC_SPI_START + 47) |
| 93 | #define VFE_IRQ (GIC_SPI_START + 48) |
| 94 | #define VCODEC_IRQ (GIC_SPI_START + 49) |
| 95 | #define KPSS_SPARE_1 (GIC_SPI_START + 50) |
| 96 | #define SMMU_VPE_CB_SC_SECURE_IRQ (GIC_SPI_START + 51) |
| 97 | #define SMMU_VPE_CB_SC_NON_SECURE_IRQ (GIC_SPI_START + 52) |
| 98 | #define SMMU_VFE_CB_SC_SECURE_IRQ (GIC_SPI_START + 53) |
| 99 | #define SMMU_VFE_CB_SC_NON_SECURE_IRQ (GIC_SPI_START + 54) |
| 100 | #define SMMU_VCODEC_B_CB_SC_SECURE_IRQ (GIC_SPI_START + 55) |
| 101 | #define SMMU_VCODEC_B_CB_SC_NON_SECURE_IRQ (GIC_SPI_START + 56) |
| 102 | #define SMMU_VCODEC_A_CB_SC_SECURE_IRQ (GIC_SPI_START + 57) |
| 103 | #define SMMU_VCODEC_A_CB_SC_NON_SECURE_IRQ (GIC_SPI_START + 58) |
| 104 | #define SMMU_ROT_CB_SC_SECURE_IRQ (GIC_SPI_START + 59) |
| 105 | #define SMMU_ROT_CB_SC_NON_SECURE_IRQ (GIC_SPI_START + 60) |
| 106 | #define SMMU_MDP1_CB_SC_SECURE_IRQ (GIC_SPI_START + 61) |
| 107 | #define SMMU_MDP1_CB_SC_NON_SECURE_IRQ (GIC_SPI_START + 62) |
| 108 | #define SMMU_MDP0_CB_SC_SECURE_IRQ (GIC_SPI_START + 63) |
| 109 | #define SMMU_MDP0_CB_SC_NON_SECURE_IRQ (GIC_SPI_START + 64) |
| 110 | #define SMMU_JPEGD_CB_SC_SECURE_IRQ (GIC_SPI_START + 65) |
| 111 | #define SMMU_JPEGD_CB_SC_NON_SECURE_IRQ (GIC_SPI_START + 66) |
| 112 | #define SMMU_IJPEG_CB_SC_SECURE_IRQ (GIC_SPI_START + 67) |
| 113 | #define SMMU_IJPEG_CB_SC_NON_SECURE_IRQ (GIC_SPI_START + 68) |
| 114 | #define SMMU_GFX3D_CB_SC_SECURE_IRQ (GIC_SPI_START + 69) |
| 115 | #define SMMU_GFX3D_CB_SC_NON_SECURE_IRQ (GIC_SPI_START + 70) |
| 116 | #define VCAP_VP (GIC_SPI_START + 71) |
| 117 | #define VCAP_VC (GIC_SPI_START + 72) |
| 118 | #define ROT_IRQ (GIC_SPI_START + 73) |
| 119 | #define MMSS_FABRIC_IRQ (GIC_SPI_START + 74) |
| 120 | #define MDP_IRQ (GIC_SPI_START + 75) |
| 121 | #define JPEGD_IRQ (GIC_SPI_START + 76) |
| 122 | #define JPEG_IRQ (GIC_SPI_START + 77) |
| 123 | #define MMSS_IMEM_IRQ (GIC_SPI_START + 78) |
| 124 | #define HDMI_IRQ (GIC_SPI_START + 79) |
| 125 | #define GFX3D_IRQ (GIC_SPI_START + 80) |
| 126 | #define GFX3d_VBIF_IRQ (GIC_SPI_START + 81) |
| 127 | #define DSI1_IRQ (GIC_SPI_START + 82) |
| 128 | #define CSI_1_IRQ (GIC_SPI_START + 83) |
| 129 | #define CSI_0_IRQ (GIC_SPI_START + 84) |
| 130 | #define LPASS_SCSS_AUDIO_IF_OUT0_IRQ (GIC_SPI_START + 85) |
| 131 | #define LPASS_SCSS_MIDI_IRQ (GIC_SPI_START + 86) |
| 132 | #define LPASS_Q6SS_WDOG_EXPIRED (GIC_SPI_START + 87) |
| 133 | #define LPASS_SCSS_GP_LOW_IRQ (GIC_SPI_START + 88) |
| 134 | #define LPASS_SCSS_GP_MEDIUM_IRQ (GIC_SPI_START + 89) |
| 135 | #define LPASS_SCSS_GP_HIGH_IRQ (GIC_SPI_START + 90) |
| 136 | #define TOP_IMEM_IRQ (GIC_SPI_START + 91) |
| 137 | #define FABRIC_SYS_IRQ (GIC_SPI_START + 92) |
| 138 | #define FABRIC_APPS_IRQ (GIC_SPI_START + 93) |
| 139 | #define USB1_HS_BAM_IRQ (GIC_SPI_START + 94) |
| 140 | #define SDC4_BAM_IRQ (GIC_SPI_START + 95) |
| 141 | #define SDC3_BAM_IRQ (GIC_SPI_START + 96) |
| 142 | #define SDC2_BAM_IRQ (GIC_SPI_START + 97) |
| 143 | #define SDC1_BAM_IRQ (GIC_SPI_START + 98) |
| 144 | #define FABRIC_SPS_IRQ (GIC_SPI_START + 99) |
| 145 | #define USB1_HS_IRQ (GIC_SPI_START + 100) |
| 146 | #define SDC4_IRQ_0 (GIC_SPI_START + 101) |
| 147 | #define SDC3_IRQ_0 (GIC_SPI_START + 102) |
| 148 | #define SDC2_IRQ_0 (GIC_SPI_START + 103) |
| 149 | #define SDC1_IRQ_0 (GIC_SPI_START + 104) |
| 150 | #define SPS_BAM_DMA_IRQ (GIC_SPI_START + 105) |
| 151 | #define SPS_SEC_VIOL_IRQ (GIC_SPI_START + 106) |
| 152 | #define SPS_MTI_0 (GIC_SPI_START + 107) |
| 153 | #define SPS_MTI_1 (GIC_SPI_START + 108) |
| 154 | #define SPS_MTI_2 (GIC_SPI_START + 109) |
| 155 | #define SPS_MTI_3 (GIC_SPI_START + 110) |
| 156 | #define SPS_MTI_4 (GIC_SPI_START + 111) |
| 157 | #define SPS_MTI_5 (GIC_SPI_START + 112) |
| 158 | #define SPS_MTI_6 (GIC_SPI_START + 113) |
| 159 | #define SPS_MTI_7 (GIC_SPI_START + 114) |
| 160 | #define SPS_MTI_8 (GIC_SPI_START + 115) |
| 161 | #define SPS_MTI_9 (GIC_SPI_START + 116) |
| 162 | #define SPS_MTI_10 (GIC_SPI_START + 117) |
| 163 | #define SPS_MTI_11 (GIC_SPI_START + 118) |
| 164 | #define SPS_MTI_12 (GIC_SPI_START + 119) |
| 165 | #define SPS_MTI_13 (GIC_SPI_START + 120) |
| 166 | #define SPS_MTI_14 (GIC_SPI_START + 121) |
| 167 | #define SPS_MTI_15 (GIC_SPI_START + 122) |
| 168 | #define SPS_MTI_16 (GIC_SPI_START + 123) |
| 169 | #define SPS_MTI_17 (GIC_SPI_START + 124) |
| 170 | #define SPS_MTI_18 (GIC_SPI_START + 125) |
| 171 | #define SPS_MTI_19 (GIC_SPI_START + 126) |
| 172 | #define SPS_MTI_20 (GIC_SPI_START + 127) |
| 173 | #define SPS_MTI_21 (GIC_SPI_START + 128) |
| 174 | #define SPS_MTI_22 (GIC_SPI_START + 129) |
| 175 | #define SPS_MTI_23 (GIC_SPI_START + 130) |
| 176 | #define SPS_MTI_24 (GIC_SPI_START + 131) |
| 177 | #define SPS_MTI_25 (GIC_SPI_START + 132) |
| 178 | #define SPS_MTI_26 (GIC_SPI_START + 133) |
| 179 | #define SPS_MTI_27 (GIC_SPI_START + 134) |
| 180 | #define SPS_MTI_28 (GIC_SPI_START + 135) |
| 181 | #define SPS_MTI_29 (GIC_SPI_START + 136) |
| 182 | #define SPS_MTI_30 (GIC_SPI_START + 137) |
| 183 | #define SPS_MTI_31 (GIC_SPI_START + 138) |
| 184 | #define CSIPHY_0_4LN_IRQ (GIC_SPI_START + 139) |
| 185 | #define CSIPHY_1_2LN_IRQ (GIC_SPI_START + 140) |
| 186 | #define KPSS_SPARE_2 (GIC_SPI_START + 141) |
| 187 | #define USB1_IRQ (GIC_SPI_START + 142) |
| 188 | #define TSSC_SSBI_IRQ (GIC_SPI_START + 143) |
| 189 | #define TSSC_SAMPLE_IRQ (GIC_SPI_START + 144) |
| 190 | #define TSSC_PENUP_IRQ (GIC_SPI_START + 145) |
| 191 | #define KPSS_SPARE_3 (GIC_SPI_START + 146) |
| 192 | #define KPSS_SPARE_4 (GIC_SPI_START + 147) |
| 193 | #define KPSS_SPARE_5 (GIC_SPI_START + 148) |
| 194 | #define KPSS_SPARE_6 (GIC_SPI_START + 149) |
| 195 | #define GSBI3_UARTDM_IRQ (GIC_SPI_START + 150) |
| 196 | #define GSBI3_QUP_IRQ (GIC_SPI_START + 151) |
| 197 | #define GSBI4_UARTDM_IRQ (GIC_SPI_START + 152) |
| 198 | #define GSBI4_QUP_IRQ (GIC_SPI_START + 153) |
| 199 | #define GSBI5_UARTDM_IRQ (GIC_SPI_START + 154) |
| 200 | #define GSBI5_QUP_IRQ (GIC_SPI_START + 155) |
| 201 | #define GSBI6_UARTDM_IRQ (GIC_SPI_START + 156) |
| 202 | #define GSBI6_QUP_IRQ (GIC_SPI_START + 157) |
| 203 | #define GSBI7_UARTDM_IRQ (GIC_SPI_START + 158) |
| 204 | #define GSBI7_QUP_IRQ (GIC_SPI_START + 159) |
| 205 | #define KPSS_SPARE_7 (GIC_SPI_START + 160) |
| 206 | #define KPSS_SPARE_8 (GIC_SPI_START + 161) |
| 207 | #define TSIF_TSPP_IRQ (GIC_SPI_START + 162) |
| 208 | #define TSIF_BAM_IRQ (GIC_SPI_START + 163) |
| 209 | #define TSIF2_IRQ (GIC_SPI_START + 164) |
| 210 | #define TSIF1_IRQ (GIC_SPI_START + 165) |
| 211 | #define DSI2_IRQ (GIC_SPI_START + 166) |
| 212 | #define ISPIF_IRQ (GIC_SPI_START + 167) |
| 213 | #define MSMC_SC_SEC_TMR_IRQ (GIC_SPI_START + 168) |
| 214 | #define MSMC_SC_SEC_WDOG_BARK_IRQ (GIC_SPI_START + 169) |
| 215 | #define ADM_0_SCSS_0_IRQ (GIC_SPI_START + 170) |
| 216 | #define ADM_0_SCSS_1_IRQ (GIC_SPI_START + 171) |
| 217 | #define ADM_0_SCSS_2_IRQ (GIC_SPI_START + 172) |
| 218 | #define ADM_0_SCSS_3_IRQ (GIC_SPI_START + 173) |
| 219 | #define CC_SCSS_WDT1CPU1BITEEXPIRED (GIC_SPI_START + 174) |
| 220 | #define CC_SCSS_WDT1CPU0BITEEXPIRED (GIC_SPI_START + 175) |
| 221 | #define CC_SCSS_WDT0CPU1BITEEXPIRED (GIC_SPI_START + 176) |
| 222 | #define CC_SCSS_WDT0CPU0BITEEXPIRED (GIC_SPI_START + 177) |
| 223 | #define TSENS_UPPER_LOWER_INT (GIC_SPI_START + 178) |
| 224 | #define SSBI2_2_SC_CPU1_SECURE_INT (GIC_SPI_START + 179) |
| 225 | #define SSBI2_2_SC_CPU1_NON_SECURE_INT (GIC_SPI_START + 180) |
| 226 | #define SSBI2_1_SC_CPU1_SECURE_INT (GIC_SPI_START + 181) |
| 227 | #define SSBI2_1_SC_CPU1_NON_SECURE_INT (GIC_SPI_START + 182) |
| 228 | #define XPU_SUMMARY_IRQ (GIC_SPI_START + 183) |
| 229 | #define BUS_EXCEPTION_SUMMARY_IRQ (GIC_SPI_START + 184) |
| 230 | #define HSDDRX_EBI1CH0_IRQ (GIC_SPI_START + 185) |
| 231 | #define HSDDRX_EBI1CH1_IRQ (GIC_SPI_START + 186) |
| 232 | #define USB3_HS_BAM_IRQ (GIC_SPI_START + 187) |
| 233 | #define USB3_HS_IRQ (GIC_SPI_START + 188) |
| 234 | #define CC_SCSS_WDT1CPU3BITEEXPIRED (GIC_SPI_START + 189) |
| 235 | #define CC_SCSS_WDT1CPU2BITEEXPIRED (GIC_SPI_START + 190) |
| 236 | #define CC_SCSS_WDT0CPU3BITEEXPIRED (GIC_SPI_START + 191) |
| 237 | #define CC_SCSS_WDT0CPU2BITEEXPIRED (GIC_SPI_START + 192) |
| 238 | #define APQ8064_GSBI1_UARTDM_IRQ (GIC_SPI_START + 193) |
| 239 | #define APQ8064_GSBI1_QUP_IRQ (GIC_SPI_START + 194) |
| 240 | #define APQ8064_GSBI2_UARTDM_IRQ (GIC_SPI_START + 195) |
| 241 | #define APQ8064_GSBI2_QUP_IRQ (GIC_SPI_START + 196) |
| 242 | #define RIVA_APSS_LTECOEX_IRQ (GIC_SPI_START + 197) |
| 243 | #define RIVA_APSS_SPARE_IRQ (GIC_SPI_START + 198) |
| 244 | #define RIVA_APSS_WDOG_BITE_RESET_RDY_IRQ (GIC_SPI_START + 199) |
| 245 | #define RIVA_APSS_RESET_DONE_IRQ (GIC_SPI_START + 200) |
| 246 | #define RIVA_APSS_ASIC_IRQ (GIC_SPI_START + 201) |
| 247 | #define RIVA_APPS_WLAN_RX_DATA_AVAIL_IRQ (GIC_SPI_START + 202) |
| 248 | #define RIVA_APPS_WLAN_DATA_XFER_DONE_IRQ (GIC_SPI_START + 203) |
| 249 | #define RIVA_APPS_WLAN_SMSM_IRQ (GIC_SPI_START + 204) |
| 250 | #define RIVA_APPS_LOG_CTRL_IRQ (GIC_SPI_START + 205) |
| 251 | #define RIVA_APPS_FM_CTRL_IRQ (GIC_SPI_START + 206) |
| 252 | #define RIVA_APPS_HCI_IRQ (GIC_SPI_START + 207) |
| 253 | #define RIVA_APPS_WLAN_CTRL_IRQ (GIC_SPI_START + 208) |
| 254 | #define SATA_CONTROLLER_IRQ (GIC_SPI_START + 209) |
| 255 | #define SMMU_GFX3D1_CB_SC_SECURE_IRQ (GIC_SPI_START + 210) |
| 256 | #define SMMU_GFX3D1_CB_SC_NON_SECURE_IRQ (GIC_SPI_START + 211) |
| 257 | #define KPSS_SPARE_9 (GIC_SPI_START + 212) |
| 258 | #define PPSS_WDOG_TIMER_IRQ (GIC_SPI_START + 213) |
| 259 | #define USB4_HS_BAM_IRQ (GIC_SPI_START + 214) |
| 260 | #define USB4_HS_IRQ (GIC_SPI_START + 215) |
| 261 | #define QDSS_ETB_IRQ (GIC_SPI_START + 216) |
| 262 | #define QDSS_CTI2KPSS_CPU1_IRQ (GIC_SPI_START + 217) |
| 263 | #define QDSS_CTI2KPSS_CPU0_IRQ (GIC_SPI_START + 218) |
| 264 | #define TLMM_MSM_DIR_CONN_IRQ_16 (GIC_SPI_START + 219) |
| 265 | #define TLMM_MSM_DIR_CONN_IRQ_17 (GIC_SPI_START + 220) |
| 266 | #define TLMM_MSM_DIR_CONN_IRQ_18 (GIC_SPI_START + 221) |
| 267 | #define TLMM_MSM_DIR_CONN_IRQ_19 (GIC_SPI_START + 222) |
| 268 | #define TLMM_MSM_DIR_CONN_IRQ_20 (GIC_SPI_START + 223) |
| 269 | #define TLMM_MSM_DIR_CONN_IRQ_21 (GIC_SPI_START + 224) |
| 270 | #define PM8921_USR_IRQ_N (GIC_SPI_START + 225) |
| 271 | #define PM8821_USR_IRQ_N (GIC_SPI_START + 226) |
| 272 | |
| 273 | #define CSI_2_IRQ (GIC_SPI_START + 227) |
| 274 | #define APQ8064_CSIPHY_2LN_IRQ (GIC_SPI_START + 228) |
| 275 | #define USB2_HSIC_IRQ (GIC_SPI_START + 229) |
| 276 | #define CE2_BAM_XPU_IRQ (GIC_SPI_START + 230) |
| 277 | #define CE1_BAM_XPU_IRQ (GIC_SPI_START + 231) |
| 278 | #define RPM_SCSS_CPU2_WAKE_UP_IRQ (GIC_SPI_START + 232) |
| 279 | #define RPM_SCSS_CPU3_WAKE_UP_IRQ (GIC_SPI_START + 233) |
| 280 | #define CS3_BAM_XPU_IRQ (GIC_SPI_START + 234) |
| 281 | #define CE3_IRQ (GIC_SPI_START + 235) |
| 282 | #define SMMU_VCAP_CB_SC_SECURE_IRQ (GIC_SPI_START + 236) |
| Joel King | 41d594e | 2011-10-14 13:18:20 -0700 | [diff] [blame] | 283 | #define SMMU_VCAP_CB_SC_NON_SECURE_IRQ (GIC_SPI_START + 237) |
| Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 284 | #define PCIE20_INT_MSI (GIC_SPI_START + 238) |
| 285 | #define PCIE20_INTA (GIC_SPI_START + 239) |
| 286 | #define PCIE20_INTB (GIC_SPI_START + 240) |
| 287 | #define PCIE20_INTC (GIC_SPI_START + 241) |
| 288 | #define PCIE20_INTD (GIC_SPI_START + 242) |
| 289 | #define PCIE20_INT_PLS_HP (GIC_SPI_START + 243) |
| 290 | #define PCIE20_INT_PLS_PME (GIC_SPI_START + 244) |
| 291 | #define PCIE20_INT_LINK_UP (GIC_SPI_START + 245) |
| 292 | #define PCIE20_INT_LINK_DOWN (GIC_SPI_START + 246) |
| 293 | #define PCIE20_INT_HP_LEGACY (GIC_SPI_START + 247) |
| 294 | #define PCIE20_AER_LEGACY (GIC_SPI_START + 248) |
| 295 | #define PCIE20_INT_PME_LEGACY (GIC_SPI_START + 249) |
| 296 | #define PCIE20_INT_BRIDGE_FLUSH_N (GIC_SPI_START + 250) |
| 297 | |
| 298 | /* Backwards compatible IRQ macros. */ |
| 299 | #define INT_ADM_AARM ADM_0_SCSS_0_IRQ |
| 300 | |
| Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 301 | /* smd/smsm interrupts */ |
| Jeff Hugo | 0c0f5e9 | 2011-09-28 13:55:45 -0600 | [diff] [blame] | 302 | #define INT_A9_M2A_0 (GIC_SPI_START + 37) /*GSS_TO_APPS_IRQ_0*/ |
| 303 | #define INT_A9_M2A_5 (GIC_SPI_START + 38) /*GSS_TO_APPS_IRQ_1*/ |
| 304 | #define INT_ADSP_A11 LPASS_SCSS_GP_HIGH_IRQ |
| 305 | #define INT_ADSP_A11_SMSM LPASS_SCSS_GP_MEDIUM_IRQ |
| 306 | #define INT_DSPS_A11 SPS_MTI_31 |
| 307 | #define INT_DSPS_A11_SMSM SPS_MTI_30 |
| 308 | #define INT_WCNSS_A11 RIVA_APSS_SPARE_IRQ |
| 309 | #define INT_WCNSS_A11_SMSM RIVA_APPS_WLAN_SMSM_IRQ |
| Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 310 | |
| 311 | #endif |
| 312 | |