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Kukjin Kim83014572011-11-06 13:54:56 +09001/* linux/arch/arm/mach-exynos/cpu.c
Changhwan Youn2b12b5c2010-07-26 21:08:52 +09002 *
Kukjin Kim7d30e8b2011-02-14 16:33:10 +09003 * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
4 * http://www.samsung.com
Changhwan Youn2b12b5c2010-07-26 21:08:52 +09005 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9*/
10
11#include <linux/sched.h>
12#include <linux/sysdev.h>
13
14#include <asm/mach/map.h>
15#include <asm/mach/irq.h>
16
17#include <asm/proc-fns.h>
Kyungmin Park1cf0eb72010-10-21 15:22:36 +090018#include <asm/hardware/cache-l2x0.h>
Changhwan Younaab74d32011-07-16 10:49:51 +090019#include <asm/hardware/gic.h>
Changhwan Youn2b12b5c2010-07-26 21:08:52 +090020
21#include <plat/cpu.h>
22#include <plat/clock.h>
MyungJoo Ham0e9e5262011-07-20 21:08:18 +090023#include <plat/devs.h>
Kukjin Kim7d30e8b2011-02-14 16:33:10 +090024#include <plat/exynos4.h>
MyungJoo Ham0e9e5262011-07-20 21:08:18 +090025#include <plat/adc-core.h>
Hyuk Lee1036c3a2010-10-05 19:07:41 +090026#include <plat/sdhci.h>
Jonghun Hane61b1702011-07-21 15:46:26 +090027#include <plat/fb-core.h>
Sylwester Nawrocki604eefe2011-03-12 08:58:01 +090028#include <plat/fimc-core.h>
Sylwester Nawrocki5f272752011-07-06 16:04:09 +090029#include <plat/iic-core.h>
Kyungmin Parkd2edddf2011-08-19 20:25:05 +090030#include <plat/reset.h>
Tomasz Stanislawskifbf05562011-09-19 16:44:42 +090031#include <plat/tv-core.h>
Changhwan Youn2b12b5c2010-07-26 21:08:52 +090032
33#include <mach/regs-irq.h>
Kyungmin Parkd2edddf2011-08-19 20:25:05 +090034#include <mach/regs-pmu.h>
Changhwan Youn2b12b5c2010-07-26 21:08:52 +090035
Changhwan Youn90a454b2011-10-04 17:08:57 +090036unsigned int gic_bank_offset __read_mostly;
37
Changhwan Youn2b12b5c2010-07-26 21:08:52 +090038extern int combiner_init(unsigned int combiner_nr, void __iomem *base,
39 unsigned int irq_start);
40extern void combiner_cascade_irq(unsigned int combiner_nr, unsigned int irq);
41
42/* Initial IO mappings */
Kukjin Kim83014572011-11-06 13:54:56 +090043static struct map_desc exynos_iodesc[] __initdata = {
Changhwan Youn2b12b5c2010-07-26 21:08:52 +090044 {
Changhwan Youn2b740152011-03-11 10:39:35 +090045 .virtual = (unsigned long)S5P_VA_SYSTIMER,
Kukjin Kim83014572011-11-06 13:54:56 +090046 .pfn = __phys_to_pfn(EXYNOS_PA_SYSTIMER),
Changhwan Youn2b740152011-03-11 10:39:35 +090047 .length = SZ_4K,
Kukjin Kimc598c472010-08-18 21:45:49 +090048 .type = MT_DEVICE,
Kukjin Kim19a2c062010-08-31 16:30:51 +090049 }, {
Changhwan Yound6d8b482010-12-03 17:15:40 +090050 .virtual = (unsigned long)S5P_VA_PMU,
Kukjin Kim83014572011-11-06 13:54:56 +090051 .pfn = __phys_to_pfn(EXYNOS_PA_PMU),
Changhwan Yound6d8b482010-12-03 17:15:40 +090052 .length = SZ_64K,
53 .type = MT_DEVICE,
54 }, {
Kukjin Kim19a2c062010-08-31 16:30:51 +090055 .virtual = (unsigned long)S5P_VA_COMBINER_BASE,
Kukjin Kim83014572011-11-06 13:54:56 +090056 .pfn = __phys_to_pfn(EXYNOS_PA_COMBINER),
Kukjin Kim19a2c062010-08-31 16:30:51 +090057 .length = SZ_4K,
58 .type = MT_DEVICE,
59 }, {
Kukjin Kim83014572011-11-06 13:54:56 +090060 .virtual = (unsigned long)S5P_VA_GIC_CPU,
61 .pfn = __phys_to_pfn(EXYNOS_PA_GIC_CPU),
62 .length = SZ_64K,
63 .type = MT_DEVICE,
64 }, {
65 .virtual = (unsigned long)S5P_VA_GIC_DIST,
66 .pfn = __phys_to_pfn(EXYNOS_PA_GIC_DIST),
67 .length = SZ_64K,
68 .type = MT_DEVICE,
69 }, {
70 .virtual = (unsigned long)S3C_VA_UART,
71 .pfn = __phys_to_pfn(S3C_PA_UART),
72 .length = SZ_512K,
73 .type = MT_DEVICE,
74 },
75};
76
77static struct map_desc exynos4_iodesc[] __initdata = {
78 {
79 .virtual = (unsigned long)S5P_VA_CMU,
80 .pfn = __phys_to_pfn(EXYNOS4_PA_CMU),
81 .length = SZ_128K,
82 .type = MT_DEVICE,
83 }, {
Kukjin Kim19a2c062010-08-31 16:30:51 +090084 .virtual = (unsigned long)S5P_VA_COREPERI_BASE,
Kukjin Kim7d30e8b2011-02-14 16:33:10 +090085 .pfn = __phys_to_pfn(EXYNOS4_PA_COREPERI),
Kukjin Kim19a2c062010-08-31 16:30:51 +090086 .length = SZ_8K,
87 .type = MT_DEVICE,
88 }, {
89 .virtual = (unsigned long)S5P_VA_L2CC,
Kukjin Kim7d30e8b2011-02-14 16:33:10 +090090 .pfn = __phys_to_pfn(EXYNOS4_PA_L2CC),
Kukjin Kim19a2c062010-08-31 16:30:51 +090091 .length = SZ_4K,
92 .type = MT_DEVICE,
93 }, {
Jongpill Lee37ea63b2010-10-14 15:46:18 +090094 .virtual = (unsigned long)S5P_VA_GPIO1,
Kukjin Kim7d30e8b2011-02-14 16:33:10 +090095 .pfn = __phys_to_pfn(EXYNOS4_PA_GPIO1),
Kukjin Kim19a2c062010-08-31 16:30:51 +090096 .length = SZ_4K,
97 .type = MT_DEVICE,
98 }, {
Jongpill Lee37ea63b2010-10-14 15:46:18 +090099 .virtual = (unsigned long)S5P_VA_GPIO2,
Kukjin Kim7d30e8b2011-02-14 16:33:10 +0900100 .pfn = __phys_to_pfn(EXYNOS4_PA_GPIO2),
Jongpill Lee37ea63b2010-10-14 15:46:18 +0900101 .length = SZ_4K,
102 .type = MT_DEVICE,
103 }, {
104 .virtual = (unsigned long)S5P_VA_GPIO3,
Kukjin Kim7d30e8b2011-02-14 16:33:10 +0900105 .pfn = __phys_to_pfn(EXYNOS4_PA_GPIO3),
Jongpill Lee37ea63b2010-10-14 15:46:18 +0900106 .length = SZ_256,
107 .type = MT_DEVICE,
108 }, {
Sunyoung Kangdd0b7e22010-12-22 07:21:17 +0900109 .virtual = (unsigned long)S5P_VA_DMC0,
Kukjin Kim7d30e8b2011-02-14 16:33:10 +0900110 .pfn = __phys_to_pfn(EXYNOS4_PA_DMC0),
Sunyoung Kangdd0b7e22010-12-22 07:21:17 +0900111 .length = SZ_4K,
112 .type = MT_DEVICE,
113 }, {
Daein Moon09596ba2010-10-25 16:30:40 +0900114 .virtual = (unsigned long)S5P_VA_SROMC,
Kukjin Kim7d30e8b2011-02-14 16:33:10 +0900115 .pfn = __phys_to_pfn(EXYNOS4_PA_SROMC),
Daein Moon09596ba2010-10-25 16:30:40 +0900116 .length = SZ_4K,
117 .type = MT_DEVICE,
Joonyoung Shim8f1d1692011-04-08 13:22:10 +0900118 }, {
Kukjin Kim08115a12011-06-01 15:09:05 -0700119 .virtual = (unsigned long)S3C_VA_USB_HSPHY,
Joonyoung Shim8f1d1692011-04-08 13:22:10 +0900120 .pfn = __phys_to_pfn(EXYNOS4_PA_HSPHY),
121 .length = SZ_4K,
122 .type = MT_DEVICE,
Changhwan Youneb13f2b2011-07-16 10:48:47 +0900123 },
Changhwan Youn2b12b5c2010-07-26 21:08:52 +0900124};
125
Kukjin Kim56b20922011-08-20 13:41:21 +0900126static struct map_desc exynos4_iodesc0[] __initdata = {
127 {
128 .virtual = (unsigned long)S5P_VA_SYSRAM,
129 .pfn = __phys_to_pfn(EXYNOS4_PA_SYSRAM0),
130 .length = SZ_4K,
131 .type = MT_DEVICE,
132 },
133};
134
135static struct map_desc exynos4_iodesc1[] __initdata = {
136 {
137 .virtual = (unsigned long)S5P_VA_SYSRAM,
138 .pfn = __phys_to_pfn(EXYNOS4_PA_SYSRAM1),
139 .length = SZ_4K,
140 .type = MT_DEVICE,
141 },
142};
143
Kukjin Kim83014572011-11-06 13:54:56 +0900144static void exynos_idle(void)
Changhwan Youn2b12b5c2010-07-26 21:08:52 +0900145{
146 if (!need_resched())
147 cpu_do_idle();
148
149 local_irq_enable();
150}
151
Kyungmin Parkd2edddf2011-08-19 20:25:05 +0900152static void exynos4_sw_reset(void)
153{
154 __raw_writel(0x1, S5P_SWRESET);
155}
156
Kukjin Kim7d30e8b2011-02-14 16:33:10 +0900157/*
Kukjin Kim83014572011-11-06 13:54:56 +0900158 * exynos_map_io
Changhwan Youn2b12b5c2010-07-26 21:08:52 +0900159 *
160 * register the standard cpu IO areas
Kukjin Kim7d30e8b2011-02-14 16:33:10 +0900161 */
162void __init exynos4_map_io(void)
Changhwan Youn2b12b5c2010-07-26 21:08:52 +0900163{
Kukjin Kim83014572011-11-06 13:54:56 +0900164 iotable_init(exynos_iodesc, ARRAY_SIZE(exynos_iodesc));
Kukjin Kim7d30e8b2011-02-14 16:33:10 +0900165 iotable_init(exynos4_iodesc, ARRAY_SIZE(exynos4_iodesc));
Hyuk Lee1036c3a2010-10-05 19:07:41 +0900166
Kukjin Kim56b20922011-08-20 13:41:21 +0900167 if (soc_is_exynos4210() && samsung_rev() == EXYNOS4210_REV_0)
168 iotable_init(exynos4_iodesc0, ARRAY_SIZE(exynos4_iodesc0));
169 else
170 iotable_init(exynos4_iodesc1, ARRAY_SIZE(exynos4_iodesc1));
171
Hyuk Lee1036c3a2010-10-05 19:07:41 +0900172 /* initialize device information early */
Kukjin Kim7d30e8b2011-02-14 16:33:10 +0900173 exynos4_default_sdhci0();
174 exynos4_default_sdhci1();
175 exynos4_default_sdhci2();
176 exynos4_default_sdhci3();
Sylwester Nawrocki604eefe2011-03-12 08:58:01 +0900177
MyungJoo Ham0e9e5262011-07-20 21:08:18 +0900178 s3c_adc_setname("samsung-adc-v3");
179
Sylwester Nawrocki604eefe2011-03-12 08:58:01 +0900180 s3c_fimc_setname(0, "exynos4-fimc");
181 s3c_fimc_setname(1, "exynos4-fimc");
182 s3c_fimc_setname(2, "exynos4-fimc");
183 s3c_fimc_setname(3, "exynos4-fimc");
Sylwester Nawrocki5f272752011-07-06 16:04:09 +0900184
185 /* The I2C bus controllers are directly compatible with s3c2440 */
186 s3c_i2c0_setname("s3c2440-i2c");
187 s3c_i2c1_setname("s3c2440-i2c");
188 s3c_i2c2_setname("s3c2440-i2c");
Jonghun Hane61b1702011-07-21 15:46:26 +0900189
190 s5p_fb_setname(0, "exynos4-fb");
Tomasz Stanislawskifbf05562011-09-19 16:44:42 +0900191 s5p_hdmi_setname("exynos4-hdmi");
Changhwan Youn2b12b5c2010-07-26 21:08:52 +0900192}
193
Kukjin Kim7d30e8b2011-02-14 16:33:10 +0900194void __init exynos4_init_clocks(int xtal)
Changhwan Youn2b12b5c2010-07-26 21:08:52 +0900195{
196 printk(KERN_DEBUG "%s: initializing clocks\n", __func__);
197
198 s3c24xx_register_baseclocks(xtal);
199 s5p_register_clocks(xtal);
Kukjin Kim2bc02c02011-08-24 17:25:09 +0900200
201 if (soc_is_exynos4210())
202 exynos4210_register_clocks();
Changhwan Youne6a275a2011-10-04 17:08:56 +0900203 else if (soc_is_exynos4212() || soc_is_exynos4412())
Kukjin Kim2bc02c02011-08-24 17:25:09 +0900204 exynos4212_register_clocks();
205
Kukjin Kim7d30e8b2011-02-14 16:33:10 +0900206 exynos4_register_clocks();
207 exynos4_setup_clocks();
Changhwan Youn2b12b5c2010-07-26 21:08:52 +0900208}
209
Changhwan Youn637c2af2011-10-04 17:02:58 +0900210static void exynos4_gic_irq_fix_base(struct irq_data *d)
Changhwan Younaab74d32011-07-16 10:49:51 +0900211{
212 struct gic_chip_data *gic_data = irq_data_get_irq_chip_data(d);
213
214 gic_data->cpu_base = S5P_VA_GIC_CPU +
Changhwan Youn90a454b2011-10-04 17:08:57 +0900215 (gic_bank_offset * smp_processor_id());
Changhwan Youn637c2af2011-10-04 17:02:58 +0900216
217 gic_data->dist_base = S5P_VA_GIC_DIST +
Changhwan Youn90a454b2011-10-04 17:08:57 +0900218 (gic_bank_offset * smp_processor_id());
Changhwan Younaab74d32011-07-16 10:49:51 +0900219}
220
Kukjin Kim7d30e8b2011-02-14 16:33:10 +0900221void __init exynos4_init_irq(void)
Changhwan Youn2b12b5c2010-07-26 21:08:52 +0900222{
223 int irq;
224
Changhwan Youn90a454b2011-10-04 17:08:57 +0900225 gic_bank_offset = soc_is_exynos4412() ? 0x4000 : 0x8000;
226
Changhwan Youn637c2af2011-10-04 17:02:58 +0900227 gic_init(0, IRQ_PPI(0), S5P_VA_GIC_DIST, S5P_VA_GIC_CPU);
228 gic_arch_extn.irq_eoi = exynos4_gic_irq_fix_base;
229 gic_arch_extn.irq_unmask = exynos4_gic_irq_fix_base;
230 gic_arch_extn.irq_mask = exynos4_gic_irq_fix_base;
Changhwan Youn2b12b5c2010-07-26 21:08:52 +0900231
232 for (irq = 0; irq < MAX_COMBINER_NR; irq++) {
Changhwan Youn1f2d6c42010-11-29 17:04:46 +0900233
Changhwan Youn2b12b5c2010-07-26 21:08:52 +0900234 combiner_init(irq, (void __iomem *)S5P_VA_COMBINER(irq),
235 COMBINER_IRQ(irq, 0));
236 combiner_cascade_irq(irq, IRQ_SPI(irq));
237 }
238
239 /* The parameters of s5p_init_irq() are for VIC init.
Kukjin Kim7d30e8b2011-02-14 16:33:10 +0900240 * Theses parameters should be NULL and 0 because EXYNOS4
Changhwan Youn2b12b5c2010-07-26 21:08:52 +0900241 * uses GIC instead of VIC.
242 */
243 s5p_init_irq(NULL, 0);
244}
245
Kukjin Kim7d30e8b2011-02-14 16:33:10 +0900246struct sysdev_class exynos4_sysclass = {
247 .name = "exynos4-core",
Changhwan Youn2b12b5c2010-07-26 21:08:52 +0900248};
249
Kukjin Kim7d30e8b2011-02-14 16:33:10 +0900250static struct sys_device exynos4_sysdev = {
251 .cls = &exynos4_sysclass,
Changhwan Youn2b12b5c2010-07-26 21:08:52 +0900252};
253
Kukjin Kim7d30e8b2011-02-14 16:33:10 +0900254static int __init exynos4_core_init(void)
Changhwan Youn2b12b5c2010-07-26 21:08:52 +0900255{
Kukjin Kim7d30e8b2011-02-14 16:33:10 +0900256 return sysdev_class_register(&exynos4_sysclass);
Changhwan Youn2b12b5c2010-07-26 21:08:52 +0900257}
Kukjin Kim7d30e8b2011-02-14 16:33:10 +0900258core_initcall(exynos4_core_init);
Changhwan Youn2b12b5c2010-07-26 21:08:52 +0900259
Kyungmin Park1cf0eb72010-10-21 15:22:36 +0900260#ifdef CONFIG_CACHE_L2X0
Kukjin Kim7d30e8b2011-02-14 16:33:10 +0900261static int __init exynos4_l2x0_cache_init(void)
Kyungmin Park1cf0eb72010-10-21 15:22:36 +0900262{
263 /* TAG, Data Latency Control: 2cycle */
264 __raw_writel(0x110, S5P_VA_L2CC + L2X0_TAG_LATENCY_CTRL);
Kukjin Kim68465382011-08-24 17:25:09 +0900265
266 if (soc_is_exynos4210())
267 __raw_writel(0x110, S5P_VA_L2CC + L2X0_DATA_LATENCY_CTRL);
Changhwan Youne6a275a2011-10-04 17:08:56 +0900268 else if (soc_is_exynos4212() || soc_is_exynos4412())
Kukjin Kim68465382011-08-24 17:25:09 +0900269 __raw_writel(0x120, S5P_VA_L2CC + L2X0_DATA_LATENCY_CTRL);
Kyungmin Park1cf0eb72010-10-21 15:22:36 +0900270
271 /* L2X0 Prefetch Control */
272 __raw_writel(0x30000007, S5P_VA_L2CC + L2X0_PREFETCH_CTRL);
273
274 /* L2X0 Power Control */
275 __raw_writel(L2X0_DYNAMIC_CLK_GATING_EN | L2X0_STNDBY_MODE_EN,
276 S5P_VA_L2CC + L2X0_POWER_CTRL);
277
Changhwan Youna50eb1c2010-11-26 13:21:53 +0900278 l2x0_init(S5P_VA_L2CC, 0x7C470001, 0xC200ffff);
Kyungmin Park1cf0eb72010-10-21 15:22:36 +0900279
280 return 0;
281}
282
Kukjin Kim7d30e8b2011-02-14 16:33:10 +0900283early_initcall(exynos4_l2x0_cache_init);
Kyungmin Park1cf0eb72010-10-21 15:22:36 +0900284#endif
285
Kukjin Kim83014572011-11-06 13:54:56 +0900286int __init exynos_init(void)
Changhwan Youn2b12b5c2010-07-26 21:08:52 +0900287{
Kukjin Kim83014572011-11-06 13:54:56 +0900288 printk(KERN_INFO "EXYNOS: Initializing architecture\n");
Changhwan Youn2b12b5c2010-07-26 21:08:52 +0900289
290 /* set idle function */
Kukjin Kim83014572011-11-06 13:54:56 +0900291 pm_idle = exynos_idle;
Changhwan Youn2b12b5c2010-07-26 21:08:52 +0900292
Kyungmin Parkd2edddf2011-08-19 20:25:05 +0900293 /* set sw_reset function */
Kukjin Kim83014572011-11-06 13:54:56 +0900294 if (soc_is_exynos4210() || soc_is_exynos4212() || soc_is_exynos4412())
295 s5p_reset_hook = exynos4_sw_reset;
Kyungmin Parkd2edddf2011-08-19 20:25:05 +0900296
Kukjin Kim7d30e8b2011-02-14 16:33:10 +0900297 return sysdev_register(&exynos4_sysdev);
Changhwan Youn2b12b5c2010-07-26 21:08:52 +0900298}