blob: 82d4099bd8f42a2899db6e6af16dfc4743442edb [file] [log] [blame]
Sascha Hauer1f1846c2010-10-06 10:25:55 +02001/*
2 * drivers/dma/imx-dma.c
3 *
4 * This file contains a driver for the Freescale i.MX DMA engine
5 * found on i.MX1/21/27
6 *
7 * Copyright 2010 Sascha Hauer, Pengutronix <s.hauer@pengutronix.de>
Javier Martin9e15db72012-03-02 09:28:47 +01008 * Copyright 2012 Javier Martin, Vista Silicon <javier.martin@vista-silicon.com>
Sascha Hauer1f1846c2010-10-06 10:25:55 +02009 *
10 * The code contained herein is licensed under the GNU General Public
11 * License. You may obtain a copy of the GNU General Public License
12 * Version 2 or later at the following locations:
13 *
14 * http://www.opensource.org/licenses/gpl-license.html
15 * http://www.gnu.org/copyleft/gpl.html
16 */
17#include <linux/init.h>
Axel Linf8de8f42011-08-30 15:08:24 +080018#include <linux/module.h>
Sascha Hauer1f1846c2010-10-06 10:25:55 +020019#include <linux/types.h>
20#include <linux/mm.h>
21#include <linux/interrupt.h>
22#include <linux/spinlock.h>
23#include <linux/device.h>
24#include <linux/dma-mapping.h>
25#include <linux/slab.h>
26#include <linux/platform_device.h>
Javier Martin6bd08122012-03-22 14:54:01 +010027#include <linux/clk.h>
Sascha Hauer1f1846c2010-10-06 10:25:55 +020028#include <linux/dmaengine.h>
Vinod Koul5170c052012-03-09 14:55:25 +053029#include <linux/module.h>
Sascha Hauer1f1846c2010-10-06 10:25:55 +020030
31#include <asm/irq.h>
Javier Martin6bd08122012-03-22 14:54:01 +010032#include <mach/dma.h>
Sascha Hauer1f1846c2010-10-06 10:25:55 +020033#include <mach/hardware.h>
34
Russell King - ARM Linuxd2ebfb32012-03-06 22:34:26 +000035#include "dmaengine.h"
Javier Martin9e15db72012-03-02 09:28:47 +010036#define IMXDMA_MAX_CHAN_DESCRIPTORS 16
Javier Martin6bd08122012-03-22 14:54:01 +010037#define IMX_DMA_CHANNELS 16
38
Javier Martin6bd08122012-03-22 14:54:01 +010039#define IMX_DMA_LENGTH_LOOP ((unsigned int)-1)
40#define IMX_DMA_MEMSIZE_32 (0 << 4)
41#define IMX_DMA_MEMSIZE_8 (1 << 4)
42#define IMX_DMA_MEMSIZE_16 (2 << 4)
43#define IMX_DMA_TYPE_LINEAR (0 << 10)
44#define IMX_DMA_TYPE_2D (1 << 10)
45#define IMX_DMA_TYPE_FIFO (2 << 10)
46
47#define IMX_DMA_ERR_BURST (1 << 0)
48#define IMX_DMA_ERR_REQUEST (1 << 1)
49#define IMX_DMA_ERR_TRANSFER (1 << 2)
50#define IMX_DMA_ERR_BUFFER (1 << 3)
51#define IMX_DMA_ERR_TIMEOUT (1 << 4)
52
53#define DMA_DCR 0x00 /* Control Register */
54#define DMA_DISR 0x04 /* Interrupt status Register */
55#define DMA_DIMR 0x08 /* Interrupt mask Register */
56#define DMA_DBTOSR 0x0c /* Burst timeout status Register */
57#define DMA_DRTOSR 0x10 /* Request timeout Register */
58#define DMA_DSESR 0x14 /* Transfer Error Status Register */
59#define DMA_DBOSR 0x18 /* Buffer overflow status Register */
60#define DMA_DBTOCR 0x1c /* Burst timeout control Register */
61#define DMA_WSRA 0x40 /* W-Size Register A */
62#define DMA_XSRA 0x44 /* X-Size Register A */
63#define DMA_YSRA 0x48 /* Y-Size Register A */
64#define DMA_WSRB 0x4c /* W-Size Register B */
65#define DMA_XSRB 0x50 /* X-Size Register B */
66#define DMA_YSRB 0x54 /* Y-Size Register B */
67#define DMA_SAR(x) (0x80 + ((x) << 6)) /* Source Address Registers */
68#define DMA_DAR(x) (0x84 + ((x) << 6)) /* Destination Address Registers */
69#define DMA_CNTR(x) (0x88 + ((x) << 6)) /* Count Registers */
70#define DMA_CCR(x) (0x8c + ((x) << 6)) /* Control Registers */
71#define DMA_RSSR(x) (0x90 + ((x) << 6)) /* Request source select Registers */
72#define DMA_BLR(x) (0x94 + ((x) << 6)) /* Burst length Registers */
73#define DMA_RTOR(x) (0x98 + ((x) << 6)) /* Request timeout Registers */
74#define DMA_BUCR(x) (0x98 + ((x) << 6)) /* Bus Utilization Registers */
75#define DMA_CCNR(x) (0x9C + ((x) << 6)) /* Channel counter Registers */
76
77#define DCR_DRST (1<<1)
78#define DCR_DEN (1<<0)
79#define DBTOCR_EN (1<<15)
80#define DBTOCR_CNT(x) ((x) & 0x7fff)
81#define CNTR_CNT(x) ((x) & 0xffffff)
82#define CCR_ACRPT (1<<14)
83#define CCR_DMOD_LINEAR (0x0 << 12)
84#define CCR_DMOD_2D (0x1 << 12)
85#define CCR_DMOD_FIFO (0x2 << 12)
86#define CCR_DMOD_EOBFIFO (0x3 << 12)
87#define CCR_SMOD_LINEAR (0x0 << 10)
88#define CCR_SMOD_2D (0x1 << 10)
89#define CCR_SMOD_FIFO (0x2 << 10)
90#define CCR_SMOD_EOBFIFO (0x3 << 10)
91#define CCR_MDIR_DEC (1<<9)
92#define CCR_MSEL_B (1<<8)
93#define CCR_DSIZ_32 (0x0 << 6)
94#define CCR_DSIZ_8 (0x1 << 6)
95#define CCR_DSIZ_16 (0x2 << 6)
96#define CCR_SSIZ_32 (0x0 << 4)
97#define CCR_SSIZ_8 (0x1 << 4)
98#define CCR_SSIZ_16 (0x2 << 4)
99#define CCR_REN (1<<3)
100#define CCR_RPT (1<<2)
101#define CCR_FRC (1<<1)
102#define CCR_CEN (1<<0)
103#define RTOR_EN (1<<15)
104#define RTOR_CLK (1<<14)
105#define RTOR_PSC (1<<13)
Javier Martin9e15db72012-03-02 09:28:47 +0100106
107enum imxdma_prep_type {
108 IMXDMA_DESC_MEMCPY,
109 IMXDMA_DESC_INTERLEAVED,
110 IMXDMA_DESC_SLAVE_SG,
111 IMXDMA_DESC_CYCLIC,
112};
113
Javier Martin6bd08122012-03-22 14:54:01 +0100114/*
115 * struct imxdma_channel_internal - i.MX specific DMA extension
116 * @name: name specified by DMA client
117 * @irq_handler: client callback for end of transfer
118 * @err_handler: client callback for error condition
119 * @data: clients context data for callbacks
120 * @dma_mode: direction of the transfer %DMA_MODE_READ or %DMA_MODE_WRITE
121 * @sg: pointer to the actual read/written chunk for scatter-gather emulation
122 * @resbytes: total residual number of bytes to transfer
123 * (it can be lower or same as sum of SG mapped chunk sizes)
124 * @sgcount: number of chunks to be read/written
125 *
126 * Structure is used for IMX DMA processing. It would be probably good
127 * @struct dma_struct in the future for external interfacing and use
128 * @struct imxdma_channel_internal only as extension to it.
129 */
130
131struct imxdma_channel_internal {
Javier Martin6bd08122012-03-22 14:54:01 +0100132 unsigned int resbytes;
133
134 int in_use;
135
Javier Martin6bd08122012-03-22 14:54:01 +0100136 struct timer_list watchdog;
137
138 int hw_chaining;
139};
140
Javier Martin9e15db72012-03-02 09:28:47 +0100141struct imxdma_desc {
142 struct list_head node;
143 struct dma_async_tx_descriptor desc;
144 enum dma_status status;
145 dma_addr_t src;
146 dma_addr_t dest;
147 size_t len;
Javier Martin2efc3442012-03-22 14:54:03 +0100148 enum dma_transfer_direction direction;
Javier Martin9e15db72012-03-02 09:28:47 +0100149 enum imxdma_prep_type type;
150 /* For memcpy and interleaved */
151 unsigned int config_port;
152 unsigned int config_mem;
153 /* For interleaved transfers */
154 unsigned int x;
155 unsigned int y;
156 unsigned int w;
157 /* For slave sg and cyclic */
158 struct scatterlist *sg;
159 unsigned int sgcount;
160};
161
Sascha Hauer1f1846c2010-10-06 10:25:55 +0200162struct imxdma_channel {
Javier Martin6bd08122012-03-22 14:54:01 +0100163 struct imxdma_channel_internal internal;
Sascha Hauer1f1846c2010-10-06 10:25:55 +0200164 struct imxdma_engine *imxdma;
165 unsigned int channel;
Sascha Hauer1f1846c2010-10-06 10:25:55 +0200166
Javier Martin9e15db72012-03-02 09:28:47 +0100167 struct tasklet_struct dma_tasklet;
168 struct list_head ld_free;
169 struct list_head ld_queue;
170 struct list_head ld_active;
171 int descs_allocated;
Sascha Hauer1f1846c2010-10-06 10:25:55 +0200172 enum dma_slave_buswidth word_size;
173 dma_addr_t per_address;
174 u32 watermark_level;
175 struct dma_chan chan;
176 spinlock_t lock;
177 struct dma_async_tx_descriptor desc;
Sascha Hauer1f1846c2010-10-06 10:25:55 +0200178 enum dma_status status;
179 int dma_request;
180 struct scatterlist *sg_list;
Javier Martin359291a2012-03-22 14:54:06 +0100181 u32 ccr_from_device;
182 u32 ccr_to_device;
Sascha Hauer1f1846c2010-10-06 10:25:55 +0200183};
184
Sascha Hauer1f1846c2010-10-06 10:25:55 +0200185struct imxdma_engine {
186 struct device *dev;
Sascha Hauer1e070a62011-01-12 13:14:37 +0100187 struct device_dma_parameters dma_parms;
Sascha Hauer1f1846c2010-10-06 10:25:55 +0200188 struct dma_device dma_device;
Javier Martin6bd08122012-03-22 14:54:01 +0100189 struct imxdma_channel channel[IMX_DMA_CHANNELS];
Sascha Hauer1f1846c2010-10-06 10:25:55 +0200190};
191
192static struct imxdma_channel *to_imxdma_chan(struct dma_chan *chan)
193{
194 return container_of(chan, struct imxdma_channel, chan);
195}
196
Javier Martin9e15db72012-03-02 09:28:47 +0100197static inline bool imxdma_chan_is_doing_cyclic(struct imxdma_channel *imxdmac)
Sascha Hauer1f1846c2010-10-06 10:25:55 +0200198{
Javier Martin9e15db72012-03-02 09:28:47 +0100199 struct imxdma_desc *desc;
200
201 if (!list_empty(&imxdmac->ld_active)) {
202 desc = list_first_entry(&imxdmac->ld_active, struct imxdma_desc,
203 node);
204 if (desc->type == IMXDMA_DESC_CYCLIC)
205 return true;
206 }
207 return false;
Sascha Hauer1f1846c2010-10-06 10:25:55 +0200208}
209
Javier Martin6bd08122012-03-22 14:54:01 +0100210/* TODO: put this inside any struct */
211static void __iomem *imx_dmav1_baseaddr;
212static struct clk *dma_clk;
Sascha Hauer1f1846c2010-10-06 10:25:55 +0200213
Javier Martin6bd08122012-03-22 14:54:01 +0100214static void imx_dmav1_writel(unsigned val, unsigned offset)
215{
216 __raw_writel(val, imx_dmav1_baseaddr + offset);
217}
218
219static unsigned imx_dmav1_readl(unsigned offset)
220{
221 return __raw_readl(imx_dmav1_baseaddr + offset);
222}
223
224static int imxdma_hw_chain(struct imxdma_channel_internal *imxdma)
225{
226 if (cpu_is_mx27())
227 return imxdma->hw_chaining;
228 else
229 return 0;
230}
231
232/*
233 * imxdma_sg_next - prepare next chunk for scatter-gather DMA emulation
234 */
Javier Martin2efc3442012-03-22 14:54:03 +0100235static inline int imxdma_sg_next(struct imxdma_desc *d, struct scatterlist *sg)
Javier Martin6bd08122012-03-22 14:54:01 +0100236{
Javier Martin2efc3442012-03-22 14:54:03 +0100237 struct imxdma_channel *imxdmac = to_imxdma_chan(d->desc.chan);
Javier Martin6bd08122012-03-22 14:54:01 +0100238 struct imxdma_channel_internal *imxdma = &imxdmac->internal;
239 unsigned long now;
240
241 now = min(imxdma->resbytes, sg->length);
242 if (imxdma->resbytes != IMX_DMA_LENGTH_LOOP)
243 imxdma->resbytes -= now;
244
Javier Martin2efc3442012-03-22 14:54:03 +0100245 if (d->direction == DMA_DEV_TO_MEM)
Javier Martin6bd08122012-03-22 14:54:01 +0100246 imx_dmav1_writel(sg->dma_address, DMA_DAR(imxdmac->channel));
247 else
248 imx_dmav1_writel(sg->dma_address, DMA_SAR(imxdmac->channel));
249
250 imx_dmav1_writel(now, DMA_CNTR(imxdmac->channel));
251
252 pr_debug("imxdma%d: next sg chunk dst 0x%08x, src 0x%08x, "
253 "size 0x%08x\n", imxdmac->channel,
254 imx_dmav1_readl(DMA_DAR(imxdmac->channel)),
255 imx_dmav1_readl(DMA_SAR(imxdmac->channel)),
256 imx_dmav1_readl(DMA_CNTR(imxdmac->channel)));
257
258 return now;
259}
260
Javier Martin2efc3442012-03-22 14:54:03 +0100261static void imxdma_enable_hw(struct imxdma_desc *d)
Javier Martin6bd08122012-03-22 14:54:01 +0100262{
Javier Martin2efc3442012-03-22 14:54:03 +0100263 struct imxdma_channel *imxdmac = to_imxdma_chan(d->desc.chan);
Javier Martin6bd08122012-03-22 14:54:01 +0100264 int channel = imxdmac->channel;
265 unsigned long flags;
266
267 pr_debug("imxdma%d: imx_dma_enable\n", channel);
268
269 if (imxdmac->internal.in_use)
270 return;
271
272 local_irq_save(flags);
273
274 imx_dmav1_writel(1 << channel, DMA_DISR);
275 imx_dmav1_writel(imx_dmav1_readl(DMA_DIMR) & ~(1 << channel), DMA_DIMR);
276 imx_dmav1_writel(imx_dmav1_readl(DMA_CCR(channel)) | CCR_CEN |
277 CCR_ACRPT, DMA_CCR(channel));
278
279 if ((cpu_is_mx21() || cpu_is_mx27()) &&
Javier Martin833bc032012-03-22 14:54:07 +0100280 d->sg && imxdma_hw_chain(&imxdmac->internal)) {
281 d->sg = sg_next(d->sg);
282 if (d->sg) {
Javier Martin6bd08122012-03-22 14:54:01 +0100283 u32 tmp;
Javier Martin833bc032012-03-22 14:54:07 +0100284 imxdma_sg_next(d, d->sg);
Javier Martin6bd08122012-03-22 14:54:01 +0100285 tmp = imx_dmav1_readl(DMA_CCR(channel));
286 imx_dmav1_writel(tmp | CCR_RPT | CCR_ACRPT,
287 DMA_CCR(channel));
288 }
289 }
290 imxdmac->internal.in_use = 1;
291
292 local_irq_restore(flags);
293}
294
295static void imxdma_disable_hw(struct imxdma_channel *imxdmac)
296{
297 int channel = imxdmac->channel;
298 unsigned long flags;
299
300 pr_debug("imxdma%d: imx_dma_disable\n", channel);
301
302 if (imxdma_hw_chain(&imxdmac->internal))
303 del_timer(&imxdmac->internal.watchdog);
304
305 local_irq_save(flags);
306 imx_dmav1_writel(imx_dmav1_readl(DMA_DIMR) | (1 << channel), DMA_DIMR);
307 imx_dmav1_writel(imx_dmav1_readl(DMA_CCR(channel)) & ~CCR_CEN,
308 DMA_CCR(channel));
309 imx_dmav1_writel(1 << channel, DMA_DISR);
310 imxdmac->internal.in_use = 0;
311 local_irq_restore(flags);
312}
313
Javier Martin6bd08122012-03-22 14:54:01 +0100314static void imxdma_watchdog(unsigned long data)
315{
316 struct imxdma_channel *imxdmac = (struct imxdma_channel *)data;
317 int channel = imxdmac->channel;
318
319 imx_dmav1_writel(0, DMA_CCR(channel));
320 imxdmac->internal.in_use = 0;
Javier Martin6bd08122012-03-22 14:54:01 +0100321
322 /* Tasklet watchdog error handler */
323 tasklet_schedule(&imxdmac->dma_tasklet);
324 pr_debug("imxdma%d: watchdog timeout!\n", imxdmac->channel);
325}
326
327static irqreturn_t imxdma_err_handler(int irq, void *dev_id)
328{
329 struct imxdma_engine *imxdma = dev_id;
330 struct imxdma_channel_internal *internal;
331 unsigned int err_mask;
332 int i, disr;
333 int errcode;
334
335 disr = imx_dmav1_readl(DMA_DISR);
336
337 err_mask = imx_dmav1_readl(DMA_DBTOSR) |
338 imx_dmav1_readl(DMA_DRTOSR) |
339 imx_dmav1_readl(DMA_DSESR) |
340 imx_dmav1_readl(DMA_DBOSR);
341
342 if (!err_mask)
343 return IRQ_HANDLED;
344
345 imx_dmav1_writel(disr & err_mask, DMA_DISR);
346
347 for (i = 0; i < IMX_DMA_CHANNELS; i++) {
348 if (!(err_mask & (1 << i)))
349 continue;
350 internal = &imxdma->channel[i].internal;
351 errcode = 0;
352
353 if (imx_dmav1_readl(DMA_DBTOSR) & (1 << i)) {
354 imx_dmav1_writel(1 << i, DMA_DBTOSR);
355 errcode |= IMX_DMA_ERR_BURST;
356 }
357 if (imx_dmav1_readl(DMA_DRTOSR) & (1 << i)) {
358 imx_dmav1_writel(1 << i, DMA_DRTOSR);
359 errcode |= IMX_DMA_ERR_REQUEST;
360 }
361 if (imx_dmav1_readl(DMA_DSESR) & (1 << i)) {
362 imx_dmav1_writel(1 << i, DMA_DSESR);
363 errcode |= IMX_DMA_ERR_TRANSFER;
364 }
365 if (imx_dmav1_readl(DMA_DBOSR) & (1 << i)) {
366 imx_dmav1_writel(1 << i, DMA_DBOSR);
367 errcode |= IMX_DMA_ERR_BUFFER;
368 }
369 /* Tasklet error handler */
370 tasklet_schedule(&imxdma->channel[i].dma_tasklet);
371
372 printk(KERN_WARNING
373 "DMA timeout on channel %d -%s%s%s%s\n", i,
374 errcode & IMX_DMA_ERR_BURST ? " burst" : "",
375 errcode & IMX_DMA_ERR_REQUEST ? " request" : "",
376 errcode & IMX_DMA_ERR_TRANSFER ? " transfer" : "",
377 errcode & IMX_DMA_ERR_BUFFER ? " buffer" : "");
378 }
379 return IRQ_HANDLED;
380}
381
382static void dma_irq_handle_channel(struct imxdma_channel *imxdmac)
383{
384 struct imxdma_channel_internal *imxdma = &imxdmac->internal;
385 int chno = imxdmac->channel;
Javier Martin2efc3442012-03-22 14:54:03 +0100386 struct imxdma_desc *desc;
Javier Martin6bd08122012-03-22 14:54:01 +0100387
Javier Martin833bc032012-03-22 14:54:07 +0100388 spin_lock(&imxdmac->lock);
389 if (list_empty(&imxdmac->ld_active)) {
390 spin_unlock(&imxdmac->lock);
391 goto out;
392 }
393
394 desc = list_first_entry(&imxdmac->ld_active,
395 struct imxdma_desc,
396 node);
397 spin_unlock(&imxdmac->lock);
398
399 if (desc->sg) {
Javier Martin6bd08122012-03-22 14:54:01 +0100400 u32 tmp;
Javier Martin833bc032012-03-22 14:54:07 +0100401 desc->sg = sg_next(desc->sg);
Javier Martin6bd08122012-03-22 14:54:01 +0100402
Javier Martin833bc032012-03-22 14:54:07 +0100403 if (desc->sg) {
404 imxdma_sg_next(desc, desc->sg);
Javier Martin6bd08122012-03-22 14:54:01 +0100405
406 tmp = imx_dmav1_readl(DMA_CCR(chno));
407
408 if (imxdma_hw_chain(imxdma)) {
409 /* FIXME: The timeout should probably be
410 * configurable
411 */
412 mod_timer(&imxdma->watchdog,
413 jiffies + msecs_to_jiffies(500));
414
415 tmp |= CCR_CEN | CCR_RPT | CCR_ACRPT;
416 imx_dmav1_writel(tmp, DMA_CCR(chno));
417 } else {
418 imx_dmav1_writel(tmp & ~CCR_CEN, DMA_CCR(chno));
419 tmp |= CCR_CEN;
420 }
421
422 imx_dmav1_writel(tmp, DMA_CCR(chno));
423
424 if (imxdma_chan_is_doing_cyclic(imxdmac))
425 /* Tasklet progression */
426 tasklet_schedule(&imxdmac->dma_tasklet);
427
428 return;
429 }
430
431 if (imxdma_hw_chain(imxdma)) {
432 del_timer(&imxdma->watchdog);
433 return;
434 }
435 }
436
Javier Martin2efc3442012-03-22 14:54:03 +0100437out:
Javier Martin6bd08122012-03-22 14:54:01 +0100438 imx_dmav1_writel(0, DMA_CCR(chno));
439 imxdma->in_use = 0;
440 /* Tasklet irq */
Javier Martin9e15db72012-03-02 09:28:47 +0100441 tasklet_schedule(&imxdmac->dma_tasklet);
Sascha Hauer1f1846c2010-10-06 10:25:55 +0200442}
443
Javier Martin6bd08122012-03-22 14:54:01 +0100444static irqreturn_t dma_irq_handler(int irq, void *dev_id)
Sascha Hauer1f1846c2010-10-06 10:25:55 +0200445{
Javier Martin6bd08122012-03-22 14:54:01 +0100446 struct imxdma_engine *imxdma = dev_id;
447 struct imxdma_channel_internal *internal;
448 int i, disr;
Sascha Hauer1f1846c2010-10-06 10:25:55 +0200449
Javier Martin6bd08122012-03-22 14:54:01 +0100450 if (cpu_is_mx21() || cpu_is_mx27())
451 imxdma_err_handler(irq, dev_id);
Sascha Hauer1f1846c2010-10-06 10:25:55 +0200452
Javier Martin6bd08122012-03-22 14:54:01 +0100453 disr = imx_dmav1_readl(DMA_DISR);
Sascha Hauer1f1846c2010-10-06 10:25:55 +0200454
Javier Martin6bd08122012-03-22 14:54:01 +0100455 pr_debug("imxdma: dma_irq_handler called, disr=0x%08x\n",
456 disr);
457
458 imx_dmav1_writel(disr, DMA_DISR);
459 for (i = 0; i < IMX_DMA_CHANNELS; i++) {
460 if (disr & (1 << i)) {
461 internal = &imxdma->channel[i].internal;
462 dma_irq_handle_channel(&imxdma->channel[i]);
463 }
464 }
465
466 return IRQ_HANDLED;
Javier Martin9e15db72012-03-02 09:28:47 +0100467}
468
469static int imxdma_xfer_desc(struct imxdma_desc *d)
470{
471 struct imxdma_channel *imxdmac = to_imxdma_chan(d->desc.chan);
Javier Martin3b4b6df2012-03-22 14:54:04 +0100472 struct imxdma_engine *imxdma = imxdmac->imxdma;
Javier Martin9e15db72012-03-02 09:28:47 +0100473
474 /* Configure and enable */
475 switch (d->type) {
476 case IMXDMA_DESC_MEMCPY:
Javier Martin3b4b6df2012-03-22 14:54:04 +0100477 imx_dmav1_writel(d->src, DMA_SAR(imxdmac->channel));
478 imx_dmav1_writel(d->dest, DMA_DAR(imxdmac->channel));
479 imx_dmav1_writel(d->config_mem | (d->config_port << 2),
480 DMA_CCR(imxdmac->channel));
481
482 imx_dmav1_writel(d->len, DMA_CNTR(imxdmac->channel));
483
484 dev_dbg(imxdma->dev, "%s channel: %d dest=0x%08x src=0x%08x "
485 "dma_length=%d\n", __func__, imxdmac->channel,
486 d->dest, d->src, d->len);
487
488 break;
Javier Martin6bd08122012-03-22 14:54:01 +0100489 /* Cyclic transfer is the same as slave_sg with special sg configuration. */
Javier Martin9e15db72012-03-02 09:28:47 +0100490 case IMXDMA_DESC_CYCLIC:
Javier Martin9e15db72012-03-02 09:28:47 +0100491 case IMXDMA_DESC_SLAVE_SG:
Javier Martin359291a2012-03-22 14:54:06 +0100492 imxdmac->internal.resbytes = d->len;
493
494 if (d->direction == DMA_DEV_TO_MEM) {
495 imx_dmav1_writel(imxdmac->per_address,
496 DMA_SAR(imxdmac->channel));
497 imx_dmav1_writel(imxdmac->ccr_from_device,
498 DMA_CCR(imxdmac->channel));
499
500 dev_dbg(imxdma->dev, "%s channel: %d sg=%p sgcount=%d "
501 "total length=%d dev_addr=0x%08x (dev2mem)\n",
502 __func__, imxdmac->channel, d->sg, d->sgcount,
503 d->len, imxdmac->per_address);
504 } else if (d->direction == DMA_MEM_TO_DEV) {
505 imx_dmav1_writel(imxdmac->per_address,
506 DMA_DAR(imxdmac->channel));
507 imx_dmav1_writel(imxdmac->ccr_to_device,
508 DMA_CCR(imxdmac->channel));
509
510 dev_dbg(imxdma->dev, "%s channel: %d sg=%p sgcount=%d "
511 "total length=%d dev_addr=0x%08x (mem2dev)\n",
512 __func__, imxdmac->channel, d->sg, d->sgcount,
513 d->len, imxdmac->per_address);
514 } else {
515 dev_err(imxdma->dev, "%s channel: %d bad dma mode\n",
516 __func__, imxdmac->channel);
517 return -EINVAL;
518 }
519
520 imxdma_sg_next(d, d->sg);
521
Javier Martin9e15db72012-03-02 09:28:47 +0100522 break;
523 default:
524 return -EINVAL;
525 }
Javier Martin2efc3442012-03-22 14:54:03 +0100526 imxdma_enable_hw(d);
Javier Martin9e15db72012-03-02 09:28:47 +0100527 return 0;
528}
529
530static void imxdma_tasklet(unsigned long data)
531{
532 struct imxdma_channel *imxdmac = (void *)data;
533 struct imxdma_engine *imxdma = imxdmac->imxdma;
534 struct imxdma_desc *desc;
535
536 spin_lock(&imxdmac->lock);
537
538 if (list_empty(&imxdmac->ld_active)) {
539 /* Someone might have called terminate all */
540 goto out;
541 }
542 desc = list_first_entry(&imxdmac->ld_active, struct imxdma_desc, node);
543
544 if (desc->desc.callback)
545 desc->desc.callback(desc->desc.callback_param);
546
Vinod Koul1f3d6dc2012-03-13 12:39:49 +0530547 dma_cookie_complete(&desc->desc);
Javier Martin9e15db72012-03-02 09:28:47 +0100548
549 /* If we are dealing with a cyclic descriptor keep it on ld_active */
550 if (imxdma_chan_is_doing_cyclic(imxdmac))
551 goto out;
552
553 list_move_tail(imxdmac->ld_active.next, &imxdmac->ld_free);
554
555 if (!list_empty(&imxdmac->ld_queue)) {
556 desc = list_first_entry(&imxdmac->ld_queue, struct imxdma_desc,
557 node);
558 list_move_tail(imxdmac->ld_queue.next, &imxdmac->ld_active);
559 if (imxdma_xfer_desc(desc) < 0)
560 dev_warn(imxdma->dev, "%s: channel: %d couldn't xfer desc\n",
561 __func__, imxdmac->channel);
562 }
563out:
564 spin_unlock(&imxdmac->lock);
Sascha Hauer1f1846c2010-10-06 10:25:55 +0200565}
566
567static int imxdma_control(struct dma_chan *chan, enum dma_ctrl_cmd cmd,
568 unsigned long arg)
569{
570 struct imxdma_channel *imxdmac = to_imxdma_chan(chan);
571 struct dma_slave_config *dmaengine_cfg = (void *)arg;
Javier Martin9e15db72012-03-02 09:28:47 +0100572 unsigned long flags;
Sascha Hauer1f1846c2010-10-06 10:25:55 +0200573 unsigned int mode = 0;
574
575 switch (cmd) {
576 case DMA_TERMINATE_ALL:
Javier Martin6bd08122012-03-22 14:54:01 +0100577 imxdma_disable_hw(imxdmac);
Javier Martin9e15db72012-03-02 09:28:47 +0100578
579 spin_lock_irqsave(&imxdmac->lock, flags);
580 list_splice_tail_init(&imxdmac->ld_active, &imxdmac->ld_free);
581 list_splice_tail_init(&imxdmac->ld_queue, &imxdmac->ld_free);
582 spin_unlock_irqrestore(&imxdmac->lock, flags);
Sascha Hauer1f1846c2010-10-06 10:25:55 +0200583 return 0;
584 case DMA_SLAVE_CONFIG:
Vinod Kouldb8196d2011-10-13 22:34:23 +0530585 if (dmaengine_cfg->direction == DMA_DEV_TO_MEM) {
Sascha Hauer1f1846c2010-10-06 10:25:55 +0200586 imxdmac->per_address = dmaengine_cfg->src_addr;
587 imxdmac->watermark_level = dmaengine_cfg->src_maxburst;
588 imxdmac->word_size = dmaengine_cfg->src_addr_width;
589 } else {
590 imxdmac->per_address = dmaengine_cfg->dst_addr;
591 imxdmac->watermark_level = dmaengine_cfg->dst_maxburst;
592 imxdmac->word_size = dmaengine_cfg->dst_addr_width;
593 }
594
595 switch (imxdmac->word_size) {
596 case DMA_SLAVE_BUSWIDTH_1_BYTE:
597 mode = IMX_DMA_MEMSIZE_8;
598 break;
599 case DMA_SLAVE_BUSWIDTH_2_BYTES:
600 mode = IMX_DMA_MEMSIZE_16;
601 break;
602 default:
603 case DMA_SLAVE_BUSWIDTH_4_BYTES:
604 mode = IMX_DMA_MEMSIZE_32;
605 break;
606 }
Sascha Hauer1f1846c2010-10-06 10:25:55 +0200607
Javier Martinbdc0c752012-03-22 14:54:05 +0100608 imxdmac->internal.hw_chaining = 1;
609 if (!imxdma_hw_chain(&imxdmac->internal))
610 return -EINVAL;
Javier Martin359291a2012-03-22 14:54:06 +0100611 imxdmac->ccr_from_device = (mode | IMX_DMA_TYPE_FIFO) |
Javier Martinbdc0c752012-03-22 14:54:05 +0100612 ((IMX_DMA_MEMSIZE_32 | IMX_DMA_TYPE_LINEAR) << 2) |
613 CCR_REN;
Javier Martin359291a2012-03-22 14:54:06 +0100614 imxdmac->ccr_to_device =
Javier Martinbdc0c752012-03-22 14:54:05 +0100615 (IMX_DMA_MEMSIZE_32 | IMX_DMA_TYPE_LINEAR) |
616 ((mode | IMX_DMA_TYPE_FIFO) << 2) | CCR_REN;
617 imx_dmav1_writel(imxdmac->dma_request,
618 DMA_RSSR(imxdmac->channel));
619
Javier Martin6bd08122012-03-22 14:54:01 +0100620 /* Set burst length */
621 imx_dmav1_writel(imxdmac->watermark_level * imxdmac->word_size,
622 DMA_BLR(imxdmac->channel));
Sascha Hauer1f1846c2010-10-06 10:25:55 +0200623
624 return 0;
625 default:
626 return -ENOSYS;
627 }
628
629 return -EINVAL;
630}
631
632static enum dma_status imxdma_tx_status(struct dma_chan *chan,
633 dma_cookie_t cookie,
634 struct dma_tx_state *txstate)
635{
Russell King - ARM Linux96a2af42012-03-06 22:35:27 +0000636 return dma_cookie_status(chan, cookie, txstate);
Sascha Hauer1f1846c2010-10-06 10:25:55 +0200637}
638
639static dma_cookie_t imxdma_tx_submit(struct dma_async_tx_descriptor *tx)
640{
641 struct imxdma_channel *imxdmac = to_imxdma_chan(tx->chan);
642 dma_cookie_t cookie;
Javier Martin9e15db72012-03-02 09:28:47 +0100643 unsigned long flags;
Sascha Hauer1f1846c2010-10-06 10:25:55 +0200644
Javier Martin9e15db72012-03-02 09:28:47 +0100645 spin_lock_irqsave(&imxdmac->lock, flags);
Russell King - ARM Linux884485e2012-03-06 22:34:46 +0000646 cookie = dma_cookie_assign(tx);
Javier Martin9e15db72012-03-02 09:28:47 +0100647 spin_unlock_irqrestore(&imxdmac->lock, flags);
Sascha Hauer1f1846c2010-10-06 10:25:55 +0200648
649 return cookie;
650}
651
652static int imxdma_alloc_chan_resources(struct dma_chan *chan)
653{
654 struct imxdma_channel *imxdmac = to_imxdma_chan(chan);
655 struct imx_dma_data *data = chan->private;
656
Javier Martin6c05f092012-02-28 17:08:17 +0100657 if (data != NULL)
658 imxdmac->dma_request = data->dma_request;
Sascha Hauer1f1846c2010-10-06 10:25:55 +0200659
Javier Martin9e15db72012-03-02 09:28:47 +0100660 while (imxdmac->descs_allocated < IMXDMA_MAX_CHAN_DESCRIPTORS) {
661 struct imxdma_desc *desc;
Sascha Hauer1f1846c2010-10-06 10:25:55 +0200662
Javier Martin9e15db72012-03-02 09:28:47 +0100663 desc = kzalloc(sizeof(*desc), GFP_KERNEL);
664 if (!desc)
665 break;
666 __memzero(&desc->desc, sizeof(struct dma_async_tx_descriptor));
667 dma_async_tx_descriptor_init(&desc->desc, chan);
668 desc->desc.tx_submit = imxdma_tx_submit;
669 /* txd.flags will be overwritten in prep funcs */
670 desc->desc.flags = DMA_CTRL_ACK;
671 desc->status = DMA_SUCCESS;
Sascha Hauer1f1846c2010-10-06 10:25:55 +0200672
Javier Martin9e15db72012-03-02 09:28:47 +0100673 list_add_tail(&desc->node, &imxdmac->ld_free);
674 imxdmac->descs_allocated++;
675 }
676
677 if (!imxdmac->descs_allocated)
678 return -ENOMEM;
679
680 return imxdmac->descs_allocated;
Sascha Hauer1f1846c2010-10-06 10:25:55 +0200681}
682
683static void imxdma_free_chan_resources(struct dma_chan *chan)
684{
685 struct imxdma_channel *imxdmac = to_imxdma_chan(chan);
Javier Martin9e15db72012-03-02 09:28:47 +0100686 struct imxdma_desc *desc, *_desc;
687 unsigned long flags;
688
689 spin_lock_irqsave(&imxdmac->lock, flags);
Sascha Hauer1f1846c2010-10-06 10:25:55 +0200690
Javier Martin6bd08122012-03-22 14:54:01 +0100691 imxdma_disable_hw(imxdmac);
Javier Martin9e15db72012-03-02 09:28:47 +0100692 list_splice_tail_init(&imxdmac->ld_active, &imxdmac->ld_free);
693 list_splice_tail_init(&imxdmac->ld_queue, &imxdmac->ld_free);
694
695 spin_unlock_irqrestore(&imxdmac->lock, flags);
696
697 list_for_each_entry_safe(desc, _desc, &imxdmac->ld_free, node) {
698 kfree(desc);
699 imxdmac->descs_allocated--;
700 }
701 INIT_LIST_HEAD(&imxdmac->ld_free);
Sascha Hauer1f1846c2010-10-06 10:25:55 +0200702
703 if (imxdmac->sg_list) {
704 kfree(imxdmac->sg_list);
705 imxdmac->sg_list = NULL;
706 }
707}
708
709static struct dma_async_tx_descriptor *imxdma_prep_slave_sg(
710 struct dma_chan *chan, struct scatterlist *sgl,
Vinod Kouldb8196d2011-10-13 22:34:23 +0530711 unsigned int sg_len, enum dma_transfer_direction direction,
Alexandre Bounine185ecb52012-03-08 15:35:13 -0500712 unsigned long flags, void *context)
Sascha Hauer1f1846c2010-10-06 10:25:55 +0200713{
714 struct imxdma_channel *imxdmac = to_imxdma_chan(chan);
715 struct scatterlist *sg;
Javier Martin9e15db72012-03-02 09:28:47 +0100716 int i, dma_length = 0;
717 struct imxdma_desc *desc;
Sascha Hauer1f1846c2010-10-06 10:25:55 +0200718
Javier Martin9e15db72012-03-02 09:28:47 +0100719 if (list_empty(&imxdmac->ld_free) ||
720 imxdma_chan_is_doing_cyclic(imxdmac))
Sascha Hauer1f1846c2010-10-06 10:25:55 +0200721 return NULL;
722
Javier Martin9e15db72012-03-02 09:28:47 +0100723 desc = list_first_entry(&imxdmac->ld_free, struct imxdma_desc, node);
Sascha Hauer1f1846c2010-10-06 10:25:55 +0200724
725 for_each_sg(sgl, sg, sg_len, i) {
726 dma_length += sg->length;
727 }
728
Sascha Hauerd07102a2011-01-12 14:13:23 +0100729 switch (imxdmac->word_size) {
730 case DMA_SLAVE_BUSWIDTH_4_BYTES:
731 if (sgl->length & 3 || sgl->dma_address & 3)
732 return NULL;
733 break;
734 case DMA_SLAVE_BUSWIDTH_2_BYTES:
735 if (sgl->length & 1 || sgl->dma_address & 1)
736 return NULL;
737 break;
738 case DMA_SLAVE_BUSWIDTH_1_BYTE:
739 break;
740 default:
741 return NULL;
742 }
743
Javier Martin9e15db72012-03-02 09:28:47 +0100744 desc->type = IMXDMA_DESC_SLAVE_SG;
745 desc->sg = sgl;
746 desc->sgcount = sg_len;
747 desc->len = dma_length;
Javier Martin2efc3442012-03-22 14:54:03 +0100748 desc->direction = direction;
Javier Martin9e15db72012-03-02 09:28:47 +0100749 if (direction == DMA_DEV_TO_MEM) {
Javier Martin9e15db72012-03-02 09:28:47 +0100750 desc->src = imxdmac->per_address;
751 } else {
Javier Martin9e15db72012-03-02 09:28:47 +0100752 desc->dest = imxdmac->per_address;
753 }
754 desc->desc.callback = NULL;
755 desc->desc.callback_param = NULL;
Sascha Hauer1f1846c2010-10-06 10:25:55 +0200756
Javier Martin9e15db72012-03-02 09:28:47 +0100757 return &desc->desc;
Sascha Hauer1f1846c2010-10-06 10:25:55 +0200758}
759
760static struct dma_async_tx_descriptor *imxdma_prep_dma_cyclic(
761 struct dma_chan *chan, dma_addr_t dma_addr, size_t buf_len,
Alexandre Bounine185ecb52012-03-08 15:35:13 -0500762 size_t period_len, enum dma_transfer_direction direction,
763 void *context)
Sascha Hauer1f1846c2010-10-06 10:25:55 +0200764{
765 struct imxdma_channel *imxdmac = to_imxdma_chan(chan);
766 struct imxdma_engine *imxdma = imxdmac->imxdma;
Javier Martin9e15db72012-03-02 09:28:47 +0100767 struct imxdma_desc *desc;
768 int i;
Sascha Hauer1f1846c2010-10-06 10:25:55 +0200769 unsigned int periods = buf_len / period_len;
Sascha Hauer1f1846c2010-10-06 10:25:55 +0200770
771 dev_dbg(imxdma->dev, "%s channel: %d buf_len=%d period_len=%d\n",
772 __func__, imxdmac->channel, buf_len, period_len);
773
Javier Martin9e15db72012-03-02 09:28:47 +0100774 if (list_empty(&imxdmac->ld_free) ||
775 imxdma_chan_is_doing_cyclic(imxdmac))
Sascha Hauer1f1846c2010-10-06 10:25:55 +0200776 return NULL;
Sascha Hauer1f1846c2010-10-06 10:25:55 +0200777
Javier Martin9e15db72012-03-02 09:28:47 +0100778 desc = list_first_entry(&imxdmac->ld_free, struct imxdma_desc, node);
Sascha Hauer1f1846c2010-10-06 10:25:55 +0200779
780 if (imxdmac->sg_list)
781 kfree(imxdmac->sg_list);
782
783 imxdmac->sg_list = kcalloc(periods + 1,
784 sizeof(struct scatterlist), GFP_KERNEL);
785 if (!imxdmac->sg_list)
786 return NULL;
787
788 sg_init_table(imxdmac->sg_list, periods);
789
790 for (i = 0; i < periods; i++) {
791 imxdmac->sg_list[i].page_link = 0;
792 imxdmac->sg_list[i].offset = 0;
793 imxdmac->sg_list[i].dma_address = dma_addr;
794 imxdmac->sg_list[i].length = period_len;
795 dma_addr += period_len;
796 }
797
798 /* close the loop */
799 imxdmac->sg_list[periods].offset = 0;
800 imxdmac->sg_list[periods].length = 0;
801 imxdmac->sg_list[periods].page_link =
802 ((unsigned long)imxdmac->sg_list | 0x01) & ~0x02;
803
Javier Martin9e15db72012-03-02 09:28:47 +0100804 desc->type = IMXDMA_DESC_CYCLIC;
805 desc->sg = imxdmac->sg_list;
806 desc->sgcount = periods;
807 desc->len = IMX_DMA_LENGTH_LOOP;
Javier Martin2efc3442012-03-22 14:54:03 +0100808 desc->direction = direction;
Javier Martin9e15db72012-03-02 09:28:47 +0100809 if (direction == DMA_DEV_TO_MEM) {
Javier Martin9e15db72012-03-02 09:28:47 +0100810 desc->src = imxdmac->per_address;
811 } else {
Javier Martin9e15db72012-03-02 09:28:47 +0100812 desc->dest = imxdmac->per_address;
813 }
814 desc->desc.callback = NULL;
815 desc->desc.callback_param = NULL;
Sascha Hauer1f1846c2010-10-06 10:25:55 +0200816
Javier Martin9e15db72012-03-02 09:28:47 +0100817 return &desc->desc;
Sascha Hauer1f1846c2010-10-06 10:25:55 +0200818}
819
Javier Martin6c05f092012-02-28 17:08:17 +0100820static struct dma_async_tx_descriptor *imxdma_prep_dma_memcpy(
821 struct dma_chan *chan, dma_addr_t dest,
822 dma_addr_t src, size_t len, unsigned long flags)
823{
824 struct imxdma_channel *imxdmac = to_imxdma_chan(chan);
825 struct imxdma_engine *imxdma = imxdmac->imxdma;
Javier Martin9e15db72012-03-02 09:28:47 +0100826 struct imxdma_desc *desc;
Javier Martin6c05f092012-02-28 17:08:17 +0100827
828 dev_dbg(imxdma->dev, "%s channel: %d src=0x%x dst=0x%x len=%d\n",
829 __func__, imxdmac->channel, src, dest, len);
830
Javier Martin9e15db72012-03-02 09:28:47 +0100831 if (list_empty(&imxdmac->ld_free) ||
832 imxdma_chan_is_doing_cyclic(imxdmac))
Javier Martin6c05f092012-02-28 17:08:17 +0100833 return NULL;
834
Javier Martin9e15db72012-03-02 09:28:47 +0100835 desc = list_first_entry(&imxdmac->ld_free, struct imxdma_desc, node);
Javier Martin6c05f092012-02-28 17:08:17 +0100836
Javier Martin9e15db72012-03-02 09:28:47 +0100837 desc->type = IMXDMA_DESC_MEMCPY;
838 desc->src = src;
839 desc->dest = dest;
840 desc->len = len;
Javier Martin2efc3442012-03-22 14:54:03 +0100841 desc->direction = DMA_MEM_TO_MEM;
Javier Martin9e15db72012-03-02 09:28:47 +0100842 desc->config_port = IMX_DMA_MEMSIZE_32 | IMX_DMA_TYPE_LINEAR;
843 desc->config_mem = IMX_DMA_MEMSIZE_32 | IMX_DMA_TYPE_LINEAR;
844 desc->desc.callback = NULL;
845 desc->desc.callback_param = NULL;
846
847 return &desc->desc;
Javier Martin6c05f092012-02-28 17:08:17 +0100848}
849
Sascha Hauer1f1846c2010-10-06 10:25:55 +0200850static void imxdma_issue_pending(struct dma_chan *chan)
851{
Sascha Hauer5b316872012-01-09 10:32:49 +0100852 struct imxdma_channel *imxdmac = to_imxdma_chan(chan);
Javier Martin9e15db72012-03-02 09:28:47 +0100853 struct imxdma_engine *imxdma = imxdmac->imxdma;
854 struct imxdma_desc *desc;
855 unsigned long flags;
Sascha Hauer5b316872012-01-09 10:32:49 +0100856
Javier Martin9e15db72012-03-02 09:28:47 +0100857 spin_lock_irqsave(&imxdmac->lock, flags);
858 if (list_empty(&imxdmac->ld_active) &&
859 !list_empty(&imxdmac->ld_queue)) {
860 desc = list_first_entry(&imxdmac->ld_queue,
861 struct imxdma_desc, node);
862
863 if (imxdma_xfer_desc(desc) < 0) {
864 dev_warn(imxdma->dev,
865 "%s: channel: %d couldn't issue DMA xfer\n",
866 __func__, imxdmac->channel);
867 } else {
868 list_move_tail(imxdmac->ld_queue.next,
869 &imxdmac->ld_active);
870 }
871 }
872 spin_unlock_irqrestore(&imxdmac->lock, flags);
Sascha Hauer1f1846c2010-10-06 10:25:55 +0200873}
874
875static int __init imxdma_probe(struct platform_device *pdev)
Javier Martin6bd08122012-03-22 14:54:01 +0100876 {
Sascha Hauer1f1846c2010-10-06 10:25:55 +0200877 struct imxdma_engine *imxdma;
878 int ret, i;
879
Javier Martin6bd08122012-03-22 14:54:01 +0100880 if (cpu_is_mx1())
881 imx_dmav1_baseaddr = MX1_IO_ADDRESS(MX1_DMA_BASE_ADDR);
882 else if (cpu_is_mx21())
883 imx_dmav1_baseaddr = MX21_IO_ADDRESS(MX21_DMA_BASE_ADDR);
884 else if (cpu_is_mx27())
885 imx_dmav1_baseaddr = MX27_IO_ADDRESS(MX27_DMA_BASE_ADDR);
886 else
887 return 0;
888
889 dma_clk = clk_get(NULL, "dma");
890 if (IS_ERR(dma_clk))
891 return PTR_ERR(dma_clk);
892 clk_enable(dma_clk);
893
894 /* reset DMA module */
895 imx_dmav1_writel(DCR_DRST, DMA_DCR);
896
897 if (cpu_is_mx1()) {
898 ret = request_irq(MX1_DMA_INT, dma_irq_handler, 0, "DMA", imxdma);
899 if (ret) {
900 pr_crit("Can't register IRQ for DMA\n");
901 return ret;
902 }
903
904 ret = request_irq(MX1_DMA_ERR, imxdma_err_handler, 0, "DMA", imxdma);
905 if (ret) {
906 pr_crit("Can't register ERRIRQ for DMA\n");
907 free_irq(MX1_DMA_INT, NULL);
908 return ret;
909 }
910 }
911
912 /* enable DMA module */
913 imx_dmav1_writel(DCR_DEN, DMA_DCR);
914
915 /* clear all interrupts */
916 imx_dmav1_writel((1 << IMX_DMA_CHANNELS) - 1, DMA_DISR);
917
918 /* disable interrupts */
919 imx_dmav1_writel((1 << IMX_DMA_CHANNELS) - 1, DMA_DIMR);
920
Sascha Hauer1f1846c2010-10-06 10:25:55 +0200921 imxdma = kzalloc(sizeof(*imxdma), GFP_KERNEL);
922 if (!imxdma)
923 return -ENOMEM;
924
925 INIT_LIST_HEAD(&imxdma->dma_device.channels);
926
Sascha Hauerf8a356f2011-01-31 11:35:59 +0100927 dma_cap_set(DMA_SLAVE, imxdma->dma_device.cap_mask);
928 dma_cap_set(DMA_CYCLIC, imxdma->dma_device.cap_mask);
Javier Martin6c05f092012-02-28 17:08:17 +0100929 dma_cap_set(DMA_MEMCPY, imxdma->dma_device.cap_mask);
Sascha Hauerf8a356f2011-01-31 11:35:59 +0100930
Sascha Hauer1f1846c2010-10-06 10:25:55 +0200931 /* Initialize channel parameters */
Javier Martin6bd08122012-03-22 14:54:01 +0100932 for (i = 0; i < IMX_DMA_CHANNELS; i++) {
Sascha Hauer1f1846c2010-10-06 10:25:55 +0200933 struct imxdma_channel *imxdmac = &imxdma->channel[i];
Javier Martin6bd08122012-03-22 14:54:01 +0100934 memset(&imxdmac->internal, 0, sizeof(imxdmac->internal));
935 if (cpu_is_mx21() || cpu_is_mx27()) {
936 ret = request_irq(MX2x_INT_DMACH0 + i,
937 dma_irq_handler, 0, "DMA", imxdma);
938 if (ret) {
939 pr_crit("Can't register IRQ %d for DMA channel %d\n",
940 MX2x_INT_DMACH0 + i, i);
941 goto err_init;
942 }
943 init_timer(&imxdmac->internal.watchdog);
944 imxdmac->internal.watchdog.function = &imxdma_watchdog;
945 imxdmac->internal.watchdog.data = (unsigned long)imxdmac;
Sascha Hauer8267f162010-10-20 08:37:19 +0200946 }
Sascha Hauer1f1846c2010-10-06 10:25:55 +0200947
Sascha Hauer1f1846c2010-10-06 10:25:55 +0200948 imxdmac->imxdma = imxdma;
949 spin_lock_init(&imxdmac->lock);
950
Javier Martin9e15db72012-03-02 09:28:47 +0100951 INIT_LIST_HEAD(&imxdmac->ld_queue);
952 INIT_LIST_HEAD(&imxdmac->ld_free);
953 INIT_LIST_HEAD(&imxdmac->ld_active);
954
955 tasklet_init(&imxdmac->dma_tasklet, imxdma_tasklet,
956 (unsigned long)imxdmac);
Sascha Hauer1f1846c2010-10-06 10:25:55 +0200957 imxdmac->chan.device = &imxdma->dma_device;
Russell King - ARM Linux8ac69542012-03-06 22:36:27 +0000958 dma_cookie_init(&imxdmac->chan);
Sascha Hauer1f1846c2010-10-06 10:25:55 +0200959 imxdmac->channel = i;
960
961 /* Add the channel to the DMAC list */
Javier Martin9e15db72012-03-02 09:28:47 +0100962 list_add_tail(&imxdmac->chan.device_node,
963 &imxdma->dma_device.channels);
Sascha Hauer1f1846c2010-10-06 10:25:55 +0200964 }
965
966 imxdma->dev = &pdev->dev;
967 imxdma->dma_device.dev = &pdev->dev;
968
969 imxdma->dma_device.device_alloc_chan_resources = imxdma_alloc_chan_resources;
970 imxdma->dma_device.device_free_chan_resources = imxdma_free_chan_resources;
971 imxdma->dma_device.device_tx_status = imxdma_tx_status;
972 imxdma->dma_device.device_prep_slave_sg = imxdma_prep_slave_sg;
973 imxdma->dma_device.device_prep_dma_cyclic = imxdma_prep_dma_cyclic;
Javier Martin6c05f092012-02-28 17:08:17 +0100974 imxdma->dma_device.device_prep_dma_memcpy = imxdma_prep_dma_memcpy;
Sascha Hauer1f1846c2010-10-06 10:25:55 +0200975 imxdma->dma_device.device_control = imxdma_control;
976 imxdma->dma_device.device_issue_pending = imxdma_issue_pending;
977
978 platform_set_drvdata(pdev, imxdma);
979
Javier Martin6c05f092012-02-28 17:08:17 +0100980 imxdma->dma_device.copy_align = 2; /* 2^2 = 4 bytes alignment */
Sascha Hauer1e070a62011-01-12 13:14:37 +0100981 imxdma->dma_device.dev->dma_parms = &imxdma->dma_parms;
982 dma_set_max_seg_size(imxdma->dma_device.dev, 0xffffff);
983
Sascha Hauer1f1846c2010-10-06 10:25:55 +0200984 ret = dma_async_device_register(&imxdma->dma_device);
985 if (ret) {
986 dev_err(&pdev->dev, "unable to register\n");
987 goto err_init;
988 }
989
990 return 0;
991
992err_init:
Javier Martin6bd08122012-03-22 14:54:01 +0100993
994 if (cpu_is_mx21() || cpu_is_mx27()) {
995 while (--i >= 0)
996 free_irq(MX2x_INT_DMACH0 + i, NULL);
997 } else if cpu_is_mx1() {
998 free_irq(MX1_DMA_INT, NULL);
999 free_irq(MX1_DMA_ERR, NULL);
Sascha Hauer1f1846c2010-10-06 10:25:55 +02001000 }
1001
1002 kfree(imxdma);
1003 return ret;
1004}
1005
1006static int __exit imxdma_remove(struct platform_device *pdev)
1007{
1008 struct imxdma_engine *imxdma = platform_get_drvdata(pdev);
1009 int i;
1010
1011 dma_async_device_unregister(&imxdma->dma_device);
1012
Javier Martin6bd08122012-03-22 14:54:01 +01001013 if (cpu_is_mx21() || cpu_is_mx27()) {
1014 for (i = 0; i < IMX_DMA_CHANNELS; i++)
1015 free_irq(MX2x_INT_DMACH0 + i, NULL);
1016 } else if cpu_is_mx1() {
1017 free_irq(MX1_DMA_INT, NULL);
1018 free_irq(MX1_DMA_ERR, NULL);
Sascha Hauer1f1846c2010-10-06 10:25:55 +02001019 }
1020
1021 kfree(imxdma);
1022
1023 return 0;
1024}
1025
1026static struct platform_driver imxdma_driver = {
1027 .driver = {
1028 .name = "imx-dma",
1029 },
1030 .remove = __exit_p(imxdma_remove),
1031};
1032
1033static int __init imxdma_module_init(void)
1034{
1035 return platform_driver_probe(&imxdma_driver, imxdma_probe);
1036}
1037subsys_initcall(imxdma_module_init);
1038
1039MODULE_AUTHOR("Sascha Hauer, Pengutronix <s.hauer@pengutronix.de>");
1040MODULE_DESCRIPTION("i.MX dma driver");
1041MODULE_LICENSE("GPL");