blob: 06c8db079b9125b7d4f400f4cbe6b15de4147ff8 [file] [log] [blame]
Jeff Garzik669a5db2006-08-29 18:12:40 -04001/*
2 * Libata driver for the highpoint 372N and 302N UDMA66 ATA controllers.
3 *
4 * This driver is heavily based upon:
5 *
6 * linux/drivers/ide/pci/hpt366.c Version 0.36 April 25, 2003
7 *
8 * Copyright (C) 1999-2003 Andre Hedrick <andre@linux-ide.org>
9 * Portions Copyright (C) 2001 Sun Microsystems, Inc.
10 * Portions Copyright (C) 2003 Red Hat Inc
11 *
12 *
13 * TODO
14 * 371N
15 * Work out best PLL policy
16 */
17
18#include <linux/kernel.h>
19#include <linux/module.h>
20#include <linux/pci.h>
21#include <linux/init.h>
22#include <linux/blkdev.h>
23#include <linux/delay.h>
24#include <scsi/scsi_host.h>
25#include <linux/libata.h>
26
27#define DRV_NAME "pata_hpt3x2n"
28#define DRV_VERSION "0.3"
29
30enum {
31 HPT_PCI_FAST = (1 << 31),
32 PCI66 = (1 << 1),
33 USE_DPLL = (1 << 0)
34};
35
36struct hpt_clock {
37 u8 xfer_speed;
38 u32 timing;
39};
40
41struct hpt_chip {
42 const char *name;
43 struct hpt_clock *clocks[3];
44};
45
46/* key for bus clock timings
47 * bit
48 * 0:3 data_high_time. inactive time of DIOW_/DIOR_ for PIO and MW
49 * DMA. cycles = value + 1
50 * 4:8 data_low_time. active time of DIOW_/DIOR_ for PIO and MW
51 * DMA. cycles = value + 1
52 * 9:12 cmd_high_time. inactive time of DIOW_/DIOR_ during task file
53 * register access.
54 * 13:17 cmd_low_time. active time of DIOW_/DIOR_ during task file
55 * register access.
56 * 18:21 udma_cycle_time. clock freq and clock cycles for UDMA xfer.
57 * during task file register access.
58 * 22:24 pre_high_time. time to initialize 1st cycle for PIO and MW DMA
59 * xfer.
60 * 25:27 cmd_pre_high_time. time to initialize 1st PIO cycle for task
61 * register access.
62 * 28 UDMA enable
63 * 29 DMA enable
64 * 30 PIO_MST enable. if set, the chip is in bus master mode during
65 * PIO.
66 * 31 FIFO enable.
67 */
Jeff Garzik85cd7252006-08-31 00:03:49 -040068
Jeff Garzik669a5db2006-08-29 18:12:40 -040069/* 66MHz DPLL clocks */
70
71static struct hpt_clock hpt3x2n_clocks[] = {
72 { XFER_UDMA_7, 0x1c869c62 },
73 { XFER_UDMA_6, 0x1c869c62 },
74 { XFER_UDMA_5, 0x1c8a9c62 },
75 { XFER_UDMA_4, 0x1c8a9c62 },
76 { XFER_UDMA_3, 0x1c8e9c62 },
77 { XFER_UDMA_2, 0x1c929c62 },
78 { XFER_UDMA_1, 0x1c9a9c62 },
79 { XFER_UDMA_0, 0x1c829c62 },
80
81 { XFER_MW_DMA_2, 0x2c829c62 },
82 { XFER_MW_DMA_1, 0x2c829c66 },
83 { XFER_MW_DMA_0, 0x2c829d2c },
84
85 { XFER_PIO_4, 0x0c829c62 },
86 { XFER_PIO_3, 0x0c829c84 },
87 { XFER_PIO_2, 0x0c829ca6 },
88 { XFER_PIO_1, 0x0d029d26 },
89 { XFER_PIO_0, 0x0d029d5e },
90 { 0, 0x0d029d5e }
91};
92
93/**
94 * hpt3x2n_find_mode - reset the hpt3x2n bus
95 * @ap: ATA port
96 * @speed: transfer mode
97 *
98 * Return the 32bit register programming information for this channel
99 * that matches the speed provided. For the moment the clocks table
100 * is hard coded but easy to change. This will be needed if we use
101 * different DPLLs
102 */
Jeff Garzik85cd7252006-08-31 00:03:49 -0400103
Jeff Garzik669a5db2006-08-29 18:12:40 -0400104static u32 hpt3x2n_find_mode(struct ata_port *ap, int speed)
105{
106 struct hpt_clock *clocks = hpt3x2n_clocks;
Jeff Garzik85cd7252006-08-31 00:03:49 -0400107
Jeff Garzik669a5db2006-08-29 18:12:40 -0400108 while(clocks->xfer_speed) {
109 if (clocks->xfer_speed == speed)
110 return clocks->timing;
111 clocks++;
112 }
113 BUG();
114 return 0xffffffffU; /* silence compiler warning */
115}
116
117/**
118 * hpt3x2n_pre_reset - reset the hpt3x2n bus
119 * @ap: ATA port to reset
120 *
121 * Perform the initial reset handling for the 3x2n series controllers.
122 * Reset the hardware and state machine, obtain the cable type.
123 */
Jeff Garzik85cd7252006-08-31 00:03:49 -0400124
Jeff Garzik669a5db2006-08-29 18:12:40 -0400125static int hpt3xn_pre_reset(struct ata_port *ap)
126{
127 u8 scr2, ata66;
128 struct pci_dev *pdev = to_pci_dev(ap->host->dev);
Jeff Garzik85cd7252006-08-31 00:03:49 -0400129
Jeff Garzik669a5db2006-08-29 18:12:40 -0400130 pci_read_config_byte(pdev, 0x5B, &scr2);
131 pci_write_config_byte(pdev, 0x5B, scr2 & ~0x01);
132 /* Cable register now active */
133 pci_read_config_byte(pdev, 0x5A, &ata66);
134 /* Restore state */
135 pci_write_config_byte(pdev, 0x5B, scr2);
Jeff Garzik85cd7252006-08-31 00:03:49 -0400136
Jeff Garzik669a5db2006-08-29 18:12:40 -0400137 if (ata66 & (1 << ap->port_no))
138 ap->cbl = ATA_CBL_PATA40;
139 else
140 ap->cbl = ATA_CBL_PATA80;
141
142 /* Reset the state machine */
Jeff Garzik85cd7252006-08-31 00:03:49 -0400143 pci_write_config_byte(pdev, 0x50, 0x37);
144 pci_write_config_byte(pdev, 0x54, 0x37);
Jeff Garzik669a5db2006-08-29 18:12:40 -0400145 udelay(100);
146
147 return ata_std_prereset(ap);
148}
Jeff Garzik85cd7252006-08-31 00:03:49 -0400149
Jeff Garzik669a5db2006-08-29 18:12:40 -0400150/**
151 * hpt3x2n_error_handler - probe the hpt3x2n bus
152 * @ap: ATA port to reset
153 *
154 * Perform the probe reset handling for the 3x2N
155 */
Jeff Garzik85cd7252006-08-31 00:03:49 -0400156
Jeff Garzik669a5db2006-08-29 18:12:40 -0400157static void hpt3x2n_error_handler(struct ata_port *ap)
158{
159 ata_bmdma_drive_eh(ap, hpt3xn_pre_reset, ata_std_softreset, NULL, ata_std_postreset);
160}
Jeff Garzik85cd7252006-08-31 00:03:49 -0400161
Jeff Garzik669a5db2006-08-29 18:12:40 -0400162/**
163 * hpt3x2n_set_piomode - PIO setup
164 * @ap: ATA interface
165 * @adev: device on the interface
166 *
Jeff Garzik85cd7252006-08-31 00:03:49 -0400167 * Perform PIO mode setup.
Jeff Garzik669a5db2006-08-29 18:12:40 -0400168 */
Jeff Garzik85cd7252006-08-31 00:03:49 -0400169
Jeff Garzik669a5db2006-08-29 18:12:40 -0400170static void hpt3x2n_set_piomode(struct ata_port *ap, struct ata_device *adev)
171{
172 struct pci_dev *pdev = to_pci_dev(ap->host->dev);
173 u32 addr1, addr2;
174 u32 reg;
175 u32 mode;
176 u8 fast;
177
178 addr1 = 0x40 + 4 * (adev->devno + 2 * ap->port_no);
179 addr2 = 0x51 + 4 * ap->port_no;
Jeff Garzik85cd7252006-08-31 00:03:49 -0400180
Jeff Garzik669a5db2006-08-29 18:12:40 -0400181 /* Fast interrupt prediction disable, hold off interrupt disable */
182 pci_read_config_byte(pdev, addr2, &fast);
183 fast &= ~0x07;
184 pci_write_config_byte(pdev, addr2, fast);
Jeff Garzik85cd7252006-08-31 00:03:49 -0400185
Jeff Garzik669a5db2006-08-29 18:12:40 -0400186 pci_read_config_dword(pdev, addr1, &reg);
187 mode = hpt3x2n_find_mode(ap, adev->pio_mode);
188 mode &= ~0x8000000; /* No FIFO in PIO */
189 mode &= ~0x30070000; /* Leave config bits alone */
190 reg &= 0x30070000; /* Strip timing bits */
191 pci_write_config_dword(pdev, addr1, reg | mode);
192}
193
194/**
195 * hpt3x2n_set_dmamode - DMA timing setup
196 * @ap: ATA interface
197 * @adev: Device being configured
198 *
199 * Set up the channel for MWDMA or UDMA modes. Much the same as with
200 * PIO, load the mode number and then set MWDMA or UDMA flag.
201 */
Jeff Garzik85cd7252006-08-31 00:03:49 -0400202
Jeff Garzik669a5db2006-08-29 18:12:40 -0400203static void hpt3x2n_set_dmamode(struct ata_port *ap, struct ata_device *adev)
204{
205 struct pci_dev *pdev = to_pci_dev(ap->host->dev);
206 u32 addr1, addr2;
207 u32 reg;
208 u32 mode;
209 u8 fast;
210
211 addr1 = 0x40 + 4 * (adev->devno + 2 * ap->port_no);
212 addr2 = 0x51 + 4 * ap->port_no;
Jeff Garzik85cd7252006-08-31 00:03:49 -0400213
Jeff Garzik669a5db2006-08-29 18:12:40 -0400214 /* Fast interrupt prediction disable, hold off interrupt disable */
215 pci_read_config_byte(pdev, addr2, &fast);
216 fast &= ~0x07;
217 pci_write_config_byte(pdev, addr2, fast);
Jeff Garzik85cd7252006-08-31 00:03:49 -0400218
Jeff Garzik669a5db2006-08-29 18:12:40 -0400219 pci_read_config_dword(pdev, addr1, &reg);
220 mode = hpt3x2n_find_mode(ap, adev->dma_mode);
221 mode |= 0x8000000; /* FIFO in MWDMA or UDMA */
222 mode &= ~0xC0000000; /* Leave config bits alone */
223 reg &= 0xC0000000; /* Strip timing bits */
224 pci_write_config_dword(pdev, addr1, reg | mode);
225}
226
227/**
228 * hpt3x2n_bmdma_end - DMA engine stop
229 * @qc: ATA command
230 *
231 * Clean up after the HPT3x2n and later DMA engine
232 */
Jeff Garzik85cd7252006-08-31 00:03:49 -0400233
Jeff Garzik669a5db2006-08-29 18:12:40 -0400234static void hpt3x2n_bmdma_stop(struct ata_queued_cmd *qc)
235{
236 struct ata_port *ap = qc->ap;
237 struct pci_dev *pdev = to_pci_dev(ap->host->dev);
238 int mscreg = 0x50 + 2 * ap->port_no;
239 u8 bwsr_stat, msc_stat;
Jeff Garzik85cd7252006-08-31 00:03:49 -0400240
Jeff Garzik669a5db2006-08-29 18:12:40 -0400241 pci_read_config_byte(pdev, 0x6A, &bwsr_stat);
242 pci_read_config_byte(pdev, mscreg, &msc_stat);
243 if (bwsr_stat & (1 << ap->port_no))
244 pci_write_config_byte(pdev, mscreg, msc_stat | 0x30);
245 ata_bmdma_stop(qc);
246}
247
248/**
249 * hpt3x2n_set_clock - clock control
250 * @ap: ATA port
251 * @source: 0x21 or 0x23 for PLL or PCI sourced clock
252 *
253 * Switch the ATA bus clock between the PLL and PCI clock sources
254 * while correctly isolating the bus and resetting internal logic
255 *
256 * We must use the DPLL for
257 * - writing
258 * - second channel UDMA7 (SATA ports) or higher
259 * - 66MHz PCI
Jeff Garzik85cd7252006-08-31 00:03:49 -0400260 *
Jeff Garzik669a5db2006-08-29 18:12:40 -0400261 * or we will underclock the device and get reduced performance.
262 */
Jeff Garzik85cd7252006-08-31 00:03:49 -0400263
Jeff Garzik669a5db2006-08-29 18:12:40 -0400264static void hpt3x2n_set_clock(struct ata_port *ap, int source)
265{
266 unsigned long bmdma = ap->ioaddr.bmdma_addr;
Jeff Garzik85cd7252006-08-31 00:03:49 -0400267
Jeff Garzik669a5db2006-08-29 18:12:40 -0400268 /* Tristate the bus */
269 outb(0x80, bmdma+0x73);
270 outb(0x80, bmdma+0x77);
Jeff Garzik85cd7252006-08-31 00:03:49 -0400271
Jeff Garzik669a5db2006-08-29 18:12:40 -0400272 /* Switch clock and reset channels */
273 outb(source, bmdma+0x7B);
274 outb(0xC0, bmdma+0x79);
Jeff Garzik85cd7252006-08-31 00:03:49 -0400275
Jeff Garzik669a5db2006-08-29 18:12:40 -0400276 /* Reset state machines */
277 outb(0x37, bmdma+0x70);
278 outb(0x37, bmdma+0x74);
Jeff Garzik85cd7252006-08-31 00:03:49 -0400279
Jeff Garzik669a5db2006-08-29 18:12:40 -0400280 /* Complete reset */
281 outb(0x00, bmdma+0x79);
Jeff Garzik85cd7252006-08-31 00:03:49 -0400282
Jeff Garzik669a5db2006-08-29 18:12:40 -0400283 /* Reconnect channels to bus */
284 outb(0x00, bmdma+0x73);
285 outb(0x00, bmdma+0x77);
286}
287
288/* Check if our partner interface is busy */
289
290static int hpt3x2n_pair_idle(struct ata_port *ap)
291{
292 struct ata_host *host = ap->host;
293 struct ata_port *pair = host->ports[ap->port_no ^ 1];
Jeff Garzik85cd7252006-08-31 00:03:49 -0400294
Jeff Garzik669a5db2006-08-29 18:12:40 -0400295 if (pair->hsm_task_state == HSM_ST_IDLE)
296 return 1;
297 return 0;
298}
299
300static int hpt3x2n_use_dpll(struct ata_port *ap, int reading)
301{
302 long flags = (long)ap->host->private_data;
303 /* See if we should use the DPLL */
304 if (reading == 0)
305 return USE_DPLL; /* Needed for write */
306 if (flags & PCI66)
307 return USE_DPLL; /* Needed at 66Mhz */
Jeff Garzik85cd7252006-08-31 00:03:49 -0400308 return 0;
Jeff Garzik669a5db2006-08-29 18:12:40 -0400309}
310
311static unsigned int hpt3x2n_qc_issue_prot(struct ata_queued_cmd *qc)
312{
313 struct ata_taskfile *tf = &qc->tf;
314 struct ata_port *ap = qc->ap;
315 int flags = (long)ap->host->private_data;
Jeff Garzik85cd7252006-08-31 00:03:49 -0400316
Jeff Garzik669a5db2006-08-29 18:12:40 -0400317 if (hpt3x2n_pair_idle(ap)) {
318 int dpll = hpt3x2n_use_dpll(ap, (tf->flags & ATA_TFLAG_WRITE));
319 if ((flags & USE_DPLL) != dpll) {
320 if (dpll == 1)
321 hpt3x2n_set_clock(ap, 0x21);
322 else
323 hpt3x2n_set_clock(ap, 0x23);
324 }
325 }
326 return ata_qc_issue_prot(qc);
327}
328
329static struct scsi_host_template hpt3x2n_sht = {
330 .module = THIS_MODULE,
331 .name = DRV_NAME,
332 .ioctl = ata_scsi_ioctl,
333 .queuecommand = ata_scsi_queuecmd,
334 .can_queue = ATA_DEF_QUEUE,
335 .this_id = ATA_SHT_THIS_ID,
336 .sg_tablesize = LIBATA_MAX_PRD,
337 .max_sectors = ATA_MAX_SECTORS,
338 .cmd_per_lun = ATA_SHT_CMD_PER_LUN,
339 .emulated = ATA_SHT_EMULATED,
340 .use_clustering = ATA_SHT_USE_CLUSTERING,
341 .proc_name = DRV_NAME,
342 .dma_boundary = ATA_DMA_BOUNDARY,
343 .slave_configure = ata_scsi_slave_config,
344 .bios_param = ata_std_bios_param,
345};
346
347/*
348 * Configuration for HPT3x2n.
349 */
Jeff Garzik85cd7252006-08-31 00:03:49 -0400350
Jeff Garzik669a5db2006-08-29 18:12:40 -0400351static struct ata_port_operations hpt3x2n_port_ops = {
352 .port_disable = ata_port_disable,
353 .set_piomode = hpt3x2n_set_piomode,
354 .set_dmamode = hpt3x2n_set_dmamode,
355 .mode_filter = ata_pci_default_filter,
Jeff Garzik85cd7252006-08-31 00:03:49 -0400356
Jeff Garzik669a5db2006-08-29 18:12:40 -0400357 .tf_load = ata_tf_load,
358 .tf_read = ata_tf_read,
359 .check_status = ata_check_status,
360 .exec_command = ata_exec_command,
361 .dev_select = ata_std_dev_select,
362
363 .freeze = ata_bmdma_freeze,
364 .thaw = ata_bmdma_thaw,
365 .error_handler = hpt3x2n_error_handler,
366 .post_internal_cmd = ata_bmdma_post_internal_cmd,
367
368 .bmdma_setup = ata_bmdma_setup,
369 .bmdma_start = ata_bmdma_start,
370 .bmdma_stop = hpt3x2n_bmdma_stop,
371 .bmdma_status = ata_bmdma_status,
372
373 .qc_prep = ata_qc_prep,
374 .qc_issue = hpt3x2n_qc_issue_prot,
375 .eng_timeout = ata_eng_timeout,
376 .data_xfer = ata_pio_data_xfer,
377
378 .irq_handler = ata_interrupt,
379 .irq_clear = ata_bmdma_irq_clear,
380
381 .port_start = ata_port_start,
382 .port_stop = ata_port_stop,
383 .host_stop = ata_host_stop
Jeff Garzik85cd7252006-08-31 00:03:49 -0400384};
Jeff Garzik669a5db2006-08-29 18:12:40 -0400385
386/**
387 * hpt3xn_calibrate_dpll - Calibrate the DPLL loop
Jeff Garzik85cd7252006-08-31 00:03:49 -0400388 * @dev: PCI device
Jeff Garzik669a5db2006-08-29 18:12:40 -0400389 *
390 * Perform a calibration cycle on the HPT3xN DPLL. Returns 1 if this
391 * succeeds
392 */
393
394static int hpt3xn_calibrate_dpll(struct pci_dev *dev)
395{
396 u8 reg5b;
397 u32 reg5c;
398 int tries;
Jeff Garzik85cd7252006-08-31 00:03:49 -0400399
Jeff Garzik669a5db2006-08-29 18:12:40 -0400400 for(tries = 0; tries < 0x5000; tries++) {
401 udelay(50);
402 pci_read_config_byte(dev, 0x5b, &reg5b);
403 if (reg5b & 0x80) {
404 /* See if it stays set */
405 for(tries = 0; tries < 0x1000; tries ++) {
406 pci_read_config_byte(dev, 0x5b, &reg5b);
407 /* Failed ? */
408 if ((reg5b & 0x80) == 0)
409 return 0;
410 }
411 /* Turn off tuning, we have the DPLL set */
412 pci_read_config_dword(dev, 0x5c, &reg5c);
413 pci_write_config_dword(dev, 0x5c, reg5c & ~ 0x100);
414 return 1;
415 }
416 }
417 /* Never went stable */
418 return 0;
419}
420
421static int hpt3x2n_pci_clock(struct pci_dev *pdev)
422{
423 unsigned long freq;
424 u32 fcnt;
Jeff Garzik85cd7252006-08-31 00:03:49 -0400425
Jeff Garzik669a5db2006-08-29 18:12:40 -0400426 pci_read_config_dword(pdev, 0x70/*CHECKME*/, &fcnt);
427 if ((fcnt >> 12) != 0xABCDE) {
428 printk(KERN_WARNING "hpt3xn: BIOS clock data not set.\n");
429 return 33; /* Not BIOS set */
430 }
431 fcnt &= 0x1FF;
Jeff Garzik85cd7252006-08-31 00:03:49 -0400432
Jeff Garzik669a5db2006-08-29 18:12:40 -0400433 freq = (fcnt * 77) / 192;
Jeff Garzik85cd7252006-08-31 00:03:49 -0400434
Jeff Garzik669a5db2006-08-29 18:12:40 -0400435 /* Clamp to bands */
436 if (freq < 40)
437 return 33;
438 if (freq < 45)
439 return 40;
440 if (freq < 55)
441 return 50;
442 return 66;
443}
444
445/**
446 * hpt3x2n_init_one - Initialise an HPT37X/302
447 * @dev: PCI device
448 * @id: Entry in match table
449 *
450 * Initialise an HPT3x2n device. There are some interesting complications
451 * here. Firstly the chip may report 366 and be one of several variants.
452 * Secondly all the timings depend on the clock for the chip which we must
453 * detect and look up
454 *
455 * This is the known chip mappings. It may be missing a couple of later
456 * releases.
457 *
458 * Chip version PCI Rev Notes
459 * HPT372 4 (HPT366) 5 Other driver
460 * HPT372N 4 (HPT366) 6 UDMA133
461 * HPT372 5 (HPT372) 1 Other driver
462 * HPT372N 5 (HPT372) 2 UDMA133
463 * HPT302 6 (HPT302) * Other driver
464 * HPT302N 6 (HPT302) > 1 UDMA133
465 * HPT371 7 (HPT371) * Other driver
466 * HPT371N 7 (HPT371) > 1 UDMA133
467 * HPT374 8 (HPT374) * Other driver
468 * HPT372N 9 (HPT372N) * UDMA133
469 *
470 * (1) UDMA133 support depends on the bus clock
471 *
472 * To pin down HPT371N
473 */
Jeff Garzik85cd7252006-08-31 00:03:49 -0400474
Jeff Garzik669a5db2006-08-29 18:12:40 -0400475static int hpt3x2n_init_one(struct pci_dev *dev, const struct pci_device_id *id)
476{
477 /* HPT372N and friends - UDMA133 */
478 static struct ata_port_info info = {
479 .sht = &hpt3x2n_sht,
480 .flags = ATA_FLAG_SLAVE_POSS | ATA_FLAG_SRST,
481 .pio_mask = 0x1f,
482 .mwdma_mask = 0x07,
483 .udma_mask = 0x7f,
484 .port_ops = &hpt3x2n_port_ops
485 };
486 struct ata_port_info *port_info[2];
487 struct ata_port_info *port = &info;
488
489 u8 irqmask;
490 u32 class_rev;
Jeff Garzik85cd7252006-08-31 00:03:49 -0400491
Jeff Garzik669a5db2006-08-29 18:12:40 -0400492 unsigned int pci_mhz;
493 unsigned int f_low, f_high;
494 int adjust;
Jeff Garzik85cd7252006-08-31 00:03:49 -0400495
Jeff Garzik669a5db2006-08-29 18:12:40 -0400496 pci_read_config_dword(dev, PCI_CLASS_REVISION, &class_rev);
497 class_rev &= 0xFF;
Jeff Garzik85cd7252006-08-31 00:03:49 -0400498
Jeff Garzik669a5db2006-08-29 18:12:40 -0400499 switch(dev->device) {
500 case PCI_DEVICE_ID_TTI_HPT366:
501 if (class_rev < 6)
502 return -ENODEV;
503 break;
504 case PCI_DEVICE_ID_TTI_HPT372:
505 /* 372N if rev >= 1*/
506 if (class_rev == 0)
507 return -ENODEV;
508 break;
509 case PCI_DEVICE_ID_TTI_HPT302:
510 if (class_rev < 2)
511 return -ENODEV;
512 break;
513 case PCI_DEVICE_ID_TTI_HPT372N:
514 break;
515 default:
516 printk(KERN_ERR "pata_hpt3x2n: PCI table is bogus please report (%d).\n", dev->device);
517 return -ENODEV;
518 }
519
520 /* Ok so this is a chip we support */
521
522 pci_write_config_byte(dev, PCI_CACHE_LINE_SIZE, (L1_CACHE_BYTES / 4));
523 pci_write_config_byte(dev, PCI_LATENCY_TIMER, 0x78);
524 pci_write_config_byte(dev, PCI_MIN_GNT, 0x08);
525 pci_write_config_byte(dev, PCI_MAX_LAT, 0x08);
526
527 pci_read_config_byte(dev, 0x5A, &irqmask);
528 irqmask &= ~0x10;
529 pci_write_config_byte(dev, 0x5a, irqmask);
530
531 /* Tune the PLL. HPT recommend using 75 for SATA, 66 for UDMA133 or
532 50 for UDMA100. Right now we always use 66 */
Jeff Garzik85cd7252006-08-31 00:03:49 -0400533
Jeff Garzik669a5db2006-08-29 18:12:40 -0400534 pci_mhz = hpt3x2n_pci_clock(dev);
Jeff Garzik85cd7252006-08-31 00:03:49 -0400535
Jeff Garzik669a5db2006-08-29 18:12:40 -0400536 f_low = (pci_mhz * 48) / 66; /* PCI Mhz for 66Mhz DPLL */
537 f_high = f_low + 2; /* Tolerance */
Jeff Garzik85cd7252006-08-31 00:03:49 -0400538
Jeff Garzik669a5db2006-08-29 18:12:40 -0400539 pci_write_config_dword(dev, 0x5C, (f_high << 16) | f_low | 0x100);
540 /* PLL clock */
541 pci_write_config_byte(dev, 0x5B, 0x21);
Jeff Garzik85cd7252006-08-31 00:03:49 -0400542
Jeff Garzik669a5db2006-08-29 18:12:40 -0400543 /* Unlike the 37x we don't try jiggling the frequency */
544 for(adjust = 0; adjust < 8; adjust++) {
545 if (hpt3xn_calibrate_dpll(dev))
546 break;
547 pci_write_config_dword(dev, 0x5C, (f_high << 16) | f_low);
548 }
549 if (adjust == 8)
550 printk(KERN_WARNING "hpt3xn: DPLL did not stabilize.\n");
551
552 /* Set our private data up. We only need a few flags so we use
553 it directly */
554 port->private_data = NULL;
555 if (pci_mhz > 60)
556 port->private_data = (void *)PCI66;
Jeff Garzik85cd7252006-08-31 00:03:49 -0400557
Jeff Garzik669a5db2006-08-29 18:12:40 -0400558 /* Now kick off ATA set up */
559 port_info[0] = port_info[1] = port;
560 return ata_pci_init_one(dev, port_info, 2);
561}
562
563static struct pci_device_id hpt3x2n[] = {
564 { PCI_DEVICE(PCI_VENDOR_ID_TTI, PCI_DEVICE_ID_TTI_HPT366), },
565 { PCI_DEVICE(PCI_VENDOR_ID_TTI, PCI_DEVICE_ID_TTI_HPT372), },
566 { PCI_DEVICE(PCI_VENDOR_ID_TTI, PCI_DEVICE_ID_TTI_HPT302), },
567 { PCI_DEVICE(PCI_VENDOR_ID_TTI, PCI_DEVICE_ID_TTI_HPT372N), },
568 { 0, },
569};
570
571static struct pci_driver hpt3x2n_pci_driver = {
572 .name = DRV_NAME,
573 .id_table = hpt3x2n,
574 .probe = hpt3x2n_init_one,
575 .remove = ata_pci_remove_one
576};
577
578static int __init hpt3x2n_init(void)
579{
580 return pci_register_driver(&hpt3x2n_pci_driver);
581}
582
583
584static void __exit hpt3x2n_exit(void)
585{
586 pci_unregister_driver(&hpt3x2n_pci_driver);
587}
588
589
590MODULE_AUTHOR("Alan Cox");
591MODULE_DESCRIPTION("low-level driver for the Highpoint HPT3x2n/30x");
592MODULE_LICENSE("GPL");
593MODULE_DEVICE_TABLE(pci, hpt3x2n);
594MODULE_VERSION(DRV_VERSION);
595
596module_init(hpt3x2n_init);
597module_exit(hpt3x2n_exit);