Hirokazu Takata | 2368086 | 2005-06-21 17:16:10 -0700 | [diff] [blame] | 1 | /* |
Hirokazu Takata | 3264f97 | 2007-08-01 21:09:31 +0900 | [diff] [blame] | 2 | * linux/arch/m32r/platforms/mappi3/setup.c |
Hirokazu Takata | 2368086 | 2005-06-21 17:16:10 -0700 | [diff] [blame] | 3 | * |
| 4 | * Setup routines for Renesas MAPPI-III(M3A-2170) Board |
| 5 | * |
Hirokazu Takata | 316240f | 2005-07-07 17:59:32 -0700 | [diff] [blame] | 6 | * Copyright (c) 2001-2005 Hiroyuki Kondo, Hirokazu Takata, |
| 7 | * Hitoshi Yamamoto, Mamoru Sakugawa |
Hirokazu Takata | 2368086 | 2005-06-21 17:16:10 -0700 | [diff] [blame] | 8 | */ |
| 9 | |
Hirokazu Takata | 2368086 | 2005-06-21 17:16:10 -0700 | [diff] [blame] | 10 | #include <linux/irq.h> |
| 11 | #include <linux/kernel.h> |
| 12 | #include <linux/init.h> |
Russell King | d052d1b | 2005-10-29 19:07:23 +0100 | [diff] [blame] | 13 | #include <linux/platform_device.h> |
Hirokazu Takata | 2368086 | 2005-06-21 17:16:10 -0700 | [diff] [blame] | 14 | |
| 15 | #include <asm/system.h> |
| 16 | #include <asm/m32r.h> |
| 17 | #include <asm/io.h> |
| 18 | |
| 19 | #define irq2port(x) (M32R_ICU_CR1_PORTL + ((x - 1) * sizeof(unsigned long))) |
| 20 | |
Hirokazu Takata | 2368086 | 2005-06-21 17:16:10 -0700 | [diff] [blame] | 21 | icu_data_t icu_data[NR_IRQS]; |
| 22 | |
| 23 | static void disable_mappi3_irq(unsigned int irq) |
| 24 | { |
| 25 | unsigned long port, data; |
| 26 | |
| 27 | if ((irq == 0) ||(irq >= NR_IRQS)) { |
| 28 | printk("bad irq 0x%08x\n", irq); |
| 29 | return; |
| 30 | } |
| 31 | port = irq2port(irq); |
| 32 | data = icu_data[irq].icucr|M32R_ICUCR_ILEVEL7; |
| 33 | outl(data, port); |
| 34 | } |
| 35 | |
| 36 | static void enable_mappi3_irq(unsigned int irq) |
| 37 | { |
| 38 | unsigned long port, data; |
| 39 | |
| 40 | if ((irq == 0) ||(irq >= NR_IRQS)) { |
| 41 | printk("bad irq 0x%08x\n", irq); |
| 42 | return; |
| 43 | } |
| 44 | port = irq2port(irq); |
| 45 | data = icu_data[irq].icucr|M32R_ICUCR_IEN|M32R_ICUCR_ILEVEL6; |
| 46 | outl(data, port); |
| 47 | } |
| 48 | |
| 49 | static void mask_and_ack_mappi3(unsigned int irq) |
| 50 | { |
| 51 | disable_mappi3_irq(irq); |
| 52 | } |
| 53 | |
| 54 | static void end_mappi3_irq(unsigned int irq) |
| 55 | { |
| 56 | enable_mappi3_irq(irq); |
| 57 | } |
| 58 | |
| 59 | static unsigned int startup_mappi3_irq(unsigned int irq) |
| 60 | { |
| 61 | enable_mappi3_irq(irq); |
| 62 | return (0); |
| 63 | } |
| 64 | |
| 65 | static void shutdown_mappi3_irq(unsigned int irq) |
| 66 | { |
| 67 | unsigned long port; |
| 68 | |
| 69 | port = irq2port(irq); |
| 70 | outl(M32R_ICUCR_ILEVEL7, port); |
| 71 | } |
| 72 | |
Thomas Gleixner | 189e91f | 2009-06-16 15:33:26 -0700 | [diff] [blame] | 73 | static struct irq_chip mappi3_irq_type = |
Hirokazu Takata | 2368086 | 2005-06-21 17:16:10 -0700 | [diff] [blame] | 74 | { |
Thomas Gleixner | d1ea13c | 2010-09-23 18:40:07 +0200 | [diff] [blame] | 75 | .name = "MAPPI3-IRQ", |
Hirokazu Takata | 6f973b0 | 2005-06-21 17:16:13 -0700 | [diff] [blame] | 76 | .startup = startup_mappi3_irq, |
| 77 | .shutdown = shutdown_mappi3_irq, |
| 78 | .enable = enable_mappi3_irq, |
| 79 | .disable = disable_mappi3_irq, |
| 80 | .ack = mask_and_ack_mappi3, |
| 81 | .end = end_mappi3_irq |
Hirokazu Takata | 2368086 | 2005-06-21 17:16:10 -0700 | [diff] [blame] | 82 | }; |
| 83 | |
| 84 | void __init init_IRQ(void) |
| 85 | { |
| 86 | #if defined(CONFIG_SMC91X) |
| 87 | /* INT0 : LAN controller (SMC91111) */ |
| 88 | irq_desc[M32R_IRQ_INT0].status = IRQ_DISABLED; |
Ingo Molnar | d1bef4e | 2006-06-29 02:24:36 -0700 | [diff] [blame] | 89 | irq_desc[M32R_IRQ_INT0].chip = &mappi3_irq_type; |
Hirokazu Takata | 2368086 | 2005-06-21 17:16:10 -0700 | [diff] [blame] | 90 | irq_desc[M32R_IRQ_INT0].action = 0; |
| 91 | irq_desc[M32R_IRQ_INT0].depth = 1; |
| 92 | icu_data[M32R_IRQ_INT0].icucr = M32R_ICUCR_IEN|M32R_ICUCR_ISMOD10; |
| 93 | disable_mappi3_irq(M32R_IRQ_INT0); |
| 94 | #endif /* CONFIG_SMC91X */ |
| 95 | |
| 96 | /* MFT2 : system timer */ |
| 97 | irq_desc[M32R_IRQ_MFT2].status = IRQ_DISABLED; |
Ingo Molnar | d1bef4e | 2006-06-29 02:24:36 -0700 | [diff] [blame] | 98 | irq_desc[M32R_IRQ_MFT2].chip = &mappi3_irq_type; |
Hirokazu Takata | 2368086 | 2005-06-21 17:16:10 -0700 | [diff] [blame] | 99 | irq_desc[M32R_IRQ_MFT2].action = 0; |
| 100 | irq_desc[M32R_IRQ_MFT2].depth = 1; |
| 101 | icu_data[M32R_IRQ_MFT2].icucr = M32R_ICUCR_IEN; |
| 102 | disable_mappi3_irq(M32R_IRQ_MFT2); |
| 103 | |
| 104 | #ifdef CONFIG_SERIAL_M32R_SIO |
| 105 | /* SIO0_R : uart receive data */ |
| 106 | irq_desc[M32R_IRQ_SIO0_R].status = IRQ_DISABLED; |
Ingo Molnar | d1bef4e | 2006-06-29 02:24:36 -0700 | [diff] [blame] | 107 | irq_desc[M32R_IRQ_SIO0_R].chip = &mappi3_irq_type; |
Hirokazu Takata | 2368086 | 2005-06-21 17:16:10 -0700 | [diff] [blame] | 108 | irq_desc[M32R_IRQ_SIO0_R].action = 0; |
| 109 | irq_desc[M32R_IRQ_SIO0_R].depth = 1; |
| 110 | icu_data[M32R_IRQ_SIO0_R].icucr = 0; |
| 111 | disable_mappi3_irq(M32R_IRQ_SIO0_R); |
| 112 | |
| 113 | /* SIO0_S : uart send data */ |
| 114 | irq_desc[M32R_IRQ_SIO0_S].status = IRQ_DISABLED; |
Ingo Molnar | d1bef4e | 2006-06-29 02:24:36 -0700 | [diff] [blame] | 115 | irq_desc[M32R_IRQ_SIO0_S].chip = &mappi3_irq_type; |
Hirokazu Takata | 2368086 | 2005-06-21 17:16:10 -0700 | [diff] [blame] | 116 | irq_desc[M32R_IRQ_SIO0_S].action = 0; |
| 117 | irq_desc[M32R_IRQ_SIO0_S].depth = 1; |
| 118 | icu_data[M32R_IRQ_SIO0_S].icucr = 0; |
| 119 | disable_mappi3_irq(M32R_IRQ_SIO0_S); |
| 120 | /* SIO1_R : uart receive data */ |
| 121 | irq_desc[M32R_IRQ_SIO1_R].status = IRQ_DISABLED; |
Ingo Molnar | d1bef4e | 2006-06-29 02:24:36 -0700 | [diff] [blame] | 122 | irq_desc[M32R_IRQ_SIO1_R].chip = &mappi3_irq_type; |
Hirokazu Takata | 2368086 | 2005-06-21 17:16:10 -0700 | [diff] [blame] | 123 | irq_desc[M32R_IRQ_SIO1_R].action = 0; |
| 124 | irq_desc[M32R_IRQ_SIO1_R].depth = 1; |
| 125 | icu_data[M32R_IRQ_SIO1_R].icucr = 0; |
| 126 | disable_mappi3_irq(M32R_IRQ_SIO1_R); |
| 127 | |
| 128 | /* SIO1_S : uart send data */ |
| 129 | irq_desc[M32R_IRQ_SIO1_S].status = IRQ_DISABLED; |
Ingo Molnar | d1bef4e | 2006-06-29 02:24:36 -0700 | [diff] [blame] | 130 | irq_desc[M32R_IRQ_SIO1_S].chip = &mappi3_irq_type; |
Hirokazu Takata | 2368086 | 2005-06-21 17:16:10 -0700 | [diff] [blame] | 131 | irq_desc[M32R_IRQ_SIO1_S].action = 0; |
| 132 | irq_desc[M32R_IRQ_SIO1_S].depth = 1; |
| 133 | icu_data[M32R_IRQ_SIO1_S].icucr = 0; |
| 134 | disable_mappi3_irq(M32R_IRQ_SIO1_S); |
| 135 | #endif /* CONFIG_M32R_USE_DBG_CONSOLE */ |
| 136 | |
| 137 | #if defined(CONFIG_USB) |
| 138 | /* INT1 : USB Host controller interrupt */ |
| 139 | irq_desc[M32R_IRQ_INT1].status = IRQ_DISABLED; |
Ingo Molnar | d1bef4e | 2006-06-29 02:24:36 -0700 | [diff] [blame] | 140 | irq_desc[M32R_IRQ_INT1].chip = &mappi3_irq_type; |
Hirokazu Takata | 2368086 | 2005-06-21 17:16:10 -0700 | [diff] [blame] | 141 | irq_desc[M32R_IRQ_INT1].action = 0; |
| 142 | irq_desc[M32R_IRQ_INT1].depth = 1; |
| 143 | icu_data[M32R_IRQ_INT1].icucr = M32R_ICUCR_ISMOD01; |
| 144 | disable_mappi3_irq(M32R_IRQ_INT1); |
| 145 | #endif /* CONFIG_USB */ |
| 146 | |
Hirokazu Takata | ad09d58 | 2005-11-28 13:44:00 -0800 | [diff] [blame] | 147 | /* CFC IREQ */ |
Hirokazu Takata | 2368086 | 2005-06-21 17:16:10 -0700 | [diff] [blame] | 148 | irq_desc[PLD_IRQ_CFIREQ].status = IRQ_DISABLED; |
Ingo Molnar | d1bef4e | 2006-06-29 02:24:36 -0700 | [diff] [blame] | 149 | irq_desc[PLD_IRQ_CFIREQ].chip = &mappi3_irq_type; |
Hirokazu Takata | 2368086 | 2005-06-21 17:16:10 -0700 | [diff] [blame] | 150 | irq_desc[PLD_IRQ_CFIREQ].action = 0; |
| 151 | irq_desc[PLD_IRQ_CFIREQ].depth = 1; /* disable nested irq */ |
| 152 | icu_data[PLD_IRQ_CFIREQ].icucr = M32R_ICUCR_IEN|M32R_ICUCR_ISMOD01; |
| 153 | disable_mappi3_irq(PLD_IRQ_CFIREQ); |
| 154 | |
| 155 | #if defined(CONFIG_M32R_CFC) |
Hirokazu Takata | ad09d58 | 2005-11-28 13:44:00 -0800 | [diff] [blame] | 156 | /* ICUCR41: CFC Insert & eject */ |
Hirokazu Takata | 2368086 | 2005-06-21 17:16:10 -0700 | [diff] [blame] | 157 | irq_desc[PLD_IRQ_CFC_INSERT].status = IRQ_DISABLED; |
Ingo Molnar | d1bef4e | 2006-06-29 02:24:36 -0700 | [diff] [blame] | 158 | irq_desc[PLD_IRQ_CFC_INSERT].chip = &mappi3_irq_type; |
Hirokazu Takata | 2368086 | 2005-06-21 17:16:10 -0700 | [diff] [blame] | 159 | irq_desc[PLD_IRQ_CFC_INSERT].action = 0; |
| 160 | irq_desc[PLD_IRQ_CFC_INSERT].depth = 1; /* disable nested irq */ |
| 161 | icu_data[PLD_IRQ_CFC_INSERT].icucr = M32R_ICUCR_IEN|M32R_ICUCR_ISMOD00; |
| 162 | disable_mappi3_irq(PLD_IRQ_CFC_INSERT); |
| 163 | |
Hirokazu Takata | 2368086 | 2005-06-21 17:16:10 -0700 | [diff] [blame] | 164 | #endif /* CONFIG_M32R_CFC */ |
Hirokazu Takata | ad09d58 | 2005-11-28 13:44:00 -0800 | [diff] [blame] | 165 | |
| 166 | /* IDE IREQ */ |
| 167 | irq_desc[PLD_IRQ_IDEIREQ].status = IRQ_DISABLED; |
Ingo Molnar | d1bef4e | 2006-06-29 02:24:36 -0700 | [diff] [blame] | 168 | irq_desc[PLD_IRQ_IDEIREQ].chip = &mappi3_irq_type; |
Hirokazu Takata | ad09d58 | 2005-11-28 13:44:00 -0800 | [diff] [blame] | 169 | irq_desc[PLD_IRQ_IDEIREQ].action = 0; |
| 170 | irq_desc[PLD_IRQ_IDEIREQ].depth = 1; /* disable nested irq */ |
| 171 | icu_data[PLD_IRQ_IDEIREQ].icucr = M32R_ICUCR_IEN|M32R_ICUCR_ISMOD10; |
| 172 | disable_mappi3_irq(PLD_IRQ_IDEIREQ); |
| 173 | |
Hirokazu Takata | 2368086 | 2005-06-21 17:16:10 -0700 | [diff] [blame] | 174 | } |
| 175 | |
Hirokazu Takata | 316240f | 2005-07-07 17:59:32 -0700 | [diff] [blame] | 176 | #if defined(CONFIG_SMC91X) |
| 177 | |
Hirokazu Takata | 2368086 | 2005-06-21 17:16:10 -0700 | [diff] [blame] | 178 | #define LAN_IOSTART 0x300 |
| 179 | #define LAN_IOEND 0x320 |
| 180 | static struct resource smc91x_resources[] = { |
| 181 | [0] = { |
| 182 | .start = (LAN_IOSTART), |
| 183 | .end = (LAN_IOEND), |
| 184 | .flags = IORESOURCE_MEM, |
| 185 | }, |
| 186 | [1] = { |
| 187 | .start = M32R_IRQ_INT0, |
| 188 | .end = M32R_IRQ_INT0, |
| 189 | .flags = IORESOURCE_IRQ, |
| 190 | } |
| 191 | }; |
| 192 | |
| 193 | static struct platform_device smc91x_device = { |
| 194 | .name = "smc91x", |
| 195 | .id = 0, |
| 196 | .num_resources = ARRAY_SIZE(smc91x_resources), |
| 197 | .resource = smc91x_resources, |
| 198 | }; |
| 199 | |
Hirokazu Takata | 316240f | 2005-07-07 17:59:32 -0700 | [diff] [blame] | 200 | #endif |
| 201 | |
| 202 | #if defined(CONFIG_FB_S1D13XXX) |
| 203 | |
| 204 | #include <video/s1d13xxxfb.h> |
| 205 | #include <asm/s1d13806.h> |
| 206 | |
| 207 | static struct s1d13xxxfb_pdata s1d13xxxfb_data = { |
| 208 | .initregs = s1d13xxxfb_initregs, |
| 209 | .initregssize = ARRAY_SIZE(s1d13xxxfb_initregs), |
| 210 | .platform_init_video = NULL, |
| 211 | #ifdef CONFIG_PM |
| 212 | .platform_suspend_video = NULL, |
| 213 | .platform_resume_video = NULL, |
| 214 | #endif |
| 215 | }; |
| 216 | |
| 217 | static struct resource s1d13xxxfb_resources[] = { |
| 218 | [0] = { |
| 219 | .start = 0x1d600000UL, |
| 220 | .end = 0x1d73FFFFUL, |
| 221 | .flags = IORESOURCE_MEM, |
| 222 | }, |
| 223 | [1] = { |
| 224 | .start = 0x1d400000UL, |
| 225 | .end = 0x1d4001FFUL, |
| 226 | .flags = IORESOURCE_MEM, |
| 227 | } |
| 228 | }; |
| 229 | |
| 230 | static struct platform_device s1d13xxxfb_device = { |
| 231 | .name = S1D_DEVICENAME, |
| 232 | .id = 0, |
| 233 | .dev = { |
| 234 | .platform_data = &s1d13xxxfb_data, |
| 235 | }, |
| 236 | .num_resources = ARRAY_SIZE(s1d13xxxfb_resources), |
| 237 | .resource = s1d13xxxfb_resources, |
| 238 | }; |
| 239 | #endif |
| 240 | |
Hirokazu Takata | 2368086 | 2005-06-21 17:16:10 -0700 | [diff] [blame] | 241 | static int __init platform_init(void) |
| 242 | { |
Hirokazu Takata | 316240f | 2005-07-07 17:59:32 -0700 | [diff] [blame] | 243 | #if defined(CONFIG_SMC91X) |
Hirokazu Takata | 2368086 | 2005-06-21 17:16:10 -0700 | [diff] [blame] | 244 | platform_device_register(&smc91x_device); |
Hirokazu Takata | 316240f | 2005-07-07 17:59:32 -0700 | [diff] [blame] | 245 | #endif |
| 246 | #if defined(CONFIG_FB_S1D13XXX) |
| 247 | platform_device_register(&s1d13xxxfb_device); |
| 248 | #endif |
Hirokazu Takata | 2368086 | 2005-06-21 17:16:10 -0700 | [diff] [blame] | 249 | return 0; |
| 250 | } |
| 251 | arch_initcall(platform_init); |