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Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07001/* include/asm-arm/arch-msm/msm_adsp.h
2 *
3 * Copyright (C) 2008 Google, Inc.
Manish Dewangan8e87bc12012-02-09 20:25:15 +05304 * Copyright (c) 2009-2010, 2012 Code Aurora Forum. All rights reserved.
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07005 *
6 * This software is licensed under the terms of the GNU General Public
7 * License version 2, as published by the Free Software Foundation, and
8 * may be copied, distributed, and modified under those terms.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 *
15 */
16
17#ifndef __ASM__ARCH_MSM_ADSP_H
18#define __ASM__ARCH_MSM_ADSP_H
19
20struct msm_adsp_module;
21
22struct msm_adsp_ops {
23 /* event is called from interrupt context when a message
24 * arrives from the DSP. Use the provided function pointer
25 * to copy the message into a local buffer. Do NOT call
26 * it multiple times.
27 */
28 void (*event)(void *driver_data, unsigned id, size_t len,
29 void (*getevent)(void *ptr, size_t len));
30};
31
32/* Get, Put, Enable, and Disable are synchronous and must only
33 * be called from thread context. Enable and Disable will block
34 * up to one second in the event of a fatal DSP error but are
35 * much faster otherwise.
36 */
37int msm_adsp_get(const char *name, struct msm_adsp_module **module,
38 struct msm_adsp_ops *ops, void *driver_data);
39void msm_adsp_put(struct msm_adsp_module *module);
40int msm_adsp_enable(struct msm_adsp_module *module);
41int msm_adsp_disable(struct msm_adsp_module *module);
42int adsp_set_clkrate(struct msm_adsp_module *module, unsigned long clk_rate);
43int msm_adsp_disable_event_rsp(struct msm_adsp_module *module);
44int32_t get_adsp_resource(unsigned short client_idx,
45 void *cmd_buf, size_t cmd_size);
46int32_t put_adsp_resource(unsigned short client_idx,
47 void *cmd_buf, size_t cmd_size);
48
49/* Write is safe to call from interrupt context.
50 */
51int msm_adsp_write(struct msm_adsp_module *module,
52 unsigned queue_id,
53 void *data, size_t len);
54
Manish Dewangan8e87bc12012-02-09 20:25:15 +053055/*Explicitly gererate adsp event */
56int msm_adsp_generate_event(void *data,
57 struct msm_adsp_module *mod,
58 unsigned event_id,
59 unsigned event_length,
60 unsigned event_size,
61 void *msg);
62
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -070063#define ADSP_MESSAGE_ID 0xFFFF
64
65/* Command Queue Indexes */
66#define QDSP_lpmCommandQueue 0
67#define QDSP_mpuAfeQueue 1
68#define QDSP_mpuGraphicsCmdQueue 2
69#define QDSP_mpuModmathCmdQueue 3
70#define QDSP_mpuVDecCmdQueue 4
71#define QDSP_mpuVDecPktQueue 5
72#define QDSP_mpuVEncCmdQueue 6
73#define QDSP_rxMpuDecCmdQueue 7
74#define QDSP_rxMpuDecPktQueue 8
75#define QDSP_txMpuEncQueue 9
76#define QDSP_uPAudPPCmd1Queue 10
77#define QDSP_uPAudPPCmd2Queue 11
78#define QDSP_uPAudPPCmd3Queue 12
79#define QDSP_uPAudPlay0BitStreamCtrlQueue 13
80#define QDSP_uPAudPlay1BitStreamCtrlQueue 14
81#define QDSP_uPAudPlay2BitStreamCtrlQueue 15
82#define QDSP_uPAudPlay3BitStreamCtrlQueue 16
83#define QDSP_uPAudPlay4BitStreamCtrlQueue 17
84#define QDSP_uPAudPreProcCmdQueue 18
85#define QDSP_uPAudRecBitStreamQueue 19
86#define QDSP_uPAudRecCmdQueue 20
87#define QDSP_uPDiagQueue 21
88#define QDSP_uPJpegActionCmdQueue 22
89#define QDSP_uPJpegCfgCmdQueue 23
90#define QDSP_uPVocProcQueue 24
91#define QDSP_vfeCommandQueue 25
92#define QDSP_vfeCommandScaleQueue 26
93#define QDSP_vfeCommandTableQueue 27
94#define QDSP_vfeFtmCmdQueue 28
95#define QDSP_vfeFtmCmdScaleQueue 29
96#define QDSP_vfeFtmCmdTableQueue 30
97#define QDSP_uPJpegFtmCfgCmdQueue 31
98#define QDSP_uPJpegFtmActionCmdQueue 32
99#define QDSP_apuAfeQueue 33
100#define QDSP_mpuRmtQueue 34
101#define QDSP_uPAudPreProcAudRecCmdQueue 35
102#define QDSP_uPAudRec0BitStreamQueue 36
103#define QDSP_uPAudRec0CmdQueue 37
104#define QDSP_uPAudRec1BitStreamQueue 38
105#define QDSP_uPAudRec1CmdQueue 39
106#define QDSP_apuRmtQueue 40
107#define QDSP_uPAudRec2BitStreamQueue 41
108#define QDSP_uPAudRec2CmdQueue 42
109#define QDSP_MAX_NUM_QUEUES 43
110
111#endif