blob: 6db478601024e60ceb60c65692cae72a8c5482f5 [file] [log] [blame]
Sandeep Paulraj358934a2009-12-16 22:02:18 +00001/*
2 * Copyright (C) 2009 Texas Instruments.
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation; either version 2 of the License, or
7 * (at your option) any later version.
8 *
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
13 *
14 * You should have received a copy of the GNU General Public License
15 * along with this program; if not, write to the Free Software
16 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
17 */
18
19#include <linux/interrupt.h>
20#include <linux/io.h>
21#include <linux/gpio.h>
22#include <linux/module.h>
23#include <linux/delay.h>
24#include <linux/platform_device.h>
25#include <linux/err.h>
26#include <linux/clk.h>
27#include <linux/dma-mapping.h>
28#include <linux/spi/spi.h>
29#include <linux/spi/spi_bitbang.h>
Tejun Heo5a0e3ad2010-03-24 17:04:11 +090030#include <linux/slab.h>
Sandeep Paulraj358934a2009-12-16 22:02:18 +000031
32#include <mach/spi.h>
33#include <mach/edma.h>
34
35#define SPI_NO_RESOURCE ((resource_size_t)-1)
36
37#define SPI_MAX_CHIPSELECT 2
38
39#define CS_DEFAULT 0xFF
40
Sandeep Paulraj358934a2009-12-16 22:02:18 +000041#define SPIFMT_PHASE_MASK BIT(16)
42#define SPIFMT_POLARITY_MASK BIT(17)
43#define SPIFMT_DISTIMER_MASK BIT(18)
44#define SPIFMT_SHIFTDIR_MASK BIT(20)
45#define SPIFMT_WAITENA_MASK BIT(21)
46#define SPIFMT_PARITYENA_MASK BIT(22)
47#define SPIFMT_ODD_PARITY_MASK BIT(23)
48#define SPIFMT_WDELAY_MASK 0x3f000000u
49#define SPIFMT_WDELAY_SHIFT 24
Brian Niebuhr7fe00922010-08-13 13:27:23 +053050#define SPIFMT_PRESCALE_SHIFT 8
Sandeep Paulraj358934a2009-12-16 22:02:18 +000051
Sandeep Paulraj358934a2009-12-16 22:02:18 +000052
53/* SPIPC0 */
54#define SPIPC0_DIFUN_MASK BIT(11) /* MISO */
55#define SPIPC0_DOFUN_MASK BIT(10) /* MOSI */
56#define SPIPC0_CLKFUN_MASK BIT(9) /* CLK */
57#define SPIPC0_SPIENA_MASK BIT(8) /* nREADY */
Sandeep Paulraj358934a2009-12-16 22:02:18 +000058
59#define SPIINT_MASKALL 0x0101035F
Brian Niebuhre0d205e2010-09-02 16:52:06 +053060#define SPIINT_MASKINT 0x0000015F
61#define SPI_INTLVL_1 0x000001FF
62#define SPI_INTLVL_0 0x00000000
Sandeep Paulraj358934a2009-12-16 22:02:18 +000063
Brian Niebuhrcfbc5d12010-08-12 12:27:33 +053064/* SPIDAT1 (upper 16 bit defines) */
65#define SPIDAT1_CSHOLD_MASK BIT(12)
66
67/* SPIGCR1 */
Sandeep Paulraj358934a2009-12-16 22:02:18 +000068#define SPIGCR1_CLKMOD_MASK BIT(1)
69#define SPIGCR1_MASTER_MASK BIT(0)
70#define SPIGCR1_LOOPBACK_MASK BIT(16)
Sekhar Nori8e206f12010-08-20 16:20:49 +053071#define SPIGCR1_SPIENA_MASK BIT(24)
Sandeep Paulraj358934a2009-12-16 22:02:18 +000072
73/* SPIBUF */
74#define SPIBUF_TXFULL_MASK BIT(29)
75#define SPIBUF_RXEMPTY_MASK BIT(31)
76
Brian Niebuhr7abbf232010-08-19 15:07:38 +053077/* SPIDELAY */
78#define SPIDELAY_C2TDELAY_SHIFT 24
79#define SPIDELAY_C2TDELAY_MASK (0xFF << SPIDELAY_C2TDELAY_SHIFT)
80#define SPIDELAY_T2CDELAY_SHIFT 16
81#define SPIDELAY_T2CDELAY_MASK (0xFF << SPIDELAY_T2CDELAY_SHIFT)
82#define SPIDELAY_T2EDELAY_SHIFT 8
83#define SPIDELAY_T2EDELAY_MASK (0xFF << SPIDELAY_T2EDELAY_SHIFT)
84#define SPIDELAY_C2EDELAY_SHIFT 0
85#define SPIDELAY_C2EDELAY_MASK 0xFF
86
Sandeep Paulraj358934a2009-12-16 22:02:18 +000087/* Error Masks */
88#define SPIFLG_DLEN_ERR_MASK BIT(0)
89#define SPIFLG_TIMEOUT_MASK BIT(1)
90#define SPIFLG_PARERR_MASK BIT(2)
91#define SPIFLG_DESYNC_MASK BIT(3)
92#define SPIFLG_BITERR_MASK BIT(4)
93#define SPIFLG_OVRRUN_MASK BIT(6)
Sandeep Paulraj358934a2009-12-16 22:02:18 +000094#define SPIFLG_BUF_INIT_ACTIVE_MASK BIT(24)
Brian Niebuhr839c9962010-08-23 16:39:19 +053095#define SPIFLG_ERROR_MASK (SPIFLG_DLEN_ERR_MASK \
96 | SPIFLG_TIMEOUT_MASK | SPIFLG_PARERR_MASK \
97 | SPIFLG_DESYNC_MASK | SPIFLG_BITERR_MASK \
98 | SPIFLG_OVRRUN_MASK)
Sandeep Paulraj358934a2009-12-16 22:02:18 +000099
Sandeep Paulraj358934a2009-12-16 22:02:18 +0000100#define SPIINT_DMA_REQ_EN BIT(16)
Sandeep Paulraj358934a2009-12-16 22:02:18 +0000101
Sandeep Paulraj358934a2009-12-16 22:02:18 +0000102/* SPI Controller registers */
103#define SPIGCR0 0x00
104#define SPIGCR1 0x04
105#define SPIINT 0x08
106#define SPILVL 0x0c
107#define SPIFLG 0x10
108#define SPIPC0 0x14
Sandeep Paulraj358934a2009-12-16 22:02:18 +0000109#define SPIDAT1 0x3c
110#define SPIBUF 0x40
Sandeep Paulraj358934a2009-12-16 22:02:18 +0000111#define SPIDELAY 0x48
112#define SPIDEF 0x4c
113#define SPIFMT0 0x50
Sandeep Paulraj358934a2009-12-16 22:02:18 +0000114
Sandeep Paulraj358934a2009-12-16 22:02:18 +0000115/* We have 2 DMA channels per CS, one for RX and one for TX */
116struct davinci_spi_dma {
117 int dma_tx_channel;
118 int dma_rx_channel;
Sandeep Paulraj358934a2009-12-16 22:02:18 +0000119 enum dma_event_q eventq;
120
121 struct completion dma_tx_completion;
122 struct completion dma_rx_completion;
123};
124
125/* SPI Controller driver's private data. */
126struct davinci_spi {
127 struct spi_bitbang bitbang;
128 struct clk *clk;
129
130 u8 version;
131 resource_size_t pbase;
132 void __iomem *base;
133 size_t region_size;
Brian Niebuhre0d205e2010-09-02 16:52:06 +0530134 u32 irq;
135 struct completion done;
Sandeep Paulraj358934a2009-12-16 22:02:18 +0000136
137 const void *tx;
138 void *rx;
Brian Niebuhre91c6592010-10-01 10:29:29 +0530139#define SPI_TMP_BUFSZ (SMP_CACHE_BYTES + 1)
140 u8 rx_tmp_buf[SPI_TMP_BUFSZ];
Brian Niebuhre0d205e2010-09-02 16:52:06 +0530141 int rcount;
142 int wcount;
Brian Niebuhr96fd8812010-09-27 22:23:23 +0530143 struct davinci_spi_dma dma_channels;
Brian Niebuhr778e2612010-09-03 15:15:06 +0530144 struct davinci_spi_platform_data *pdata;
Sandeep Paulraj358934a2009-12-16 22:02:18 +0000145
146 void (*get_rx)(u32 rx_data, struct davinci_spi *);
147 u32 (*get_tx)(struct davinci_spi *);
148
Brian Niebuhrcda987e2010-08-19 16:16:28 +0530149 u8 bytes_per_word[SPI_MAX_CHIPSELECT];
Sandeep Paulraj358934a2009-12-16 22:02:18 +0000150};
151
Brian Niebuhr53a31b02010-08-16 15:05:51 +0530152static struct davinci_spi_config davinci_spi_default_cfg;
153
Sandeep Paulraj358934a2009-12-16 22:02:18 +0000154static void davinci_spi_rx_buf_u8(u32 data, struct davinci_spi *davinci_spi)
155{
Brian Niebuhr53d454a2010-08-19 17:04:25 +0530156 if (davinci_spi->rx) {
157 u8 *rx = davinci_spi->rx;
158 *rx++ = (u8)data;
159 davinci_spi->rx = rx;
160 }
Sandeep Paulraj358934a2009-12-16 22:02:18 +0000161}
162
163static void davinci_spi_rx_buf_u16(u32 data, struct davinci_spi *davinci_spi)
164{
Brian Niebuhr53d454a2010-08-19 17:04:25 +0530165 if (davinci_spi->rx) {
166 u16 *rx = davinci_spi->rx;
167 *rx++ = (u16)data;
168 davinci_spi->rx = rx;
169 }
Sandeep Paulraj358934a2009-12-16 22:02:18 +0000170}
171
172static u32 davinci_spi_tx_buf_u8(struct davinci_spi *davinci_spi)
173{
Brian Niebuhr53d454a2010-08-19 17:04:25 +0530174 u32 data = 0;
175 if (davinci_spi->tx) {
176 const u8 *tx = davinci_spi->tx;
177 data = *tx++;
178 davinci_spi->tx = tx;
179 }
Sandeep Paulraj358934a2009-12-16 22:02:18 +0000180 return data;
181}
182
183static u32 davinci_spi_tx_buf_u16(struct davinci_spi *davinci_spi)
184{
Brian Niebuhr53d454a2010-08-19 17:04:25 +0530185 u32 data = 0;
186 if (davinci_spi->tx) {
187 const u16 *tx = davinci_spi->tx;
188 data = *tx++;
189 davinci_spi->tx = tx;
190 }
Sandeep Paulraj358934a2009-12-16 22:02:18 +0000191 return data;
192}
193
194static inline void set_io_bits(void __iomem *addr, u32 bits)
195{
196 u32 v = ioread32(addr);
197
198 v |= bits;
199 iowrite32(v, addr);
200}
201
202static inline void clear_io_bits(void __iomem *addr, u32 bits)
203{
204 u32 v = ioread32(addr);
205
206 v &= ~bits;
207 iowrite32(v, addr);
208}
209
Sandeep Paulraj358934a2009-12-16 22:02:18 +0000210/*
211 * Interface to control the chip select signal
212 */
213static void davinci_spi_chipselect(struct spi_device *spi, int value)
214{
215 struct davinci_spi *davinci_spi;
216 struct davinci_spi_platform_data *pdata;
Brian Niebuhr7978b8c2010-08-13 10:11:03 +0530217 u8 chip_sel = spi->chip_select;
Brian Niebuhrcfbc5d12010-08-12 12:27:33 +0530218 u16 spidat1_cfg = CS_DEFAULT;
Brian Niebuhr23853972010-08-13 10:57:44 +0530219 bool gpio_chipsel = false;
Sandeep Paulraj358934a2009-12-16 22:02:18 +0000220
221 davinci_spi = spi_master_get_devdata(spi->master);
222 pdata = davinci_spi->pdata;
223
Brian Niebuhr23853972010-08-13 10:57:44 +0530224 if (pdata->chip_sel && chip_sel < pdata->num_chipselect &&
225 pdata->chip_sel[chip_sel] != SPI_INTERN_CS)
226 gpio_chipsel = true;
227
Sandeep Paulraj358934a2009-12-16 22:02:18 +0000228 /*
229 * Board specific chip select logic decides the polarity and cs
230 * line for the controller
231 */
Brian Niebuhr23853972010-08-13 10:57:44 +0530232 if (gpio_chipsel) {
233 if (value == BITBANG_CS_ACTIVE)
234 gpio_set_value(pdata->chip_sel[chip_sel], 0);
235 else
236 gpio_set_value(pdata->chip_sel[chip_sel], 1);
237 } else {
238 if (value == BITBANG_CS_ACTIVE) {
239 spidat1_cfg |= SPIDAT1_CSHOLD_MASK;
240 spidat1_cfg &= ~(0x1 << chip_sel);
241 }
Brian Niebuhr7978b8c2010-08-13 10:11:03 +0530242
Brian Niebuhr23853972010-08-13 10:57:44 +0530243 iowrite16(spidat1_cfg, davinci_spi->base + SPIDAT1 + 2);
244 }
Sandeep Paulraj358934a2009-12-16 22:02:18 +0000245}
246
247/**
Brian Niebuhr7fe00922010-08-13 13:27:23 +0530248 * davinci_spi_get_prescale - Calculates the correct prescale value
249 * @maxspeed_hz: the maximum rate the SPI clock can run at
250 *
251 * This function calculates the prescale value that generates a clock rate
252 * less than or equal to the specified maximum.
253 *
254 * Returns: calculated prescale - 1 for easy programming into SPI registers
255 * or negative error number if valid prescalar cannot be updated.
256 */
257static inline int davinci_spi_get_prescale(struct davinci_spi *davinci_spi,
258 u32 max_speed_hz)
259{
260 int ret;
261
262 ret = DIV_ROUND_UP(clk_get_rate(davinci_spi->clk), max_speed_hz);
263
264 if (ret < 3 || ret > 256)
265 return -EINVAL;
266
267 return ret - 1;
268}
269
270/**
Sandeep Paulraj358934a2009-12-16 22:02:18 +0000271 * davinci_spi_setup_transfer - This functions will determine transfer method
272 * @spi: spi device on which data transfer to be done
273 * @t: spi transfer in which transfer info is filled
274 *
275 * This function determines data transfer method (8/16/32 bit transfer).
276 * It will also set the SPI Clock Control register according to
277 * SPI slave device freq.
278 */
279static int davinci_spi_setup_transfer(struct spi_device *spi,
280 struct spi_transfer *t)
281{
282
283 struct davinci_spi *davinci_spi;
Brian Niebuhr25f33512010-08-19 12:15:22 +0530284 struct davinci_spi_config *spicfg;
Sandeep Paulraj358934a2009-12-16 22:02:18 +0000285 u8 bits_per_word = 0;
Brian Niebuhr25f33512010-08-19 12:15:22 +0530286 u32 hz = 0, spifmt = 0, prescale = 0;
Sandeep Paulraj358934a2009-12-16 22:02:18 +0000287
288 davinci_spi = spi_master_get_devdata(spi->master);
Brian Niebuhr25f33512010-08-19 12:15:22 +0530289 spicfg = (struct davinci_spi_config *)spi->controller_data;
290 if (!spicfg)
291 spicfg = &davinci_spi_default_cfg;
Sandeep Paulraj358934a2009-12-16 22:02:18 +0000292
293 if (t) {
294 bits_per_word = t->bits_per_word;
295 hz = t->speed_hz;
296 }
297
298 /* if bits_per_word is not set then set it default */
299 if (!bits_per_word)
300 bits_per_word = spi->bits_per_word;
301
302 /*
303 * Assign function pointer to appropriate transfer method
304 * 8bit, 16bit or 32bit transfer
305 */
306 if (bits_per_word <= 8 && bits_per_word >= 2) {
307 davinci_spi->get_rx = davinci_spi_rx_buf_u8;
308 davinci_spi->get_tx = davinci_spi_tx_buf_u8;
Brian Niebuhrcda987e2010-08-19 16:16:28 +0530309 davinci_spi->bytes_per_word[spi->chip_select] = 1;
Sandeep Paulraj358934a2009-12-16 22:02:18 +0000310 } else if (bits_per_word <= 16 && bits_per_word >= 2) {
311 davinci_spi->get_rx = davinci_spi_rx_buf_u16;
312 davinci_spi->get_tx = davinci_spi_tx_buf_u16;
Brian Niebuhrcda987e2010-08-19 16:16:28 +0530313 davinci_spi->bytes_per_word[spi->chip_select] = 2;
Sandeep Paulraj358934a2009-12-16 22:02:18 +0000314 } else
315 return -EINVAL;
316
317 if (!hz)
318 hz = spi->max_speed_hz;
319
Brian Niebuhr25f33512010-08-19 12:15:22 +0530320 /* Set up SPIFMTn register, unique to this chipselect. */
321
Brian Niebuhr7fe00922010-08-13 13:27:23 +0530322 prescale = davinci_spi_get_prescale(davinci_spi, hz);
323 if (prescale < 0)
324 return prescale;
325
Brian Niebuhr25f33512010-08-19 12:15:22 +0530326 spifmt = (prescale << SPIFMT_PRESCALE_SHIFT) | (bits_per_word & 0x1f);
Sandeep Paulraj358934a2009-12-16 22:02:18 +0000327
Brian Niebuhr25f33512010-08-19 12:15:22 +0530328 if (spi->mode & SPI_LSB_FIRST)
329 spifmt |= SPIFMT_SHIFTDIR_MASK;
330
331 if (spi->mode & SPI_CPOL)
332 spifmt |= SPIFMT_POLARITY_MASK;
333
334 if (!(spi->mode & SPI_CPHA))
335 spifmt |= SPIFMT_PHASE_MASK;
336
337 /*
338 * Version 1 hardware supports two basic SPI modes:
339 * - Standard SPI mode uses 4 pins, with chipselect
340 * - 3 pin SPI is a 4 pin variant without CS (SPI_NO_CS)
341 * (distinct from SPI_3WIRE, with just one data wire;
342 * or similar variants without MOSI or without MISO)
343 *
344 * Version 2 hardware supports an optional handshaking signal,
345 * so it can support two more modes:
346 * - 5 pin SPI variant is standard SPI plus SPI_READY
347 * - 4 pin with enable is (SPI_READY | SPI_NO_CS)
348 */
349
350 if (davinci_spi->version == SPI_VERSION_2) {
351
Brian Niebuhr7abbf232010-08-19 15:07:38 +0530352 u32 delay = 0;
353
Brian Niebuhr25f33512010-08-19 12:15:22 +0530354 spifmt |= ((spicfg->wdelay << SPIFMT_WDELAY_SHIFT)
355 & SPIFMT_WDELAY_MASK);
356
357 if (spicfg->odd_parity)
358 spifmt |= SPIFMT_ODD_PARITY_MASK;
359
360 if (spicfg->parity_enable)
361 spifmt |= SPIFMT_PARITYENA_MASK;
362
Brian Niebuhr7abbf232010-08-19 15:07:38 +0530363 if (spicfg->timer_disable) {
Brian Niebuhr25f33512010-08-19 12:15:22 +0530364 spifmt |= SPIFMT_DISTIMER_MASK;
Brian Niebuhr7abbf232010-08-19 15:07:38 +0530365 } else {
366 delay |= (spicfg->c2tdelay << SPIDELAY_C2TDELAY_SHIFT)
367 & SPIDELAY_C2TDELAY_MASK;
368 delay |= (spicfg->t2cdelay << SPIDELAY_T2CDELAY_SHIFT)
369 & SPIDELAY_T2CDELAY_MASK;
370 }
Brian Niebuhr25f33512010-08-19 12:15:22 +0530371
Brian Niebuhr7abbf232010-08-19 15:07:38 +0530372 if (spi->mode & SPI_READY) {
Brian Niebuhr25f33512010-08-19 12:15:22 +0530373 spifmt |= SPIFMT_WAITENA_MASK;
Brian Niebuhr7abbf232010-08-19 15:07:38 +0530374 delay |= (spicfg->t2edelay << SPIDELAY_T2EDELAY_SHIFT)
375 & SPIDELAY_T2EDELAY_MASK;
376 delay |= (spicfg->c2edelay << SPIDELAY_C2EDELAY_SHIFT)
377 & SPIDELAY_C2EDELAY_MASK;
378 }
379
380 iowrite32(delay, davinci_spi->base + SPIDELAY);
Brian Niebuhr25f33512010-08-19 12:15:22 +0530381 }
382
383 iowrite32(spifmt, davinci_spi->base + SPIFMT0);
Sandeep Paulraj358934a2009-12-16 22:02:18 +0000384
385 return 0;
386}
387
388static void davinci_spi_dma_rx_callback(unsigned lch, u16 ch_status, void *data)
389{
Sekhar Nori903ca252010-10-01 14:51:40 +0530390 struct davinci_spi_dma *davinci_spi_dma = data;
Sandeep Paulraj358934a2009-12-16 22:02:18 +0000391
392 if (ch_status == DMA_COMPLETE)
393 edma_stop(davinci_spi_dma->dma_rx_channel);
394 else
395 edma_clean_channel(davinci_spi_dma->dma_rx_channel);
396
397 complete(&davinci_spi_dma->dma_rx_completion);
Sandeep Paulraj358934a2009-12-16 22:02:18 +0000398}
399
400static void davinci_spi_dma_tx_callback(unsigned lch, u16 ch_status, void *data)
401{
Sekhar Nori903ca252010-10-01 14:51:40 +0530402 struct davinci_spi_dma *davinci_spi_dma = data;
Sandeep Paulraj358934a2009-12-16 22:02:18 +0000403
404 if (ch_status == DMA_COMPLETE)
405 edma_stop(davinci_spi_dma->dma_tx_channel);
406 else
407 edma_clean_channel(davinci_spi_dma->dma_tx_channel);
408
409 complete(&davinci_spi_dma->dma_tx_completion);
Sandeep Paulraj358934a2009-12-16 22:02:18 +0000410}
411
Sandeep Paulraj358934a2009-12-16 22:02:18 +0000412/**
413 * davinci_spi_setup - This functions will set default transfer method
414 * @spi: spi device on which data transfer to be done
415 *
416 * This functions sets the default transfer method.
417 */
Sandeep Paulraj358934a2009-12-16 22:02:18 +0000418static int davinci_spi_setup(struct spi_device *spi)
419{
Brian Niebuhrb23a5d42010-09-24 18:53:32 +0530420 int retval = 0;
Sandeep Paulraj358934a2009-12-16 22:02:18 +0000421 struct davinci_spi *davinci_spi;
Brian Niebuhrbe884712010-09-03 12:15:28 +0530422 struct davinci_spi_platform_data *pdata;
Sandeep Paulraj358934a2009-12-16 22:02:18 +0000423
424 davinci_spi = spi_master_get_devdata(spi->master);
Brian Niebuhrbe884712010-09-03 12:15:28 +0530425 pdata = davinci_spi->pdata;
Sandeep Paulraj358934a2009-12-16 22:02:18 +0000426
427 /* if bits per word length is zero then set it default 8 */
428 if (!spi->bits_per_word)
429 spi->bits_per_word = 8;
430
Brian Niebuhrbe884712010-09-03 12:15:28 +0530431 if (!(spi->mode & SPI_NO_CS)) {
432 if ((pdata->chip_sel == NULL) ||
433 (pdata->chip_sel[spi->chip_select] == SPI_INTERN_CS))
434 set_io_bits(davinci_spi->base + SPIPC0,
435 1 << spi->chip_select);
436
437 }
438
439 if (spi->mode & SPI_READY)
440 set_io_bits(davinci_spi->base + SPIPC0, SPIPC0_SPIENA_MASK);
441
442 if (spi->mode & SPI_LOOP)
443 set_io_bits(davinci_spi->base + SPIGCR1,
444 SPIGCR1_LOOPBACK_MASK);
445 else
446 clear_io_bits(davinci_spi->base + SPIGCR1,
447 SPIGCR1_LOOPBACK_MASK);
448
Sandeep Paulraj358934a2009-12-16 22:02:18 +0000449 return retval;
450}
451
Sandeep Paulraj358934a2009-12-16 22:02:18 +0000452static int davinci_spi_check_error(struct davinci_spi *davinci_spi,
453 int int_status)
454{
455 struct device *sdev = davinci_spi->bitbang.master->dev.parent;
456
457 if (int_status & SPIFLG_TIMEOUT_MASK) {
458 dev_dbg(sdev, "SPI Time-out Error\n");
459 return -ETIMEDOUT;
460 }
461 if (int_status & SPIFLG_DESYNC_MASK) {
462 dev_dbg(sdev, "SPI Desynchronization Error\n");
463 return -EIO;
464 }
465 if (int_status & SPIFLG_BITERR_MASK) {
466 dev_dbg(sdev, "SPI Bit error\n");
467 return -EIO;
468 }
469
470 if (davinci_spi->version == SPI_VERSION_2) {
471 if (int_status & SPIFLG_DLEN_ERR_MASK) {
472 dev_dbg(sdev, "SPI Data Length Error\n");
473 return -EIO;
474 }
475 if (int_status & SPIFLG_PARERR_MASK) {
476 dev_dbg(sdev, "SPI Parity Error\n");
477 return -EIO;
478 }
479 if (int_status & SPIFLG_OVRRUN_MASK) {
480 dev_dbg(sdev, "SPI Data Overrun error\n");
481 return -EIO;
482 }
Sandeep Paulraj358934a2009-12-16 22:02:18 +0000483 if (int_status & SPIFLG_BUF_INIT_ACTIVE_MASK) {
484 dev_dbg(sdev, "SPI Buffer Init Active\n");
485 return -EBUSY;
486 }
487 }
488
489 return 0;
490}
491
492/**
Brian Niebuhre0d205e2010-09-02 16:52:06 +0530493 * davinci_spi_process_events - check for and handle any SPI controller events
494 * @davinci_spi: the controller data
495 *
496 * This function will check the SPIFLG register and handle any events that are
497 * detected there
498 */
499static int davinci_spi_process_events(struct davinci_spi *davinci_spi)
500{
501 u32 buf, status, errors = 0, data1_reg_val;
502
503 buf = ioread32(davinci_spi->base + SPIBUF);
504
505 if (davinci_spi->rcount > 0 && !(buf & SPIBUF_RXEMPTY_MASK)) {
506 davinci_spi->get_rx(buf & 0xFFFF, davinci_spi);
507 davinci_spi->rcount--;
508 }
509
510 status = ioread32(davinci_spi->base + SPIFLG);
511
512 if (unlikely(status & SPIFLG_ERROR_MASK)) {
513 errors = status & SPIFLG_ERROR_MASK;
514 goto out;
515 }
516
517 if (davinci_spi->wcount > 0 && !(buf & SPIBUF_TXFULL_MASK)) {
518 data1_reg_val = ioread32(davinci_spi->base + SPIDAT1);
519 davinci_spi->wcount--;
520 data1_reg_val &= ~0xFFFF;
521 data1_reg_val |= 0xFFFF & davinci_spi->get_tx(davinci_spi);
522 iowrite32(data1_reg_val, davinci_spi->base + SPIDAT1);
523 }
524
525out:
526 return errors;
527}
528
529/**
Sandeep Paulraj358934a2009-12-16 22:02:18 +0000530 * davinci_spi_bufs - functions which will handle transfer data
531 * @spi: spi device on which data transfer to be done
532 * @t: spi transfer in which transfer info is filled
533 *
534 * This function will put data to be transferred into data register
535 * of SPI controller and then wait until the completion will be marked
536 * by the IRQ Handler.
537 */
538static int davinci_spi_bufs_pio(struct spi_device *spi, struct spi_transfer *t)
539{
540 struct davinci_spi *davinci_spi;
Brian Niebuhr839c9962010-08-23 16:39:19 +0530541 int ret;
Sandeep Paulraj358934a2009-12-16 22:02:18 +0000542 u32 tx_data, data1_reg_val;
Brian Niebuhr839c9962010-08-23 16:39:19 +0530543 u32 errors = 0;
Brian Niebuhre0d205e2010-09-02 16:52:06 +0530544 struct davinci_spi_config *spicfg;
Sandeep Paulraj358934a2009-12-16 22:02:18 +0000545 struct davinci_spi_platform_data *pdata;
546
547 davinci_spi = spi_master_get_devdata(spi->master);
548 pdata = davinci_spi->pdata;
Brian Niebuhre0d205e2010-09-02 16:52:06 +0530549 spicfg = (struct davinci_spi_config *)spi->controller_data;
550 if (!spicfg)
551 spicfg = &davinci_spi_default_cfg;
Sandeep Paulraj358934a2009-12-16 22:02:18 +0000552
553 davinci_spi->tx = t->tx_buf;
554 davinci_spi->rx = t->rx_buf;
Brian Niebuhre0d205e2010-09-02 16:52:06 +0530555 davinci_spi->wcount = t->len /
556 davinci_spi->bytes_per_word[spi->chip_select];
557 davinci_spi->rcount = davinci_spi->wcount;
Brian Niebuhr7978b8c2010-08-13 10:11:03 +0530558
Brian Niebuhr839c9962010-08-23 16:39:19 +0530559 data1_reg_val = ioread32(davinci_spi->base + SPIDAT1);
560
Sandeep Paulraj358934a2009-12-16 22:02:18 +0000561 /* Enable SPI */
562 set_io_bits(davinci_spi->base + SPIGCR1, SPIGCR1_SPIENA_MASK);
563
Brian Niebuhre0d205e2010-09-02 16:52:06 +0530564 if (spicfg->io_type == SPI_IO_TYPE_INTR) {
565 set_io_bits(davinci_spi->base + SPIINT, SPIINT_MASKINT);
566 INIT_COMPLETION(davinci_spi->done);
567 }
Brian Niebuhrcf90fe72010-08-20 17:02:49 +0530568
Brian Niebuhr839c9962010-08-23 16:39:19 +0530569 /* start the transfer */
Brian Niebuhre0d205e2010-09-02 16:52:06 +0530570 davinci_spi->wcount--;
Brian Niebuhr839c9962010-08-23 16:39:19 +0530571 tx_data = davinci_spi->get_tx(davinci_spi);
572 data1_reg_val &= 0xFFFF0000;
573 data1_reg_val |= tx_data & 0xFFFF;
574 iowrite32(data1_reg_val, davinci_spi->base + SPIDAT1);
Sandeep Paulraj358934a2009-12-16 22:02:18 +0000575
Brian Niebuhre0d205e2010-09-02 16:52:06 +0530576 /* Wait for the transfer to complete */
577 if (spicfg->io_type == SPI_IO_TYPE_INTR) {
578 wait_for_completion_interruptible(&(davinci_spi->done));
579 } else {
580 while (davinci_spi->rcount > 0 || davinci_spi->wcount > 0) {
581 errors = davinci_spi_process_events(davinci_spi);
582 if (errors)
583 break;
584 cpu_relax();
Sandeep Paulraj358934a2009-12-16 22:02:18 +0000585 }
586 }
587
Brian Niebuhre0d205e2010-09-02 16:52:06 +0530588 clear_io_bits(davinci_spi->base + SPIINT, SPIINT_MASKALL);
589
Sandeep Paulraj358934a2009-12-16 22:02:18 +0000590 /*
591 * Check for bit error, desync error,parity error,timeout error and
592 * receive overflow errors
593 */
Brian Niebuhr839c9962010-08-23 16:39:19 +0530594 if (errors) {
595 ret = davinci_spi_check_error(davinci_spi, errors);
596 WARN(!ret, "%s: error reported but no error found!\n",
597 dev_name(&spi->dev));
Sandeep Paulraj358934a2009-12-16 22:02:18 +0000598 return ret;
Brian Niebuhr839c9962010-08-23 16:39:19 +0530599 }
Sandeep Paulraj358934a2009-12-16 22:02:18 +0000600
Sandeep Paulraj358934a2009-12-16 22:02:18 +0000601 return t->len;
602}
603
Brian Niebuhre0d205e2010-09-02 16:52:06 +0530604/**
605 * davinci_spi_irq - Interrupt handler for SPI Master Controller
606 * @irq: IRQ number for this SPI Master
607 * @context_data: structure for SPI Master controller davinci_spi
608 *
609 * ISR will determine that interrupt arrives either for READ or WRITE command.
610 * According to command it will do the appropriate action. It will check
611 * transfer length and if it is not zero then dispatch transfer command again.
612 * If transfer length is zero then it will indicate the COMPLETION so that
613 * davinci_spi_bufs function can go ahead.
614 */
615static irqreturn_t davinci_spi_irq(s32 irq, void *context_data)
616{
617 struct davinci_spi *davinci_spi = context_data;
618 int status;
619
620 status = davinci_spi_process_events(davinci_spi);
621 if (unlikely(status != 0))
622 clear_io_bits(davinci_spi->base + SPIINT, SPIINT_MASKINT);
623
624 if ((!davinci_spi->rcount && !davinci_spi->wcount) || status)
625 complete(&davinci_spi->done);
626
627 return IRQ_HANDLED;
628}
629
Sandeep Paulraj358934a2009-12-16 22:02:18 +0000630static int davinci_spi_bufs_dma(struct spi_device *spi, struct spi_transfer *t)
631{
632 struct davinci_spi *davinci_spi;
633 int int_status = 0;
Brian Niebuhrd3f71412010-09-29 12:31:54 +0530634 int count;
Brian Niebuhre91c6592010-10-01 10:29:29 +0530635 unsigned rx_buf_count;
Sandeep Paulraj358934a2009-12-16 22:02:18 +0000636 struct davinci_spi_dma *davinci_spi_dma;
Brian Niebuhrb7ab24a2010-08-19 16:42:42 +0530637 int data_type, ret;
Sandeep Paulraj358934a2009-12-16 22:02:18 +0000638 unsigned long tx_reg, rx_reg;
Brian Niebuhrc29e3c62010-09-28 13:59:26 +0530639 struct davinci_spi_platform_data *pdata;
Brian Niebuhre91c6592010-10-01 10:29:29 +0530640 void *rx_buf;
Sandeep Paulraj358934a2009-12-16 22:02:18 +0000641 struct device *sdev;
Brian Niebuhr49fc3f42010-10-01 11:22:23 +0530642 struct edmacc_param param;
Sandeep Paulraj358934a2009-12-16 22:02:18 +0000643
644 davinci_spi = spi_master_get_devdata(spi->master);
Brian Niebuhrc29e3c62010-09-28 13:59:26 +0530645 pdata = davinci_spi->pdata;
Sandeep Paulraj358934a2009-12-16 22:02:18 +0000646 sdev = davinci_spi->bitbang.master->dev.parent;
647
Brian Niebuhr96fd8812010-09-27 22:23:23 +0530648 davinci_spi_dma = &davinci_spi->dma_channels;
Sandeep Paulraj358934a2009-12-16 22:02:18 +0000649
650 tx_reg = (unsigned long)davinci_spi->pbase + SPIDAT1;
651 rx_reg = (unsigned long)davinci_spi->pbase + SPIBUF;
652
653 davinci_spi->tx = t->tx_buf;
654 davinci_spi->rx = t->rx_buf;
655
656 /* convert len to words based on bits_per_word */
Brian Niebuhrb7ab24a2010-08-19 16:42:42 +0530657 data_type = davinci_spi->bytes_per_word[spi->chip_select];
Sandeep Paulraj358934a2009-12-16 22:02:18 +0000658
Sandeep Paulraj358934a2009-12-16 22:02:18 +0000659 init_completion(&davinci_spi_dma->dma_rx_completion);
660 init_completion(&davinci_spi_dma->dma_tx_completion);
661
Brian Niebuhrf2bf4e82010-08-20 15:28:23 +0530662 count = t->len / data_type; /* the number of elements */
Sandeep Paulraj358934a2009-12-16 22:02:18 +0000663
664 /* disable all interrupts for dma transfers */
665 clear_io_bits(davinci_spi->base + SPIINT, SPIINT_MASKALL);
Sandeep Paulraj358934a2009-12-16 22:02:18 +0000666 /* Enable SPI */
667 set_io_bits(davinci_spi->base + SPIGCR1, SPIGCR1_SPIENA_MASK);
668
Brian Niebuhrd3f71412010-09-29 12:31:54 +0530669 /*
670 * Transmit DMA setup
671 *
672 * If there is transmit data, map the transmit buffer, set it as the
673 * source of data and set the source B index to data size.
674 * If there is no transmit data, set the transmit register as the
675 * source of data, and set the source B index to zero.
676 *
677 * The destination is always the transmit register itself. And the
678 * destination never increments.
679 */
680
Sandeep Paulraj358934a2009-12-16 22:02:18 +0000681 if (t->tx_buf) {
682 t->tx_dma = dma_map_single(&spi->dev, (void *)t->tx_buf, count,
683 DMA_TO_DEVICE);
684 if (dma_mapping_error(&spi->dev, t->tx_dma)) {
685 dev_dbg(sdev, "Unable to DMA map a %d bytes"
686 " TX buffer\n", count);
687 return -ENOMEM;
688 }
Sandeep Paulraj358934a2009-12-16 22:02:18 +0000689 }
690
Brian Niebuhr49fc3f42010-10-01 11:22:23 +0530691 param.opt = TCINTEN | EDMA_TCC(davinci_spi_dma->dma_tx_channel);
692 param.src = t->tx_buf ? t->tx_dma : tx_reg;
693 param.a_b_cnt = count << 16 | data_type;
694 param.dst = tx_reg;
695 param.src_dst_bidx = t->tx_buf ? data_type : 0;
696 param.link_bcntrld = 0xffff;
697 param.src_dst_cidx = 0;
698 param.ccnt = 1;
699 edma_write_slot(davinci_spi_dma->dma_tx_channel, &param);
Sandeep Paulraj358934a2009-12-16 22:02:18 +0000700
Brian Niebuhre91c6592010-10-01 10:29:29 +0530701 /*
702 * Receive DMA setup
703 *
704 * If there is receive buffer, use it to receive data. If there
705 * is none provided, use a temporary receive buffer. Set the
706 * destination B index to 0 so effectively only one byte is used
707 * in the temporary buffer (address does not increment).
708 *
709 * The source of receive data is the receive data register. The
710 * source address never increments.
711 */
712
Sandeep Paulraj358934a2009-12-16 22:02:18 +0000713 if (t->rx_buf) {
Brian Niebuhre91c6592010-10-01 10:29:29 +0530714 rx_buf = t->rx_buf;
715 rx_buf_count = count;
716 } else {
717 rx_buf = davinci_spi->rx_tmp_buf;
718 rx_buf_count = sizeof(davinci_spi->rx_tmp_buf);
Sandeep Paulraj358934a2009-12-16 22:02:18 +0000719 }
720
Brian Niebuhre91c6592010-10-01 10:29:29 +0530721 t->rx_dma = dma_map_single(&spi->dev, rx_buf, rx_buf_count,
722 DMA_FROM_DEVICE);
723 if (dma_mapping_error(&spi->dev, t->rx_dma)) {
724 dev_dbg(sdev, "Couldn't DMA map a %d bytes RX buffer\n",
725 rx_buf_count);
726 if (t->tx_buf)
727 dma_unmap_single(NULL, t->tx_dma, count, DMA_TO_DEVICE);
728 return -ENOMEM;
729 }
730
Brian Niebuhr49fc3f42010-10-01 11:22:23 +0530731 param.opt = TCINTEN | EDMA_TCC(davinci_spi_dma->dma_rx_channel);
732 param.src = rx_reg;
733 param.a_b_cnt = count << 16 | data_type;
734 param.dst = t->rx_dma;
735 param.src_dst_bidx = (t->rx_buf ? data_type : 0) << 16;
736 param.link_bcntrld = 0xffff;
737 param.src_dst_cidx = 0;
738 param.ccnt = 1;
739 edma_write_slot(davinci_spi_dma->dma_rx_channel, &param);
Brian Niebuhre91c6592010-10-01 10:29:29 +0530740
Brian Niebuhrc29e3c62010-09-28 13:59:26 +0530741 if (pdata->cshold_bug) {
742 u16 spidat1 = ioread16(davinci_spi->base + SPIDAT1 + 2);
743 iowrite16(spidat1, davinci_spi->base + SPIDAT1 + 2);
744 }
Sandeep Paulraj358934a2009-12-16 22:02:18 +0000745
Brian Niebuhre91c6592010-10-01 10:29:29 +0530746 edma_start(davinci_spi_dma->dma_rx_channel);
Brian Niebuhrc29e3c62010-09-28 13:59:26 +0530747 edma_start(davinci_spi_dma->dma_tx_channel);
Brian Niebuhra4f44972010-10-01 14:00:48 +0530748 set_io_bits(davinci_spi->base + SPIINT, SPIINT_DMA_REQ_EN);
Sandeep Paulraj358934a2009-12-16 22:02:18 +0000749
Brian Niebuhrc29e3c62010-09-28 13:59:26 +0530750 wait_for_completion_interruptible(&davinci_spi_dma->dma_tx_completion);
Brian Niebuhre91c6592010-10-01 10:29:29 +0530751 wait_for_completion_interruptible(&davinci_spi_dma->dma_rx_completion);
Sandeep Paulraj358934a2009-12-16 22:02:18 +0000752
Brian Niebuhrd3f71412010-09-29 12:31:54 +0530753 if (t->tx_buf)
754 dma_unmap_single(NULL, t->tx_dma, count, DMA_TO_DEVICE);
Sandeep Paulraj358934a2009-12-16 22:02:18 +0000755
Brian Niebuhre91c6592010-10-01 10:29:29 +0530756 dma_unmap_single(NULL, t->rx_dma, rx_buf_count, DMA_FROM_DEVICE);
Sandeep Paulraj358934a2009-12-16 22:02:18 +0000757
Brian Niebuhra4f44972010-10-01 14:00:48 +0530758 clear_io_bits(davinci_spi->base + SPIINT, SPIINT_DMA_REQ_EN);
759
Sandeep Paulraj358934a2009-12-16 22:02:18 +0000760 /*
761 * Check for bit error, desync error,parity error,timeout error and
762 * receive overflow errors
763 */
764 int_status = ioread32(davinci_spi->base + SPIFLG);
765
766 ret = davinci_spi_check_error(davinci_spi, int_status);
767 if (ret != 0)
768 return ret;
769
Sandeep Paulraj358934a2009-12-16 22:02:18 +0000770 return t->len;
771}
772
Sekhar Nori903ca252010-10-01 14:51:40 +0530773static int davinci_spi_request_dma(struct davinci_spi_dma *davinci_spi_dma)
774{
775 int r;
776
777 r = edma_alloc_channel(davinci_spi_dma->dma_rx_channel,
778 davinci_spi_dma_rx_callback, davinci_spi_dma,
779 davinci_spi_dma->eventq);
780 if (r < 0) {
781 pr_err("Unable to request DMA channel for SPI RX\n");
782 return -EAGAIN;
783 }
784
785 r = edma_alloc_channel(davinci_spi_dma->dma_tx_channel,
786 davinci_spi_dma_tx_callback, davinci_spi_dma,
787 davinci_spi_dma->eventq);
788 if (r < 0) {
789 edma_free_channel(davinci_spi_dma->dma_rx_channel);
790 pr_err("Unable to request DMA channel for SPI TX\n");
791 return -EAGAIN;
792 }
793
794 return 0;
795}
796
Sandeep Paulraj358934a2009-12-16 22:02:18 +0000797/**
Sandeep Paulraj358934a2009-12-16 22:02:18 +0000798 * davinci_spi_probe - probe function for SPI Master Controller
799 * @pdev: platform_device structure which contains plateform specific data
800 */
801static int davinci_spi_probe(struct platform_device *pdev)
802{
803 struct spi_master *master;
804 struct davinci_spi *davinci_spi;
805 struct davinci_spi_platform_data *pdata;
806 struct resource *r, *mem;
807 resource_size_t dma_rx_chan = SPI_NO_RESOURCE;
808 resource_size_t dma_tx_chan = SPI_NO_RESOURCE;
809 resource_size_t dma_eventq = SPI_NO_RESOURCE;
810 int i = 0, ret = 0;
Brian Niebuhrf34bd4c2010-09-03 11:56:35 +0530811 u32 spipc0;
Sandeep Paulraj358934a2009-12-16 22:02:18 +0000812
813 pdata = pdev->dev.platform_data;
814 if (pdata == NULL) {
815 ret = -ENODEV;
816 goto err;
817 }
818
819 master = spi_alloc_master(&pdev->dev, sizeof(struct davinci_spi));
820 if (master == NULL) {
821 ret = -ENOMEM;
822 goto err;
823 }
824
825 dev_set_drvdata(&pdev->dev, master);
826
827 davinci_spi = spi_master_get_devdata(master);
828 if (davinci_spi == NULL) {
829 ret = -ENOENT;
830 goto free_master;
831 }
832
833 r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
834 if (r == NULL) {
835 ret = -ENOENT;
836 goto free_master;
837 }
838
839 davinci_spi->pbase = r->start;
840 davinci_spi->region_size = resource_size(r);
841 davinci_spi->pdata = pdata;
842
843 mem = request_mem_region(r->start, davinci_spi->region_size,
844 pdev->name);
845 if (mem == NULL) {
846 ret = -EBUSY;
847 goto free_master;
848 }
849
Sekhar Nori50356dd2010-10-08 15:27:26 +0530850 davinci_spi->base = ioremap(r->start, davinci_spi->region_size);
Sandeep Paulraj358934a2009-12-16 22:02:18 +0000851 if (davinci_spi->base == NULL) {
852 ret = -ENOMEM;
853 goto release_region;
854 }
855
Brian Niebuhre0d205e2010-09-02 16:52:06 +0530856 davinci_spi->irq = platform_get_irq(pdev, 0);
857 if (davinci_spi->irq <= 0) {
858 ret = -EINVAL;
859 goto unmap_io;
860 }
861
862 ret = request_irq(davinci_spi->irq, davinci_spi_irq, 0,
863 dev_name(&pdev->dev), davinci_spi);
864 if (ret)
865 goto unmap_io;
866
Sandeep Paulraj358934a2009-12-16 22:02:18 +0000867 davinci_spi->bitbang.master = spi_master_get(master);
868 if (davinci_spi->bitbang.master == NULL) {
869 ret = -ENODEV;
Brian Niebuhrd3f71412010-09-29 12:31:54 +0530870 goto irq_free;
Sandeep Paulraj358934a2009-12-16 22:02:18 +0000871 }
872
873 davinci_spi->clk = clk_get(&pdev->dev, NULL);
874 if (IS_ERR(davinci_spi->clk)) {
875 ret = -ENODEV;
876 goto put_master;
877 }
878 clk_enable(davinci_spi->clk);
879
Sandeep Paulraj358934a2009-12-16 22:02:18 +0000880 master->bus_num = pdev->id;
881 master->num_chipselect = pdata->num_chipselect;
882 master->setup = davinci_spi_setup;
Sandeep Paulraj358934a2009-12-16 22:02:18 +0000883
884 davinci_spi->bitbang.chipselect = davinci_spi_chipselect;
885 davinci_spi->bitbang.setup_transfer = davinci_spi_setup_transfer;
886
887 davinci_spi->version = pdata->version;
Sandeep Paulraj358934a2009-12-16 22:02:18 +0000888
889 davinci_spi->bitbang.flags = SPI_NO_CS | SPI_LSB_FIRST | SPI_LOOP;
890 if (davinci_spi->version == SPI_VERSION_2)
891 davinci_spi->bitbang.flags |= SPI_READY;
892
Sekhar Nori903ca252010-10-01 14:51:40 +0530893 r = platform_get_resource(pdev, IORESOURCE_DMA, 0);
894 if (r)
895 dma_rx_chan = r->start;
896 r = platform_get_resource(pdev, IORESOURCE_DMA, 1);
897 if (r)
898 dma_tx_chan = r->start;
899 r = platform_get_resource(pdev, IORESOURCE_DMA, 2);
900 if (r)
901 dma_eventq = r->start;
Sandeep Paulraj358934a2009-12-16 22:02:18 +0000902
Sekhar Nori903ca252010-10-01 14:51:40 +0530903 davinci_spi->bitbang.txrx_bufs = davinci_spi_bufs_pio;
904 if (dma_rx_chan != SPI_NO_RESOURCE &&
905 dma_tx_chan != SPI_NO_RESOURCE &&
906 dma_eventq != SPI_NO_RESOURCE) {
907 davinci_spi->dma_channels.dma_rx_channel = dma_rx_chan;
908 davinci_spi->dma_channels.dma_tx_channel = dma_tx_chan;
Brian Niebuhr96fd8812010-09-27 22:23:23 +0530909 davinci_spi->dma_channels.eventq = dma_eventq;
910
Sekhar Nori903ca252010-10-01 14:51:40 +0530911 ret = davinci_spi_request_dma(&davinci_spi->dma_channels);
912 if (ret)
913 goto free_clk;
914
915 davinci_spi->bitbang.txrx_bufs = davinci_spi_bufs_dma;
Sandeep Paulraj358934a2009-12-16 22:02:18 +0000916 dev_info(&pdev->dev, "DaVinci SPI driver in EDMA mode\n"
917 "Using RX channel = %d , TX channel = %d and "
918 "event queue = %d", dma_rx_chan, dma_tx_chan,
919 dma_eventq);
920 }
921
922 davinci_spi->get_rx = davinci_spi_rx_buf_u8;
923 davinci_spi->get_tx = davinci_spi_tx_buf_u8;
924
Brian Niebuhre0d205e2010-09-02 16:52:06 +0530925 init_completion(&davinci_spi->done);
926
Sandeep Paulraj358934a2009-12-16 22:02:18 +0000927 /* Reset In/OUT SPI module */
928 iowrite32(0, davinci_spi->base + SPIGCR0);
929 udelay(100);
930 iowrite32(1, davinci_spi->base + SPIGCR0);
931
Brian Niebuhrbe884712010-09-03 12:15:28 +0530932 /* Set up SPIPC0. CS and ENA init is done in davinci_spi_setup */
Brian Niebuhrf34bd4c2010-09-03 11:56:35 +0530933 spipc0 = SPIPC0_DIFUN_MASK | SPIPC0_DOFUN_MASK | SPIPC0_CLKFUN_MASK;
934 iowrite32(spipc0, davinci_spi->base + SPIPC0);
935
Brian Niebuhr23853972010-08-13 10:57:44 +0530936 /* initialize chip selects */
937 if (pdata->chip_sel) {
938 for (i = 0; i < pdata->num_chipselect; i++) {
939 if (pdata->chip_sel[i] != SPI_INTERN_CS)
940 gpio_direction_output(pdata->chip_sel[i], 1);
941 }
942 }
943
Sandeep Paulraj358934a2009-12-16 22:02:18 +0000944 /* Clock internal */
945 if (davinci_spi->pdata->clk_internal)
946 set_io_bits(davinci_spi->base + SPIGCR1,
947 SPIGCR1_CLKMOD_MASK);
948 else
949 clear_io_bits(davinci_spi->base + SPIGCR1,
950 SPIGCR1_CLKMOD_MASK);
951
Brian Niebuhre0d205e2010-09-02 16:52:06 +0530952 if (pdata->intr_line)
953 iowrite32(SPI_INTLVL_1, davinci_spi->base + SPILVL);
954 else
955 iowrite32(SPI_INTLVL_0, davinci_spi->base + SPILVL);
956
Brian Niebuhr843a7132010-08-12 12:49:05 +0530957 iowrite32(CS_DEFAULT, davinci_spi->base + SPIDEF);
958
Sandeep Paulraj358934a2009-12-16 22:02:18 +0000959 /* master mode default */
960 set_io_bits(davinci_spi->base + SPIGCR1, SPIGCR1_MASTER_MASK);
961
Sandeep Paulraj358934a2009-12-16 22:02:18 +0000962 ret = spi_bitbang_start(&davinci_spi->bitbang);
963 if (ret)
Sekhar Nori903ca252010-10-01 14:51:40 +0530964 goto free_dma;
Sandeep Paulraj358934a2009-12-16 22:02:18 +0000965
Brian Niebuhr3b740b12010-09-03 14:50:07 +0530966 dev_info(&pdev->dev, "Controller at 0x%p\n", davinci_spi->base);
Sandeep Paulraj358934a2009-12-16 22:02:18 +0000967
Sandeep Paulraj358934a2009-12-16 22:02:18 +0000968 return ret;
969
Sekhar Nori903ca252010-10-01 14:51:40 +0530970free_dma:
971 edma_free_channel(davinci_spi->dma_channels.dma_tx_channel);
972 edma_free_channel(davinci_spi->dma_channels.dma_rx_channel);
Sandeep Paulraj358934a2009-12-16 22:02:18 +0000973free_clk:
974 clk_disable(davinci_spi->clk);
975 clk_put(davinci_spi->clk);
976put_master:
977 spi_master_put(master);
Brian Niebuhre0d205e2010-09-02 16:52:06 +0530978irq_free:
979 free_irq(davinci_spi->irq, davinci_spi);
Sandeep Paulraj358934a2009-12-16 22:02:18 +0000980unmap_io:
981 iounmap(davinci_spi->base);
982release_region:
983 release_mem_region(davinci_spi->pbase, davinci_spi->region_size);
984free_master:
985 kfree(master);
986err:
987 return ret;
988}
989
990/**
991 * davinci_spi_remove - remove function for SPI Master Controller
992 * @pdev: platform_device structure which contains plateform specific data
993 *
994 * This function will do the reverse action of davinci_spi_probe function
995 * It will free the IRQ and SPI controller's memory region.
996 * It will also call spi_bitbang_stop to destroy the work queue which was
997 * created by spi_bitbang_start.
998 */
999static int __exit davinci_spi_remove(struct platform_device *pdev)
1000{
1001 struct davinci_spi *davinci_spi;
1002 struct spi_master *master;
1003
1004 master = dev_get_drvdata(&pdev->dev);
1005 davinci_spi = spi_master_get_devdata(master);
1006
1007 spi_bitbang_stop(&davinci_spi->bitbang);
1008
1009 clk_disable(davinci_spi->clk);
1010 clk_put(davinci_spi->clk);
1011 spi_master_put(master);
Brian Niebuhre0d205e2010-09-02 16:52:06 +05301012 free_irq(davinci_spi->irq, davinci_spi);
Sandeep Paulraj358934a2009-12-16 22:02:18 +00001013 iounmap(davinci_spi->base);
1014 release_mem_region(davinci_spi->pbase, davinci_spi->region_size);
1015
1016 return 0;
1017}
1018
1019static struct platform_driver davinci_spi_driver = {
1020 .driver.name = "spi_davinci",
1021 .remove = __exit_p(davinci_spi_remove),
1022};
1023
1024static int __init davinci_spi_init(void)
1025{
1026 return platform_driver_probe(&davinci_spi_driver, davinci_spi_probe);
1027}
1028module_init(davinci_spi_init);
1029
1030static void __exit davinci_spi_exit(void)
1031{
1032 platform_driver_unregister(&davinci_spi_driver);
1033}
1034module_exit(davinci_spi_exit);
1035
1036MODULE_DESCRIPTION("TI DaVinci SPI Master Controller Driver");
1037MODULE_LICENSE("GPL");