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Praveen Chidambaram78499012011-11-01 17:15:17 -06001/* Copyright (c) 2012, Code Aurora Forum. All rights reserved.
2 *
3 * This program is free software; you can redistribute it and/or modify
4 * it under the terms of the GNU General Public License version 2 and
5 * only version 2 as published by the Free Software Foundation.
6 *
7 * This program is distributed in the hope that it will be useful,
8 * but WITHOUT ANY WARRANTY; without even the implied warranty of
9 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
10 * GNU General Public License for more details.
11 *
12 */
13
14#include <linux/kernel.h>
15#include <linux/platform_device.h>
Arun Menonaabf2632012-02-24 15:30:47 -080016#include <linux/ion.h>
Praveen Chidambaram78499012011-11-01 17:15:17 -060017#include <mach/msm_iomap.h>
18#include <mach/irqs-8930.h>
19#include <mach/rpm.h>
Praveen Chidambaram5c8adf22012-02-23 18:44:37 -070020#include <mach/msm_dcvs.h>
Arun Menonaabf2632012-02-24 15:30:47 -080021#include <mach/msm_bus.h>
Gagan Maccd5b3272012-02-09 18:13:10 -070022#include <mach/msm_bus_board.h>
Arun Menonaabf2632012-02-24 15:30:47 -080023#include <mach/board.h>
24#include <mach/socinfo.h>
Praveen Chidambaram78499012011-11-01 17:15:17 -060025
26#include "devices.h"
27#include "rpm_log.h"
28#include "rpm_stats.h"
29
30#ifdef CONFIG_MSM_MPM
Subhash Jadavani909e04f2012-04-12 10:52:50 +053031#include <mach/mpm.h>
Praveen Chidambaram78499012011-11-01 17:15:17 -060032#endif
33
34struct msm_rpm_platform_data msm8930_rpm_data __initdata = {
35 .reg_base_addrs = {
36 [MSM_RPM_PAGE_STATUS] = MSM_RPM_BASE,
37 [MSM_RPM_PAGE_CTRL] = MSM_RPM_BASE + 0x400,
38 [MSM_RPM_PAGE_REQ] = MSM_RPM_BASE + 0x600,
39 [MSM_RPM_PAGE_ACK] = MSM_RPM_BASE + 0xa00,
40 },
41 .irq_ack = RPM_APCC_CPU0_GP_HIGH_IRQ,
Stephen Boydf61255e2012-02-24 14:31:09 -080042 .irq_err = RPM_APCC_CPU0_GP_LOW_IRQ,
Praveen Chidambaram78499012011-11-01 17:15:17 -060043 .ipc_rpm_reg = MSM_APCS_GCC_BASE + 0x008,
44 .ipc_rpm_val = 4,
45 .target_id = {
46 MSM_RPM_MAP(8930, NOTIFICATION_CONFIGURED_0, NOTIFICATION, 4),
47 MSM_RPM_MAP(8930, NOTIFICATION_REGISTERED_0, NOTIFICATION, 4),
48 MSM_RPM_MAP(8930, INVALIDATE_0, INVALIDATE, 8),
Mahesh Sivasubramanianef2a0fa2012-01-24 15:57:01 -070049 MSM_RPM_MAP(8960, TRIGGER_TIMED_TO, TRIGGER_TIMED, 1),
50 MSM_RPM_MAP(8960, TRIGGER_TIMED_SCLK_COUNT, TRIGGER_TIMED, 1),
Praveen Chidambaram78499012011-11-01 17:15:17 -060051 MSM_RPM_MAP(8930, RPM_CTL, RPM_CTL, 1),
52 MSM_RPM_MAP(8930, CXO_CLK, CXO_CLK, 1),
53 MSM_RPM_MAP(8930, PXO_CLK, PXO_CLK, 1),
54 MSM_RPM_MAP(8930, APPS_FABRIC_CLK, APPS_FABRIC_CLK, 1),
55 MSM_RPM_MAP(8930, SYSTEM_FABRIC_CLK, SYSTEM_FABRIC_CLK, 1),
56 MSM_RPM_MAP(8930, MM_FABRIC_CLK, MM_FABRIC_CLK, 1),
57 MSM_RPM_MAP(8930, DAYTONA_FABRIC_CLK, DAYTONA_FABRIC_CLK, 1),
58 MSM_RPM_MAP(8930, SFPB_CLK, SFPB_CLK, 1),
59 MSM_RPM_MAP(8930, CFPB_CLK, CFPB_CLK, 1),
60 MSM_RPM_MAP(8930, MMFPB_CLK, MMFPB_CLK, 1),
61 MSM_RPM_MAP(8930, EBI1_CLK, EBI1_CLK, 1),
62 MSM_RPM_MAP(8930, APPS_FABRIC_CFG_HALT_0,
63 APPS_FABRIC_CFG_HALT, 2),
64 MSM_RPM_MAP(8930, APPS_FABRIC_CFG_CLKMOD_0,
65 APPS_FABRIC_CFG_CLKMOD, 3),
66 MSM_RPM_MAP(8930, APPS_FABRIC_CFG_IOCTL,
67 APPS_FABRIC_CFG_IOCTL, 1),
Mahesh Sivasubramanian2d2c70592012-03-20 17:07:24 -060068 MSM_RPM_MAP(8930, APPS_FABRIC_ARB_0, APPS_FABRIC_ARB, 6),
Praveen Chidambaram78499012011-11-01 17:15:17 -060069 MSM_RPM_MAP(8930, SYS_FABRIC_CFG_HALT_0,
70 SYS_FABRIC_CFG_HALT, 2),
71 MSM_RPM_MAP(8930, SYS_FABRIC_CFG_CLKMOD_0,
72 SYS_FABRIC_CFG_CLKMOD, 3),
73 MSM_RPM_MAP(8930, SYS_FABRIC_CFG_IOCTL,
74 SYS_FABRIC_CFG_IOCTL, 1),
75 MSM_RPM_MAP(8930, SYSTEM_FABRIC_ARB_0,
Mahesh Sivasubramanian2d2c70592012-03-20 17:07:24 -060076 SYSTEM_FABRIC_ARB, 20),
Praveen Chidambaram78499012011-11-01 17:15:17 -060077 MSM_RPM_MAP(8930, MMSS_FABRIC_CFG_HALT_0,
78 MMSS_FABRIC_CFG_HALT, 2),
79 MSM_RPM_MAP(8930, MMSS_FABRIC_CFG_CLKMOD_0,
80 MMSS_FABRIC_CFG_CLKMOD, 3),
81 MSM_RPM_MAP(8930, MMSS_FABRIC_CFG_IOCTL,
82 MMSS_FABRIC_CFG_IOCTL, 1),
Mahesh Sivasubramanian2d2c70592012-03-20 17:07:24 -060083 MSM_RPM_MAP(8930, MM_FABRIC_ARB_0, MM_FABRIC_ARB, 11),
Praveen Chidambaram78499012011-11-01 17:15:17 -060084 MSM_RPM_MAP(8930, PM8038_S1_0, PM8038_S1, 2),
85 MSM_RPM_MAP(8930, PM8038_S2_0, PM8038_S2, 2),
86 MSM_RPM_MAP(8930, PM8038_S3_0, PM8038_S3, 2),
87 MSM_RPM_MAP(8930, PM8038_S4_0, PM8038_S4, 2),
88 MSM_RPM_MAP(8930, PM8038_S5_0, PM8038_S5, 2),
89 MSM_RPM_MAP(8930, PM8038_S6_0, PM8038_S6, 2),
90 MSM_RPM_MAP(8930, PM8038_L1_0, PM8038_L1, 2),
91 MSM_RPM_MAP(8930, PM8038_L2_0, PM8038_L2, 2),
92 MSM_RPM_MAP(8930, PM8038_L3_0, PM8038_L3, 2),
93 MSM_RPM_MAP(8930, PM8038_L4_0, PM8038_L4, 2),
94 MSM_RPM_MAP(8930, PM8038_L5_0, PM8038_L5, 2),
95 MSM_RPM_MAP(8930, PM8038_L6_0, PM8038_L6, 2),
96 MSM_RPM_MAP(8930, PM8038_L7_0, PM8038_L7, 2),
97 MSM_RPM_MAP(8930, PM8038_L8_0, PM8038_L8, 2),
98 MSM_RPM_MAP(8930, PM8038_L9_0, PM8038_L9, 2),
99 MSM_RPM_MAP(8930, PM8038_L10_0, PM8038_L10, 2),
100 MSM_RPM_MAP(8930, PM8038_L11_0, PM8038_L11, 2),
101 MSM_RPM_MAP(8930, PM8038_L12_0, PM8038_L12, 2),
102 MSM_RPM_MAP(8930, PM8038_L13_0, PM8038_L13, 2),
103 MSM_RPM_MAP(8930, PM8038_L14_0, PM8038_L14, 2),
104 MSM_RPM_MAP(8930, PM8038_L15_0, PM8038_L15, 2),
105 MSM_RPM_MAP(8930, PM8038_L16_0, PM8038_L16, 2),
106 MSM_RPM_MAP(8930, PM8038_L17_0, PM8038_L17, 2),
107 MSM_RPM_MAP(8930, PM8038_L18_0, PM8038_L18, 2),
108 MSM_RPM_MAP(8930, PM8038_L19_0, PM8038_L19, 2),
109 MSM_RPM_MAP(8930, PM8038_L20_0, PM8038_L20, 2),
110 MSM_RPM_MAP(8930, PM8038_L21_0, PM8038_L21, 2),
111 MSM_RPM_MAP(8930, PM8038_L22_0, PM8038_L22, 2),
112 MSM_RPM_MAP(8930, PM8038_L23_0, PM8038_L23, 2),
113 MSM_RPM_MAP(8930, PM8038_L24_0, PM8038_L24, 2),
114 MSM_RPM_MAP(8930, PM8038_L25_0, PM8038_L25, 2),
115 MSM_RPM_MAP(8930, PM8038_L26_0, PM8038_L26, 2),
116 MSM_RPM_MAP(8930, PM8038_L27_0, PM8038_L27, 2),
117 MSM_RPM_MAP(8930, PM8038_CLK1_0, PM8038_CLK1, 2),
118 MSM_RPM_MAP(8930, PM8038_CLK2_0, PM8038_CLK2, 2),
119 MSM_RPM_MAP(8930, PM8038_LVS1, PM8038_LVS1, 1),
120 MSM_RPM_MAP(8930, PM8038_LVS2, PM8038_LVS2, 1),
121 MSM_RPM_MAP(8930, NCP_0, NCP, 2),
122 MSM_RPM_MAP(8930, CXO_BUFFERS, CXO_BUFFERS, 1),
123 MSM_RPM_MAP(8930, USB_OTG_SWITCH, USB_OTG_SWITCH, 1),
124 MSM_RPM_MAP(8930, HDMI_SWITCH, HDMI_SWITCH, 1),
125 MSM_RPM_MAP(8930, QDSS_CLK, QDSS_CLK, 1),
Mahesh Sivasubramanian9e52ce42012-02-01 16:00:19 -0700126 MSM_RPM_MAP(8930, VOLTAGE_CORNER, VOLTAGE_CORNER, 1),
Praveen Chidambaram78499012011-11-01 17:15:17 -0600127 },
128 .target_status = {
129 MSM_RPM_STATUS_ID_MAP(8930, VERSION_MAJOR),
130 MSM_RPM_STATUS_ID_MAP(8930, VERSION_MINOR),
131 MSM_RPM_STATUS_ID_MAP(8930, VERSION_BUILD),
132 MSM_RPM_STATUS_ID_MAP(8930, SUPPORTED_RESOURCES_0),
133 MSM_RPM_STATUS_ID_MAP(8930, SUPPORTED_RESOURCES_1),
134 MSM_RPM_STATUS_ID_MAP(8930, SUPPORTED_RESOURCES_2),
135 MSM_RPM_STATUS_ID_MAP(8930, RESERVED_SUPPORTED_RESOURCES_0),
136 MSM_RPM_STATUS_ID_MAP(8930, SEQUENCE),
137 MSM_RPM_STATUS_ID_MAP(8930, RPM_CTL),
138 MSM_RPM_STATUS_ID_MAP(8930, CXO_CLK),
139 MSM_RPM_STATUS_ID_MAP(8930, PXO_CLK),
140 MSM_RPM_STATUS_ID_MAP(8930, APPS_FABRIC_CLK),
141 MSM_RPM_STATUS_ID_MAP(8930, SYSTEM_FABRIC_CLK),
142 MSM_RPM_STATUS_ID_MAP(8930, MM_FABRIC_CLK),
143 MSM_RPM_STATUS_ID_MAP(8930, DAYTONA_FABRIC_CLK),
144 MSM_RPM_STATUS_ID_MAP(8930, SFPB_CLK),
145 MSM_RPM_STATUS_ID_MAP(8930, CFPB_CLK),
146 MSM_RPM_STATUS_ID_MAP(8930, MMFPB_CLK),
147 MSM_RPM_STATUS_ID_MAP(8930, EBI1_CLK),
148 MSM_RPM_STATUS_ID_MAP(8930, APPS_FABRIC_CFG_HALT),
149 MSM_RPM_STATUS_ID_MAP(8930, APPS_FABRIC_CFG_CLKMOD),
150 MSM_RPM_STATUS_ID_MAP(8930, APPS_FABRIC_CFG_IOCTL),
151 MSM_RPM_STATUS_ID_MAP(8930, APPS_FABRIC_ARB),
152 MSM_RPM_STATUS_ID_MAP(8930, SYS_FABRIC_CFG_HALT),
153 MSM_RPM_STATUS_ID_MAP(8930, SYS_FABRIC_CFG_CLKMOD),
154 MSM_RPM_STATUS_ID_MAP(8930, SYS_FABRIC_CFG_IOCTL),
155 MSM_RPM_STATUS_ID_MAP(8930, SYSTEM_FABRIC_ARB),
156 MSM_RPM_STATUS_ID_MAP(8930, MMSS_FABRIC_CFG_HALT),
157 MSM_RPM_STATUS_ID_MAP(8930, MMSS_FABRIC_CFG_CLKMOD),
158 MSM_RPM_STATUS_ID_MAP(8930, MMSS_FABRIC_CFG_IOCTL),
159 MSM_RPM_STATUS_ID_MAP(8930, MM_FABRIC_ARB),
160 MSM_RPM_STATUS_ID_MAP(8930, PM8038_S1_0),
161 MSM_RPM_STATUS_ID_MAP(8930, PM8038_S1_1),
162 MSM_RPM_STATUS_ID_MAP(8930, PM8038_S2_0),
163 MSM_RPM_STATUS_ID_MAP(8930, PM8038_S2_1),
164 MSM_RPM_STATUS_ID_MAP(8930, PM8038_S3_0),
165 MSM_RPM_STATUS_ID_MAP(8930, PM8038_S3_1),
166 MSM_RPM_STATUS_ID_MAP(8930, PM8038_S4_0),
167 MSM_RPM_STATUS_ID_MAP(8930, PM8038_S4_1),
168 MSM_RPM_STATUS_ID_MAP(8930, PM8038_L1_0),
169 MSM_RPM_STATUS_ID_MAP(8930, PM8038_L1_1),
170 MSM_RPM_STATUS_ID_MAP(8930, PM8038_L2_0),
171 MSM_RPM_STATUS_ID_MAP(8930, PM8038_L2_1),
172 MSM_RPM_STATUS_ID_MAP(8930, PM8038_L3_0),
173 MSM_RPM_STATUS_ID_MAP(8930, PM8038_L3_1),
174 MSM_RPM_STATUS_ID_MAP(8930, PM8038_L4_0),
175 MSM_RPM_STATUS_ID_MAP(8930, PM8038_L4_1),
176 MSM_RPM_STATUS_ID_MAP(8930, PM8038_L5_0),
177 MSM_RPM_STATUS_ID_MAP(8930, PM8038_L5_1),
178 MSM_RPM_STATUS_ID_MAP(8930, PM8038_L6_0),
179 MSM_RPM_STATUS_ID_MAP(8930, PM8038_L6_1),
180 MSM_RPM_STATUS_ID_MAP(8930, PM8038_L7_0),
181 MSM_RPM_STATUS_ID_MAP(8930, PM8038_L7_1),
182 MSM_RPM_STATUS_ID_MAP(8930, PM8038_L8_0),
183 MSM_RPM_STATUS_ID_MAP(8930, PM8038_L8_1),
184 MSM_RPM_STATUS_ID_MAP(8930, PM8038_L9_0),
185 MSM_RPM_STATUS_ID_MAP(8930, PM8038_L9_1),
186 MSM_RPM_STATUS_ID_MAP(8930, PM8038_L10_0),
187 MSM_RPM_STATUS_ID_MAP(8930, PM8038_L10_1),
188 MSM_RPM_STATUS_ID_MAP(8930, PM8038_L11_0),
189 MSM_RPM_STATUS_ID_MAP(8930, PM8038_L11_1),
190 MSM_RPM_STATUS_ID_MAP(8930, PM8038_L12_0),
191 MSM_RPM_STATUS_ID_MAP(8930, PM8038_L12_1),
192 MSM_RPM_STATUS_ID_MAP(8930, PM8038_L13_0),
193 MSM_RPM_STATUS_ID_MAP(8930, PM8038_L13_1),
194 MSM_RPM_STATUS_ID_MAP(8930, PM8038_L14_0),
195 MSM_RPM_STATUS_ID_MAP(8930, PM8038_L14_1),
196 MSM_RPM_STATUS_ID_MAP(8930, PM8038_L15_0),
197 MSM_RPM_STATUS_ID_MAP(8930, PM8038_L15_1),
198 MSM_RPM_STATUS_ID_MAP(8930, PM8038_L16_0),
199 MSM_RPM_STATUS_ID_MAP(8930, PM8038_L16_1),
200 MSM_RPM_STATUS_ID_MAP(8930, PM8038_L17_0),
201 MSM_RPM_STATUS_ID_MAP(8930, PM8038_L17_1),
202 MSM_RPM_STATUS_ID_MAP(8930, PM8038_L18_0),
203 MSM_RPM_STATUS_ID_MAP(8930, PM8038_L18_1),
204 MSM_RPM_STATUS_ID_MAP(8930, PM8038_L19_0),
205 MSM_RPM_STATUS_ID_MAP(8930, PM8038_L19_1),
206 MSM_RPM_STATUS_ID_MAP(8930, PM8038_L20_0),
207 MSM_RPM_STATUS_ID_MAP(8930, PM8038_L20_1),
208 MSM_RPM_STATUS_ID_MAP(8930, PM8038_L21_0),
209 MSM_RPM_STATUS_ID_MAP(8930, PM8038_L21_1),
210 MSM_RPM_STATUS_ID_MAP(8930, PM8038_L22_0),
211 MSM_RPM_STATUS_ID_MAP(8930, PM8038_L22_1),
212 MSM_RPM_STATUS_ID_MAP(8930, PM8038_L23_0),
213 MSM_RPM_STATUS_ID_MAP(8930, PM8038_L23_1),
214 MSM_RPM_STATUS_ID_MAP(8930, PM8038_L24_0),
215 MSM_RPM_STATUS_ID_MAP(8930, PM8038_L24_1),
216 MSM_RPM_STATUS_ID_MAP(8930, PM8038_L25_0),
217 MSM_RPM_STATUS_ID_MAP(8930, PM8038_L25_1),
218 MSM_RPM_STATUS_ID_MAP(8930, PM8038_CLK1_0),
219 MSM_RPM_STATUS_ID_MAP(8930, PM8038_CLK1_1),
220 MSM_RPM_STATUS_ID_MAP(8930, PM8038_CLK2_0),
221 MSM_RPM_STATUS_ID_MAP(8930, PM8038_CLK2_1),
222 MSM_RPM_STATUS_ID_MAP(8930, PM8038_LVS1),
223 MSM_RPM_STATUS_ID_MAP(8930, PM8038_LVS2),
224 MSM_RPM_STATUS_ID_MAP(8930, NCP_0),
225 MSM_RPM_STATUS_ID_MAP(8930, NCP_1),
226 MSM_RPM_STATUS_ID_MAP(8930, CXO_BUFFERS),
227 MSM_RPM_STATUS_ID_MAP(8930, USB_OTG_SWITCH),
228 MSM_RPM_STATUS_ID_MAP(8930, HDMI_SWITCH),
Mahesh Sivasubramanianef2a0fa2012-01-24 15:57:01 -0700229 MSM_RPM_STATUS_ID_MAP(8930, QDSS_CLK),
Mahesh Sivasubramanian9e52ce42012-02-01 16:00:19 -0700230 MSM_RPM_STATUS_ID_MAP(8930, VOLTAGE_CORNER),
Praveen Chidambaram78499012011-11-01 17:15:17 -0600231 },
232 .target_ctrl_id = {
233 MSM_RPM_CTRL_MAP(8930, VERSION_MAJOR),
234 MSM_RPM_CTRL_MAP(8930, VERSION_MINOR),
235 MSM_RPM_CTRL_MAP(8930, VERSION_BUILD),
236 MSM_RPM_CTRL_MAP(8930, REQ_CTX_0),
237 MSM_RPM_CTRL_MAP(8930, REQ_SEL_0),
238 MSM_RPM_CTRL_MAP(8930, ACK_CTX_0),
239 MSM_RPM_CTRL_MAP(8930, ACK_SEL_0),
240 },
241 .sel_invalidate = MSM_RPM_8930_SEL_INVALIDATE,
242 .sel_notification = MSM_RPM_8930_SEL_NOTIFICATION,
243 .sel_last = MSM_RPM_8930_SEL_LAST,
244 .ver = {3, 0, 0},
245};
246
247struct platform_device msm8930_rpm_device = {
248 .name = "msm_rpm",
249 .id = -1,
250};
251
252static struct msm_rpm_log_platform_data msm_rpm_log_pdata = {
253 .phys_addr_base = 0x0010C000,
254 .reg_offsets = {
255 [MSM_RPM_LOG_PAGE_INDICES] = 0x00000080,
256 [MSM_RPM_LOG_PAGE_BUFFER] = 0x000000A0,
257 },
258 .phys_size = SZ_8K,
259 .log_len = 4096, /* log's buffer length in bytes */
260 .log_len_mask = (4096 >> 2) - 1, /* length mask in units of u32 */
261};
262
263struct platform_device msm8930_rpm_log_device = {
264 .name = "msm_rpm_log",
265 .id = -1,
266 .dev = {
267 .platform_data = &msm_rpm_log_pdata,
268 },
269};
270
271static struct msm_rpmstats_platform_data msm_rpm_stat_pdata = {
272 .phys_addr_base = 0x0010D204,
273 .phys_size = SZ_8K,
274};
275
276struct platform_device msm8930_rpm_stat_device = {
277 .name = "msm_rpm_stat",
278 .id = -1,
279 .dev = {
280 .platform_data = &msm_rpm_stat_pdata,
281 },
282};
283
Praveen Chidambaram8ea3dcd2011-12-07 14:46:31 -0700284static int msm8930_LPM_latency = 1000; /* >100 usec for WFI */
285
286struct platform_device msm8930_cpu_idle_device = {
287 .name = "msm_cpu_idle",
288 .id = -1,
289 .dev = {
290 .platform_data = &msm8930_LPM_latency,
291 },
292};
Praveen Chidambaram5c8adf22012-02-23 18:44:37 -0700293
294static struct msm_dcvs_freq_entry msm8930_freq[] = {
295 { 384000, 166981, 345600},
296 { 702000, 213049, 632502},
297 {1026000, 285712, 925613},
298 {1242000, 383945, 1176550},
299 {1458000, 419729, 1465478},
300 {1512000, 434116, 1546674},
301
302};
303
304static struct msm_dcvs_core_info msm8930_core_info = {
305 .freq_tbl = &msm8930_freq[0],
306 .core_param = {
307 .max_time_us = 100000,
308 .num_freq = ARRAY_SIZE(msm8930_freq),
309 },
310 .algo_param = {
311 .slack_time_us = 58000,
312 .scale_slack_time = 0,
313 .scale_slack_time_pct = 0,
314 .disable_pc_threshold = 1458000,
315 .em_window_size = 100000,
316 .em_max_util_pct = 97,
317 .ss_window_size = 1000000,
318 .ss_util_pct = 95,
319 .ss_iobusy_conv = 100,
320 },
321};
322
323struct platform_device msm8930_msm_gov_device = {
324 .name = "msm_dcvs_gov",
325 .id = -1,
326 .dev = {
327 .platform_data = &msm8930_core_info,
328 },
329};
Gagan Maccd5b3272012-02-09 18:13:10 -0700330
331struct platform_device msm_bus_8930_sys_fabric = {
332 .name = "msm_bus_fabric",
333 .id = MSM_BUS_FAB_SYSTEM,
334};
335struct platform_device msm_bus_8930_apps_fabric = {
336 .name = "msm_bus_fabric",
337 .id = MSM_BUS_FAB_APPSS,
338};
339struct platform_device msm_bus_8930_mm_fabric = {
340 .name = "msm_bus_fabric",
341 .id = MSM_BUS_FAB_MMSS,
342};
343struct platform_device msm_bus_8930_sys_fpb = {
344 .name = "msm_bus_fabric",
345 .id = MSM_BUS_FAB_SYSTEM_FPB,
346};
347struct platform_device msm_bus_8930_cpss_fpb = {
348 .name = "msm_bus_fabric",
349 .id = MSM_BUS_FAB_CPSS_FPB,
350};
351
Arun Menonaabf2632012-02-24 15:30:47 -0800352/* MSM Video core device */
353#ifdef CONFIG_MSM_BUS_SCALING
354static struct msm_bus_vectors vidc_init_vectors[] = {
355 {
356 .src = MSM_BUS_MASTER_HD_CODEC_PORT0,
357 .dst = MSM_BUS_SLAVE_EBI_CH0,
358 .ab = 0,
359 .ib = 0,
360 },
361 {
362 .src = MSM_BUS_MASTER_HD_CODEC_PORT1,
363 .dst = MSM_BUS_SLAVE_EBI_CH0,
364 .ab = 0,
365 .ib = 0,
366 },
367 {
368 .src = MSM_BUS_MASTER_AMPSS_M0,
369 .dst = MSM_BUS_SLAVE_EBI_CH0,
370 .ab = 0,
371 .ib = 0,
372 },
373 {
374 .src = MSM_BUS_MASTER_AMPSS_M0,
375 .dst = MSM_BUS_SLAVE_EBI_CH0,
376 .ab = 0,
377 .ib = 0,
378 },
379};
380static struct msm_bus_vectors vidc_venc_vga_vectors[] = {
381 {
382 .src = MSM_BUS_MASTER_HD_CODEC_PORT0,
383 .dst = MSM_BUS_SLAVE_EBI_CH0,
384 .ab = 54525952,
385 .ib = 436207616,
386 },
387 {
388 .src = MSM_BUS_MASTER_HD_CODEC_PORT1,
389 .dst = MSM_BUS_SLAVE_EBI_CH0,
390 .ab = 72351744,
391 .ib = 289406976,
392 },
393 {
394 .src = MSM_BUS_MASTER_AMPSS_M0,
395 .dst = MSM_BUS_SLAVE_EBI_CH0,
396 .ab = 500000,
397 .ib = 1000000,
398 },
399 {
400 .src = MSM_BUS_MASTER_AMPSS_M0,
401 .dst = MSM_BUS_SLAVE_EBI_CH0,
402 .ab = 500000,
403 .ib = 1000000,
404 },
405};
406static struct msm_bus_vectors vidc_vdec_vga_vectors[] = {
407 {
408 .src = MSM_BUS_MASTER_HD_CODEC_PORT0,
409 .dst = MSM_BUS_SLAVE_EBI_CH0,
410 .ab = 40894464,
411 .ib = 327155712,
412 },
413 {
414 .src = MSM_BUS_MASTER_HD_CODEC_PORT1,
415 .dst = MSM_BUS_SLAVE_EBI_CH0,
416 .ab = 48234496,
417 .ib = 192937984,
418 },
419 {
420 .src = MSM_BUS_MASTER_AMPSS_M0,
421 .dst = MSM_BUS_SLAVE_EBI_CH0,
422 .ab = 500000,
423 .ib = 2000000,
424 },
425 {
426 .src = MSM_BUS_MASTER_AMPSS_M0,
427 .dst = MSM_BUS_SLAVE_EBI_CH0,
428 .ab = 500000,
429 .ib = 2000000,
430 },
431};
432static struct msm_bus_vectors vidc_venc_720p_vectors[] = {
433 {
434 .src = MSM_BUS_MASTER_HD_CODEC_PORT0,
435 .dst = MSM_BUS_SLAVE_EBI_CH0,
436 .ab = 163577856,
437 .ib = 1308622848,
438 },
439 {
440 .src = MSM_BUS_MASTER_HD_CODEC_PORT1,
441 .dst = MSM_BUS_SLAVE_EBI_CH0,
442 .ab = 219152384,
443 .ib = 876609536,
444 },
445 {
446 .src = MSM_BUS_MASTER_AMPSS_M0,
447 .dst = MSM_BUS_SLAVE_EBI_CH0,
448 .ab = 1750000,
449 .ib = 3500000,
450 },
451 {
452 .src = MSM_BUS_MASTER_AMPSS_M0,
453 .dst = MSM_BUS_SLAVE_EBI_CH0,
454 .ab = 1750000,
455 .ib = 3500000,
456 },
457};
458static struct msm_bus_vectors vidc_vdec_720p_vectors[] = {
459 {
460 .src = MSM_BUS_MASTER_HD_CODEC_PORT0,
461 .dst = MSM_BUS_SLAVE_EBI_CH0,
462 .ab = 121634816,
463 .ib = 973078528,
464 },
465 {
466 .src = MSM_BUS_MASTER_HD_CODEC_PORT1,
467 .dst = MSM_BUS_SLAVE_EBI_CH0,
468 .ab = 155189248,
469 .ib = 620756992,
470 },
471 {
472 .src = MSM_BUS_MASTER_AMPSS_M0,
473 .dst = MSM_BUS_SLAVE_EBI_CH0,
474 .ab = 1750000,
475 .ib = 7000000,
476 },
477 {
478 .src = MSM_BUS_MASTER_AMPSS_M0,
479 .dst = MSM_BUS_SLAVE_EBI_CH0,
480 .ab = 1750000,
481 .ib = 7000000,
482 },
483};
484static struct msm_bus_vectors vidc_venc_1080p_vectors[] = {
485 {
486 .src = MSM_BUS_MASTER_HD_CODEC_PORT0,
487 .dst = MSM_BUS_SLAVE_EBI_CH0,
488 .ab = 372244480,
489 .ib = 2560000000U,
490 },
491 {
492 .src = MSM_BUS_MASTER_HD_CODEC_PORT1,
493 .dst = MSM_BUS_SLAVE_EBI_CH0,
494 .ab = 501219328,
495 .ib = 2560000000U,
496 },
497 {
498 .src = MSM_BUS_MASTER_AMPSS_M0,
499 .dst = MSM_BUS_SLAVE_EBI_CH0,
500 .ab = 2500000,
501 .ib = 5000000,
502 },
503 {
504 .src = MSM_BUS_MASTER_AMPSS_M0,
505 .dst = MSM_BUS_SLAVE_EBI_CH0,
506 .ab = 2500000,
507 .ib = 5000000,
508 },
509};
510static struct msm_bus_vectors vidc_vdec_1080p_vectors[] = {
511 {
512 .src = MSM_BUS_MASTER_HD_CODEC_PORT0,
513 .dst = MSM_BUS_SLAVE_EBI_CH0,
514 .ab = 222298112,
515 .ib = 2560000000U,
516 },
517 {
518 .src = MSM_BUS_MASTER_HD_CODEC_PORT1,
519 .dst = MSM_BUS_SLAVE_EBI_CH0,
520 .ab = 330301440,
521 .ib = 2560000000U,
522 },
523 {
524 .src = MSM_BUS_MASTER_AMPSS_M0,
525 .dst = MSM_BUS_SLAVE_EBI_CH0,
526 .ab = 2500000,
527 .ib = 700000000,
528 },
529 {
530 .src = MSM_BUS_MASTER_AMPSS_M0,
531 .dst = MSM_BUS_SLAVE_EBI_CH0,
532 .ab = 2500000,
533 .ib = 10000000,
534 },
535};
536
537static struct msm_bus_paths vidc_bus_client_config[] = {
538 {
539 ARRAY_SIZE(vidc_init_vectors),
540 vidc_init_vectors,
541 },
542 {
543 ARRAY_SIZE(vidc_venc_vga_vectors),
544 vidc_venc_vga_vectors,
545 },
546 {
547 ARRAY_SIZE(vidc_vdec_vga_vectors),
548 vidc_vdec_vga_vectors,
549 },
550 {
551 ARRAY_SIZE(vidc_venc_720p_vectors),
552 vidc_venc_720p_vectors,
553 },
554 {
555 ARRAY_SIZE(vidc_vdec_720p_vectors),
556 vidc_vdec_720p_vectors,
557 },
558 {
559 ARRAY_SIZE(vidc_venc_1080p_vectors),
560 vidc_venc_1080p_vectors,
561 },
562 {
563 ARRAY_SIZE(vidc_vdec_1080p_vectors),
564 vidc_vdec_1080p_vectors,
565 },
566};
567
568static struct msm_bus_scale_pdata vidc_bus_client_data = {
569 vidc_bus_client_config,
570 ARRAY_SIZE(vidc_bus_client_config),
571 .name = "vidc",
572};
573#endif
574
575#define MSM_VIDC_BASE_PHYS 0x04400000
576#define MSM_VIDC_BASE_SIZE 0x00100000
577
578static struct resource apq8930_device_vidc_resources[] = {
579 {
580 .start = MSM_VIDC_BASE_PHYS,
581 .end = MSM_VIDC_BASE_PHYS + MSM_VIDC_BASE_SIZE - 1,
582 .flags = IORESOURCE_MEM,
583 },
584 {
585 .start = VCODEC_IRQ,
586 .end = VCODEC_IRQ,
587 .flags = IORESOURCE_IRQ,
588 },
589};
590
591struct msm_vidc_platform_data apq8930_vidc_platform_data = {
592#ifdef CONFIG_MSM_BUS_SCALING
593 .vidc_bus_client_pdata = &vidc_bus_client_data,
594#endif
595#ifdef CONFIG_MSM_MULTIMEDIA_USE_ION
596 .memtype = ION_CP_MM_HEAP_ID,
597 .enable_ion = 1,
598#else
599 .memtype = MEMTYPE_EBI1,
600 .enable_ion = 0,
601#endif
602 .disable_dmx = 0,
603 .disable_fullhd = 0,
604};
605
606struct platform_device apq8930_msm_device_vidc = {
607 .name = "msm_vidc",
608 .id = 0,
609 .num_resources = ARRAY_SIZE(apq8930_device_vidc_resources),
610 .resource = apq8930_device_vidc_resources,
611 .dev = {
612 .platform_data = &apq8930_vidc_platform_data,
613 },
614};
615
616struct platform_device *vidc_device[] __initdata = {
617 &apq8930_msm_device_vidc
618};
619
620void __init msm8930_add_vidc_device(void)
621{
622 if (cpu_is_msm8627()) {
623 struct msm_vidc_platform_data *pdata;
624 pdata = (struct msm_vidc_platform_data *)
625 apq8930_msm_device_vidc.dev.platform_data;
626 pdata->disable_fullhd = 1;
627 }
628 platform_add_devices(vidc_device, ARRAY_SIZE(vidc_device));
629}